.. | .. |
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274 | 274 | .confops = &foo_pconf_ops, |
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275 | 275 | }; |
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276 | 276 | |
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277 | | -Since some controllers have special logic for handling entire groups of pins |
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278 | | -they can exploit the special whole-group pin control function. The |
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279 | | -pin_config_group_set() callback is allowed to return the error code -EAGAIN, |
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280 | | -for groups it does not want to handle, or if it just wants to do some |
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281 | | -group-level handling and then fall through to iterate over all pins, in which |
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282 | | -case each individual pin will be treated by separate pin_config_set() calls as |
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283 | | -well. |
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284 | | - |
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285 | | - |
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286 | 277 | Interaction with the GPIO subsystem |
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287 | 278 | =================================== |
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288 | 279 | |
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.. | .. |
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647 | 638 | } |
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648 | 639 | |
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649 | 640 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, |
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650 | | - unsigned ** const pins, |
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651 | | - unsigned * const num_pins) |
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| 641 | + const unsigned ** pins, |
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| 642 | + unsigned * num_pins) |
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652 | 643 | { |
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653 | 644 | *pins = (unsigned *) foo_groups[selector].pins; |
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654 | 645 | *num_pins = foo_groups[selector].num_pins; |
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.. | .. |
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714 | 705 | { |
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715 | 706 | u8 regbit = (1 << selector + group); |
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716 | 707 | |
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717 | | - writeb((readb(MUX)|regbit), MUX) |
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| 708 | + writeb((readb(MUX)|regbit), MUX); |
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718 | 709 | return 0; |
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719 | 710 | } |
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720 | 711 | |
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