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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/tools/arch/x86/include/asm/cpufeatures.h
....@@ -13,8 +13,8 @@
1313 /*
1414  * Defines x86 CPU feature bits
1515  */
16
-#define NCAPINTS			19	   /* N 32-bit words worth of info */
17
-#define NBUGINTS			1	   /* N 32-bit bug flags */
16
+#define NCAPINTS			20	   /* N 32-bit words worth of info */
17
+#define NBUGINTS			2	   /* N 32-bit bug flags */
1818 
1919 /*
2020  * Note: If the comment begins with a quoted string, that string is used
....@@ -96,7 +96,7 @@
9696 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
9797 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
9898 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
99
-#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */
99
+/* FREE!                                ( 3*32+17) */
100100 #define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */
101101 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
102102 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
....@@ -201,7 +201,7 @@
201201 #define X86_FEATURE_INVPCID_SINGLE	( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
202202 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
203203 #define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */
204
-#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */
204
+/* FREE!                                ( 7*32+10) */
205205 #define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */
206206 #define X86_FEATURE_KERNEL_IBRS		( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
207207 #define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
....@@ -211,7 +211,7 @@
211211 #define X86_FEATURE_SSBD		( 7*32+17) /* Speculative Store Bypass Disable */
212212 #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
213213 #define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */
214
-#define X86_FEATURE_SEV			( 7*32+20) /* AMD Secure Encrypted Virtualization */
214
+/* FREE!                                ( 7*32+20) */
215215 #define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
216216 #define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */
217217 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */
....@@ -236,7 +236,6 @@
236236 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
237237 #define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
238238 #define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
239
-#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
240239 
241240 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
242241 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
....@@ -299,6 +298,7 @@
299298 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */
300299 
301300 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
301
+#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
302302 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
303303 
304304 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
....@@ -343,6 +343,7 @@
343343 #define X86_FEATURE_AVIC		(15*32+13) /* Virtual Interrupt Controller */
344344 #define X86_FEATURE_V_VMSAVE_VMLOAD	(15*32+15) /* Virtual VMSAVE VMLOAD */
345345 #define X86_FEATURE_VGIF		(15*32+16) /* Virtual GIF */
346
+#define X86_FEATURE_SVME_ADDR_CHK	(15*32+28) /* "" SVME addr check */
346347 
347348 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
348349 #define X86_FEATURE_AVX512VBMI		(16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
....@@ -389,6 +390,13 @@
389390 #define X86_FEATURE_CORE_CAPABILITIES	(18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
390391 #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
391392 
393
+/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
394
+#define X86_FEATURE_SME			(19*32+ 0) /* AMD Secure Memory Encryption */
395
+#define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
396
+#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
397
+#define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
398
+#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
399
+
392400 /*
393401  * BUG word(s)
394402  */