update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/sound/soc/rockchip/rockchip_i2s.h
..
..
@@ -18,8 +18,9 @@
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 #define I2S_TXCR_RCNT_SHIFT	17
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 #define I2S_TXCR_RCNT_MASK	(0x3f << I2S_TXCR_RCNT_SHIFT)
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 #define I2S_TXCR_CSR_SHIFT	15
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-#define I2S_TXCR_CSR(x)		(x << I2S_TXCR_CSR_SHIFT)
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 #define I2S_TXCR_CSR_MASK	(3 << I2S_TXCR_CSR_SHIFT)
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+#define I2S_TXCR_CSR(x)		(x << I2S_TXCR_CSR_SHIFT)
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+#define I2S_TXCR_CSR_V(v)	((((v) & I2S_TXCR_CSR_MASK) >> 15) + 1)
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 #define I2S_TXCR_HWT		BIT(14)
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 #define I2S_TXCR_SJM_SHIFT	12
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 #define I2S_TXCR_SJM_R		(0 << I2S_TXCR_SJM_SHIFT)
..
..
@@ -48,8 +49,9 @@
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  * receive operation control register
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 */
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 #define I2S_RXCR_CSR_SHIFT	15
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-#define I2S_RXCR_CSR(x)		(x << I2S_RXCR_CSR_SHIFT)
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 #define I2S_RXCR_CSR_MASK	(3 << I2S_RXCR_CSR_SHIFT)
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+#define I2S_RXCR_CSR(x)		(x << I2S_RXCR_CSR_SHIFT)
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+#define I2S_RXCR_CSR_V(v)	((((v) & I2S_RXCR_CSR_MASK) >> 15) + 1)
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 #define I2S_RXCR_HWT		BIT(14)
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 #define I2S_RXCR_SJM_SHIFT	12
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 #define I2S_RXCR_SJM_R		(0 << I2S_RXCR_SJM_SHIFT)
..
..
@@ -132,14 +134,16 @@
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 #define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
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 #define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
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 #define I2S_DMACR_RDL_SHIFT	16
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-#define I2S_DMACR_RDL(x)	((x - 1) << I2S_DMACR_RDL_SHIFT)
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 #define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
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+#define I2S_DMACR_RDL(x)	((x - 1) << I2S_DMACR_RDL_SHIFT)
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+#define I2S_DMACR_RDL_V(v)	((((v) & I2S_DMACR_RDL_MASK) >> 16) + 1)
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 #define I2S_DMACR_TDE_SHIFT	8
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 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
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 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
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 #define I2S_DMACR_TDL_SHIFT	0
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-#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
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 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
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+#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
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+#define I2S_DMACR_TDL_V(v)	(((v) & I2S_DMACR_TDL_MASK) >> 0)
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 /*
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  * INTCR
..
..
@@ -229,7 +233,7 @@
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 #define I2S_TXCR	(0x0000)
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 #define I2S_RXCR	(0x0004)
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 #define I2S_CKR		(0x0008)
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-#define I2S_FIFOLR	(0x000c)
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+#define I2S_TXFIFOLR	(0x000c)
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 #define I2S_DMACR	(0x0010)
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 #define I2S_INTCR	(0x0014)
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 #define I2S_INTSR	(0x0018)
..
..
@@ -237,6 +241,7 @@
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 #define I2S_CLR		(0x0020)
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 #define I2S_TXDR	(0x0024)
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 #define I2S_RXDR	(0x0028)
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+#define I2S_RXFIFOLR	(0x002c)
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 /* io direction cfg register */
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 #define I2S_IO_DIRECTION_MASK	(7)
..
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@@ -245,4 +250,11 @@
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 #define I2S_IO_4CH_OUT_6CH_IN	(6)
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 #define I2S_IO_2CH_OUT_8CH_IN	(7)
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+/* XFL4 is compatible for old version */
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+#define I2S_FIFOLR_XFL4(v)	(((v) & GENMASK(29, 24)) >> 24)
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+#define I2S_FIFOLR_XFL3(v)	(((v) & GENMASK(23, 18)) >> 18)
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+#define I2S_FIFOLR_XFL2(v)	(((v) & GENMASK(17, 12)) >> 12)
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+#define I2S_FIFOLR_XFL1(v)	(((v) & GENMASK(11, 6)) >> 6)
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+#define I2S_FIFOLR_XFL0(v)	(((v) & GENMASK(5, 0)) >> 0)
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+
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 #endif /* _ROCKCHIP_IIS_H */