update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/sound/soc/meson/axg-tdm-formatter.c
..
..
@@ -30,27 +30,32 @@
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 					struct axg_tdm_stream *ts,
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 					unsigned int offset)
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 {
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-	unsigned int val, ch = ts->channels;
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-	unsigned long mask;
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-	int i, j;
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+	unsigned int ch = ts->channels;
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+	u32 val[AXG_TDM_NUM_LANES];
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+	int i, j, k;
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+
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+	/*
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+	 * We need to mimick the slot distribution used by the HW to keep the
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+	 * channel placement consistent regardless of the number of channel
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+	 * in the stream. This is why the odd algorithm below is used.
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+	 */
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+	memset(val, 0, sizeof(*val) * AXG_TDM_NUM_LANES);
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 	/*
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 	 * Distribute the channels of the stream over the available slots
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-	 * of each TDM lane
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+	 * of each TDM lane. We need to go over the 32 slots ...
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 	 */
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-	for (i = 0; i < AXG_TDM_NUM_LANES; i++) {
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-		val = 0;
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-		mask = ts->mask[i];
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-
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-		for (j = find_first_bit(&mask, 32);
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-		     (j < 32) && ch;
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-		     j = find_next_bit(&mask, 32, j + 1)) {
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-			val |= 1 << j;
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-			ch -= 1;
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+	for (i = 0; (i < 32) && ch; i += 2) {
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+		/* ... of all the lanes ... */
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+		for (j = 0; j < AXG_TDM_NUM_LANES; j++) {
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+			/* ... then distribute the channels in pairs */
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+			for (k = 0; k < 2; k++) {
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+				if ((BIT(i + k) & ts->mask[j]) && ch) {
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+					val[j] |= BIT(i + k);
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+					ch -= 1;
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+				}
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+			}
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 		}
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-
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-		regmap_write(map, offset, val);
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-		offset += regmap_get_reg_stride(map);
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 	}
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 	/*
..
..
@@ -63,6 +68,11 @@
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 		return -EINVAL;
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 	}
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+	for (i = 0; i < AXG_TDM_NUM_LANES; i++) {
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+		regmap_write(map, offset, val[i]);
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+		offset += regmap_get_reg_stride(map);
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+	}
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+
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 	return 0;
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 }
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 EXPORT_SYMBOL_GPL(axg_tdm_formatter_set_channel_masks);