forked from ~ljy/RK356X_SDK_RELEASE

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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/sound/soc/atmel/mchp-spdifrx.c
....@@ -56,7 +56,7 @@
5656 /* Validity Bit Mode */
5757 #define SPDIFRX_MR_VBMODE_MASK		GENAMSK(1, 1)
5858 #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \
59
-	(0 << 1)	/* Load sample regardles of validity bit value */
59
+	(0 << 1)	/* Load sample regardless of validity bit value */
6060 #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \
6161 	(1 << 1)	/* Load sample only if validity bit is 0 */
6262 
....@@ -217,7 +217,6 @@
217217 struct mchp_spdifrx_user_data {
218218 	unsigned char data[SPDIFRX_UD_BITS / 8];
219219 	struct completion done;
220
-	spinlock_t lock;	/* protect access to user data */
221220 };
222221 
223222 struct mchp_spdifrx_mixer_control {
....@@ -231,13 +230,13 @@
231230 struct mchp_spdifrx_dev {
232231 	struct snd_dmaengine_dai_dma_data	capture;
233232 	struct mchp_spdifrx_mixer_control	control;
234
-	spinlock_t				blockend_lock;	/* protect access to blockend_refcount */
235
-	int					blockend_refcount;
233
+	struct mutex				mlock;
236234 	struct device				*dev;
237235 	struct regmap				*regmap;
238236 	struct clk				*pclk;
239237 	struct clk				*gclk;
240238 	unsigned int				fmt;
239
+	unsigned int				trigger_enabled;
241240 	unsigned int				gclk_enabled:1;
242241 };
243242 
....@@ -275,37 +274,11 @@
275274 	}
276275 }
277276 
278
-/* called from non-atomic context only */
279
-static void mchp_spdifrx_isr_blockend_en(struct mchp_spdifrx_dev *dev)
280
-{
281
-	unsigned long flags;
282
-
283
-	spin_lock_irqsave(&dev->blockend_lock, flags);
284
-	dev->blockend_refcount++;
285
-	/* don't enable BLOCKEND interrupt if it's already enabled */
286
-	if (dev->blockend_refcount == 1)
287
-		regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND);
288
-	spin_unlock_irqrestore(&dev->blockend_lock, flags);
289
-}
290
-
291
-/* called from atomic/non-atomic context */
292
-static void mchp_spdifrx_isr_blockend_dis(struct mchp_spdifrx_dev *dev)
293
-{
294
-	unsigned long flags;
295
-
296
-	spin_lock_irqsave(&dev->blockend_lock, flags);
297
-	dev->blockend_refcount--;
298
-	/* don't enable BLOCKEND interrupt if it's already enabled */
299
-	if (dev->blockend_refcount == 0)
300
-		regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND);
301
-	spin_unlock_irqrestore(&dev->blockend_lock, flags);
302
-}
303
-
304277 static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id)
305278 {
306279 	struct mchp_spdifrx_dev *dev = dev_id;
307280 	struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
308
-	u32 sr, imr, pending, idr = 0;
281
+	u32 sr, imr, pending;
309282 	irqreturn_t ret = IRQ_NONE;
310283 	int ch;
311284 
....@@ -320,13 +293,10 @@
320293 
321294 	if (pending & SPDIFRX_IR_BLOCKEND) {
322295 		for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
323
-			spin_lock(&ctrl->user_data[ch].lock);
324296 			mchp_spdifrx_channel_user_data_read(dev, ch);
325
-			spin_unlock(&ctrl->user_data[ch].lock);
326
-
327297 			complete(&ctrl->user_data[ch].done);
328298 		}
329
-		mchp_spdifrx_isr_blockend_dis(dev);
299
+		regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND);
330300 		ret = IRQ_HANDLED;
331301 	}
332302 
....@@ -334,7 +304,7 @@
334304 		if (pending & SPDIFRX_IR_CSC(ch)) {
335305 			mchp_spdifrx_channel_status_read(dev, ch);
336306 			complete(&ctrl->ch_stat[ch].done);
337
-			idr |= SPDIFRX_IR_CSC(ch);
307
+			regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(ch));
338308 			ret = IRQ_HANDLED;
339309 		}
340310 	}
....@@ -344,8 +314,6 @@
344314 		ret = IRQ_HANDLED;
345315 	}
346316 
347
-	regmap_write(dev->regmap, SPDIFRX_IDR, idr);
348
-
349317 	return ret;
350318 }
351319 
....@@ -353,47 +321,40 @@
353321 				struct snd_soc_dai *dai)
354322 {
355323 	struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
356
-	u32 mr;
357
-	int running;
358
-	int ret;
359
-
360
-	regmap_read(dev->regmap, SPDIFRX_MR, &mr);
361
-	running = !!(mr & SPDIFRX_MR_RXEN_ENABLE);
324
+	int ret = 0;
362325 
363326 	switch (cmd) {
364327 	case SNDRV_PCM_TRIGGER_START:
365328 	case SNDRV_PCM_TRIGGER_RESUME:
366329 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
367
-		if (!running) {
368
-			mr &= ~SPDIFRX_MR_RXEN_MASK;
369
-			mr |= SPDIFRX_MR_RXEN_ENABLE;
370
-			/* enable overrun interrupts */
371
-			regmap_write(dev->regmap, SPDIFRX_IER,
372
-				     SPDIFRX_IR_OVERRUN);
373
-		}
330
+		mutex_lock(&dev->mlock);
331
+		/* Enable overrun interrupts */
332
+		regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_OVERRUN);
333
+
334
+		/* Enable receiver. */
335
+		regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK,
336
+				   SPDIFRX_MR_RXEN_ENABLE);
337
+		dev->trigger_enabled = true;
338
+		mutex_unlock(&dev->mlock);
374339 		break;
375340 	case SNDRV_PCM_TRIGGER_STOP:
376341 	case SNDRV_PCM_TRIGGER_SUSPEND:
377342 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
378
-		if (running) {
379
-			mr &= ~SPDIFRX_MR_RXEN_MASK;
380
-			mr |= SPDIFRX_MR_RXEN_DISABLE;
381
-			/* disable overrun interrupts */
382
-			regmap_write(dev->regmap, SPDIFRX_IDR,
383
-				     SPDIFRX_IR_OVERRUN);
384
-		}
343
+		mutex_lock(&dev->mlock);
344
+		/* Disable overrun interrupts */
345
+		regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_OVERRUN);
346
+
347
+		/* Disable receiver. */
348
+		regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK,
349
+				   SPDIFRX_MR_RXEN_DISABLE);
350
+		dev->trigger_enabled = false;
351
+		mutex_unlock(&dev->mlock);
385352 		break;
386353 	default:
387
-		return -EINVAL;
354
+		ret = -EINVAL;
388355 	}
389356 
390
-	ret = regmap_write(dev->regmap, SPDIFRX_MR, mr);
391
-	if (ret) {
392
-		dev_err(dev->dev, "unable to enable/disable RX: %d\n", ret);
393
-		return ret;
394
-	}
395
-
396
-	return 0;
357
+	return ret;
397358 }
398359 
399360 static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream,
....@@ -401,7 +362,7 @@
401362 				  struct snd_soc_dai *dai)
402363 {
403364 	struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
404
-	u32 mr;
365
+	u32 mr = 0;
405366 	int ret;
406367 
407368 	dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
....@@ -411,13 +372,6 @@
411372 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
412373 		dev_err(dev->dev, "Playback is not supported\n");
413374 		return -EINVAL;
414
-	}
415
-
416
-	regmap_read(dev->regmap, SPDIFRX_MR, &mr);
417
-
418
-	if (mr & SPDIFRX_MR_RXEN_ENABLE) {
419
-		dev_err(dev->dev, "PCM already running\n");
420
-		return -EBUSY;
421375 	}
422376 
423377 	if (params_channels(params) != SPDIFRX_CHANNELS) {
....@@ -445,6 +399,13 @@
445399 		return -EINVAL;
446400 	}
447401 
402
+	mutex_lock(&dev->mlock);
403
+	if (dev->trigger_enabled) {
404
+		dev_err(dev->dev, "PCM already running\n");
405
+		ret = -EBUSY;
406
+		goto unlock;
407
+	}
408
+
448409 	if (dev->gclk_enabled) {
449410 		clk_disable_unprepare(dev->gclk);
450411 		dev->gclk_enabled = 0;
....@@ -455,19 +416,24 @@
455416 		dev_err(dev->dev,
456417 			"unable to set gclk min rate: rate %u * ratio %u + 1\n",
457418 			params_rate(params), SPDIFRX_GCLK_RATIO_MIN);
458
-		return ret;
419
+		goto unlock;
459420 	}
460421 	ret = clk_prepare_enable(dev->gclk);
461422 	if (ret) {
462423 		dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
463
-		return ret;
424
+		goto unlock;
464425 	}
465426 	dev->gclk_enabled = 1;
466427 
467428 	dev_dbg(dev->dev, "GCLK range min set to %d\n",
468429 		params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1);
469430 
470
-	return regmap_write(dev->regmap, SPDIFRX_MR, mr);
431
+	ret = regmap_write(dev->regmap, SPDIFRX_MR, mr);
432
+
433
+unlock:
434
+	mutex_unlock(&dev->mlock);
435
+
436
+	return ret;
471437 }
472438 
473439 static int mchp_spdifrx_hw_free(struct snd_pcm_substream *substream,
....@@ -475,10 +441,12 @@
475441 {
476442 	struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
477443 
444
+	mutex_lock(&dev->mlock);
478445 	if (dev->gclk_enabled) {
479446 		clk_disable_unprepare(dev->gclk);
480447 		dev->gclk_enabled = 0;
481448 	}
449
+	mutex_unlock(&dev->mlock);
482450 	return 0;
483451 }
484452 
....@@ -515,22 +483,51 @@
515483 {
516484 	struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
517485 	struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel];
518
-	int ret;
486
+	int ret = 0;
519487 
520
-	regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel));
521
-	/* check for new data available */
522
-	ret = wait_for_completion_interruptible_timeout(&ch_stat->done,
523
-							msecs_to_jiffies(100));
524
-	/* IP might not be started or valid stream might not be prezent */
525
-	if (ret < 0) {
526
-		dev_dbg(dev->dev, "channel status for channel %d timeout\n",
527
-			channel);
488
+	mutex_lock(&dev->mlock);
489
+
490
+	/*
491
+	 * We may reach this point with both clocks enabled but the receiver
492
+	 * still disabled. To void waiting for completion and return with
493
+	 * timeout check the dev->trigger_enabled.
494
+	 *
495
+	 * To retrieve data:
496
+	 * - if the receiver is enabled CSC IRQ will update the data in software
497
+	 *   caches (ch_stat->data)
498
+	 * - otherwise we just update it here the software caches with latest
499
+	 *   available information and return it; in this case we don't need
500
+	 *   spin locking as the IRQ is disabled and will not be raised from
501
+	 *   anywhere else.
502
+	 */
503
+
504
+	if (dev->trigger_enabled) {
505
+		reinit_completion(&ch_stat->done);
506
+		regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel));
507
+		/* Check for new data available */
508
+		ret = wait_for_completion_interruptible_timeout(&ch_stat->done,
509
+								msecs_to_jiffies(100));
510
+		/* Valid stream might not be present */
511
+		if (ret <= 0) {
512
+			dev_dbg(dev->dev, "channel status for channel %d timeout\n",
513
+				channel);
514
+			regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(channel));
515
+			ret = ret ? : -ETIMEDOUT;
516
+			goto unlock;
517
+		} else {
518
+			ret = 0;
519
+		}
520
+	} else {
521
+		/* Update software cache with latest channel status. */
522
+		mchp_spdifrx_channel_status_read(dev, channel);
528523 	}
529524 
530525 	memcpy(uvalue->value.iec958.status, ch_stat->data,
531526 	       sizeof(ch_stat->data));
532527 
533
-	return 0;
528
+unlock:
529
+	mutex_unlock(&dev->mlock);
530
+	return ret;
534531 }
535532 
536533 static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol,
....@@ -564,29 +561,49 @@
564561 				       int channel,
565562 				       struct snd_ctl_elem_value *uvalue)
566563 {
567
-	unsigned long flags;
568564 	struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
569565 	struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel];
570
-	int ret;
566
+	int ret = 0;
571567 
572
-	reinit_completion(&user_data->done);
573
-	mchp_spdifrx_isr_blockend_en(dev);
574
-	ret = wait_for_completion_interruptible_timeout(&user_data->done,
575
-							msecs_to_jiffies(100));
576
-	/* IP might not be started or valid stream might not be prezent */
577
-	if (ret <= 0) {
578
-		dev_dbg(dev->dev, "user data for channel %d timeout\n",
579
-			channel);
580
-		mchp_spdifrx_isr_blockend_dis(dev);
581
-		return ret;
568
+	mutex_lock(&dev->mlock);
569
+
570
+	/*
571
+	 * We may reach this point with both clocks enabled but the receiver
572
+	 * still disabled. To void waiting for completion to just timeout we
573
+	 * check here the dev->trigger_enabled flag.
574
+	 *
575
+	 * To retrieve data:
576
+	 * - if the receiver is enabled we need to wait for blockend IRQ to read
577
+	 *   data to and update it for us in software caches
578
+	 * - otherwise reading the SPDIFRX_CHUD() registers is enough.
579
+	 */
580
+
581
+	if (dev->trigger_enabled) {
582
+		reinit_completion(&user_data->done);
583
+		regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND);
584
+		ret = wait_for_completion_interruptible_timeout(&user_data->done,
585
+								msecs_to_jiffies(100));
586
+		/* Valid stream might not be present. */
587
+		if (ret <= 0) {
588
+			dev_dbg(dev->dev, "user data for channel %d timeout\n",
589
+				channel);
590
+			regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND);
591
+			ret = ret ? : -ETIMEDOUT;
592
+			goto unlock;
593
+		} else {
594
+			ret = 0;
595
+		}
596
+	} else {
597
+		/* Update software cache with last available data. */
598
+		mchp_spdifrx_channel_user_data_read(dev, channel);
582599 	}
583600 
584
-	spin_lock_irqsave(&user_data->lock, flags);
585601 	memcpy(uvalue->value.iec958.subcode, user_data->data,
586602 	       sizeof(user_data->data));
587
-	spin_unlock_irqrestore(&user_data->lock, flags);
588603 
589
-	return 0;
604
+unlock:
605
+	mutex_unlock(&dev->mlock);
606
+	return ret;
590607 }
591608 
592609 static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol,
....@@ -627,9 +644,23 @@
627644 	u32 val;
628645 	bool ulock_old = ctrl->ulock;
629646 
630
-	regmap_read(dev->regmap, SPDIFRX_RSR, &val);
631
-	ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK);
647
+	mutex_lock(&dev->mlock);
648
+
649
+	/*
650
+	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
651
+	 * and the receiver is disabled. Thus we take into account the
652
+	 * dev->trigger_enabled here to return a real status.
653
+	 */
654
+	if (dev->trigger_enabled) {
655
+		regmap_read(dev->regmap, SPDIFRX_RSR, &val);
656
+		ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK);
657
+	} else {
658
+		ctrl->ulock = 0;
659
+	}
660
+
632661 	uvalue->value.integer.value[0] = ctrl->ulock;
662
+
663
+	mutex_unlock(&dev->mlock);
633664 
634665 	return ulock_old != ctrl->ulock;
635666 }
....@@ -643,8 +674,22 @@
643674 	u32 val;
644675 	bool badf_old = ctrl->badf;
645676 
646
-	regmap_read(dev->regmap, SPDIFRX_RSR, &val);
647
-	ctrl->badf = !!(val & SPDIFRX_RSR_BADF);
677
+	mutex_lock(&dev->mlock);
678
+
679
+	/*
680
+	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
681
+	 * and the receiver is disabled. Thus we take into account the
682
+	 * dev->trigger_enabled here to return a real status.
683
+	 */
684
+	if (dev->trigger_enabled) {
685
+		regmap_read(dev->regmap, SPDIFRX_RSR, &val);
686
+		ctrl->badf = !!(val & SPDIFRX_RSR_BADF);
687
+	} else {
688
+		ctrl->badf = 0;
689
+	}
690
+
691
+	mutex_unlock(&dev->mlock);
692
+
648693 	uvalue->value.integer.value[0] = ctrl->badf;
649694 
650695 	return badf_old != ctrl->badf;
....@@ -656,11 +701,48 @@
656701 	struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
657702 	struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
658703 	struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
659
-	u32 val;
704
+	u32 val = ~0U, loops = 10;
705
+	int ret;
660706 	bool signal_old = ctrl->signal;
661707 
662
-	regmap_read(dev->regmap, SPDIFRX_RSR, &val);
663
-	ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL);
708
+	mutex_lock(&dev->mlock);
709
+
710
+	/*
711
+	 * To get the signal we need to have receiver enabled. This
712
+	 * could be enabled also from trigger() function thus we need to
713
+	 * take care of not disabling the receiver when it runs.
714
+	 */
715
+	if (!dev->trigger_enabled) {
716
+		ret = clk_prepare_enable(dev->gclk);
717
+		if (ret)
718
+			goto unlock;
719
+
720
+		regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK,
721
+				   SPDIFRX_MR_RXEN_ENABLE);
722
+
723
+		/* Wait for RSR.ULOCK bit. */
724
+		while (--loops) {
725
+			regmap_read(dev->regmap, SPDIFRX_RSR, &val);
726
+			if (!(val & SPDIFRX_RSR_ULOCK))
727
+				break;
728
+			usleep_range(100, 150);
729
+		}
730
+
731
+		regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK,
732
+				   SPDIFRX_MR_RXEN_DISABLE);
733
+
734
+		clk_disable_unprepare(dev->gclk);
735
+	} else {
736
+		regmap_read(dev->regmap, SPDIFRX_RSR, &val);
737
+	}
738
+
739
+unlock:
740
+	mutex_unlock(&dev->mlock);
741
+
742
+	if (!(val & SPDIFRX_RSR_ULOCK))
743
+		ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL);
744
+	else
745
+		ctrl->signal = 0;
664746 	uvalue->value.integer.value[0] = ctrl->signal;
665747 
666748 	return signal_old != ctrl->signal;
....@@ -685,18 +767,32 @@
685767 	u32 val;
686768 	int rate;
687769 
688
-	regmap_read(dev->regmap, SPDIFRX_RSR, &val);
770
+	mutex_lock(&dev->mlock);
689771 
690
-	/* if the receiver is not locked, ISF data is invalid */
691
-	if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) {
772
+	/*
773
+	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled
774
+	 * and the receiver is disabled. Thus we take into account the
775
+	 * dev->trigger_enabled here to return a real status.
776
+	 */
777
+	if (dev->trigger_enabled) {
778
+		regmap_read(dev->regmap, SPDIFRX_RSR, &val);
779
+		/* If the receiver is not locked, ISF data is invalid. */
780
+		if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) {
781
+			ucontrol->value.integer.value[0] = 0;
782
+			goto unlock;
783
+		}
784
+	} else {
785
+		/* Reveicer is not locked, IFS data is invalid. */
692786 		ucontrol->value.integer.value[0] = 0;
693
-		return 0;
787
+		goto unlock;
694788 	}
695789 
696790 	rate = clk_get_rate(dev->gclk);
697791 
698792 	ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val));
699793 
794
+unlock:
795
+	mutex_unlock(&dev->mlock);
700796 	return 0;
701797 }
702798 
....@@ -808,11 +904,9 @@
808904 		     SPDIFRX_MR_AUTORST_NOACTION |
809905 		     SPDIFRX_MR_PACK_DISABLED);
810906 
811
-	dev->blockend_refcount = 0;
812907 	for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
813908 		init_completion(&ctrl->ch_stat[ch].done);
814909 		init_completion(&ctrl->user_data[ch].done);
815
-		spin_lock_init(&ctrl->user_data[ch].lock);
816910 	}
817911 
818912 	/* Add controls */
....@@ -827,7 +921,7 @@
827921 	struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
828922 
829923 	/* Disable interrupts */
830
-	regmap_write(dev->regmap, SPDIFRX_IDR, 0xFF);
924
+	regmap_write(dev->regmap, SPDIFRX_IDR, GENMASK(14, 0));
831925 
832926 	clk_disable_unprepare(dev->pclk);
833927 
....@@ -912,7 +1006,17 @@
9121006 			"failed to get the PMC generated clock: %d\n", err);
9131007 		return err;
9141008 	}
915
-	spin_lock_init(&dev->blockend_lock);
1009
+
1010
+	/*
1011
+	 * Signal control need a valid rate on gclk. hw_params() configures
1012
+	 * it propertly but requesting signal before any hw_params() has been
1013
+	 * called lead to invalid value returned for signal. Thus, configure
1014
+	 * gclk at a valid rate, here, in initialization, to simplify the
1015
+	 * control path.
1016
+	 */
1017
+	clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1);
1018
+
1019
+	mutex_init(&dev->mlock);
9161020 
9171021 	dev->dev = &pdev->dev;
9181022 	dev->regmap = regmap;