~hc/RK356X_SDK_RELEASE.git

..	..	@@ -72,17 +72,42 @@
72	72
73	73	enum {
74	74	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
	75	+ MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
75	76	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
	77	+ MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
76	78	};
77	79
78	80	enum {
79		- MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80		- MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
	81	+ MLX5_SHARED_RESOURCE_UID = 0xffff,
81	82	};
82	83
83	84	enum {
84		- MLX5_OBJ_TYPE_UCTX = 0x0004,
85		- MLX5_OBJ_TYPE_UMEM = 0x0005,
	85	+ MLX5_OBJ_TYPE_SW_ICM = 0x0008,
	86	+};
	87	+
	88	+enum {
	89	+ MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
	90	+ MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
	91	+ MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
	92	+};
	93	+
	94	+enum {
	95	+ MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
	96	+ MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
	97	+ MLX5_OBJ_TYPE_MKEY = 0xff01,
	98	+ MLX5_OBJ_TYPE_QP = 0xff02,
	99	+ MLX5_OBJ_TYPE_PSV = 0xff03,
	100	+ MLX5_OBJ_TYPE_RMP = 0xff04,
	101	+ MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
	102	+ MLX5_OBJ_TYPE_RQ = 0xff06,
	103	+ MLX5_OBJ_TYPE_SQ = 0xff07,
	104	+ MLX5_OBJ_TYPE_TIR = 0xff08,
	105	+ MLX5_OBJ_TYPE_TIS = 0xff09,
	106	+ MLX5_OBJ_TYPE_DCT = 0xff0a,
	107	+ MLX5_OBJ_TYPE_XRQ = 0xff0b,
	108	+ MLX5_OBJ_TYPE_RQT = 0xff0e,
	109	+ MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
	110	+ MLX5_OBJ_TYPE_CQ = 0xff10,
86	111	};
87	112
88	113	enum {
..	..	@@ -98,6 +123,9 @@
98	123	MLX5_CMD_OP_QUERY_ISSI = 0x10a,
99	124	MLX5_CMD_OP_SET_ISSI = 0x10b,
100	125	MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
	126	+ MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
	127	+ MLX5_CMD_OP_ALLOC_SF = 0x113,
	128	+ MLX5_CMD_OP_DEALLOC_SF = 0x114,
101	129	MLX5_CMD_OP_CREATE_MKEY = 0x200,
102	130	MLX5_CMD_OP_QUERY_MKEY = 0x201,
103	131	MLX5_CMD_OP_DESTROY_MKEY = 0x202,
..	..	@@ -144,6 +172,12 @@
144	172	MLX5_CMD_OP_DESTROY_XRQ = 0x718,
145	173	MLX5_CMD_OP_QUERY_XRQ = 0x719,
146	174	MLX5_CMD_OP_ARM_XRQ = 0x71a,
	175	+ MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
	176	+ MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
	177	+ MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
	178	+ MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
	179	+ MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
	180	+ MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
147	181	MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
148	182	MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
149	183	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
..	..	@@ -161,6 +195,8 @@
161	195	MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
162	196	MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
163	197	MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
	198	+ MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
	199	+ MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
164	200	MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
165	201	MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
166	202	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
..	..	@@ -243,8 +279,9 @@
243	279	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
244	280	MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
245	281	MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
246		- MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
247		- MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
	282	+ MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
	283	+ MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
	284	+ MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
248	285	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
249	286	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
250	287	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
..	..	@@ -257,7 +294,18 @@
257	294	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
258	295	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
259	296	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
	297	+ MLX5_CMD_OP_CREATE_UCTX = 0xa04,
	298	+ MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
	299	+ MLX5_CMD_OP_CREATE_UMEM = 0xa08,
	300	+ MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
	301	+ MLX5_CMD_OP_SYNC_STEERING = 0xb00,
260	302	MLX5_CMD_OP_MAX
	303	+};
	304	+
	305	+/* Valid range for general commands that don't work over an object */
	306	+enum {
	307	+ MLX5_CMD_OP_GENERAL_START = 0xb00,
	308	+ MLX5_CMD_OP_GENERAL_END = 0xd00,
261	309	};
262	310
263	311	struct mlx5_ifc_flow_table_fields_supported_bits {
..	..	@@ -287,7 +335,11 @@
287	335	u8 outer_gre_protocol[0x1];
288	336	u8 outer_gre_key[0x1];
289	337	u8 outer_vxlan_vni[0x1];
290		- u8 reserved_at_1a[0x5];
	338	+ u8 outer_geneve_vni[0x1];
	339	+ u8 outer_geneve_oam[0x1];
	340	+ u8 outer_geneve_protocol_type[0x1];
	341	+ u8 outer_geneve_opt_len[0x1];
	342	+ u8 reserved_at_1e[0x1];
291	343	u8 source_eswitch_port[0x1];
292	344
293	345	u8 inner_dmac[0x1];
..	..	@@ -315,7 +367,8 @@
315	367	u8 inner_tcp_flags[0x1];
316	368	u8 reserved_at_37[0x9];
317	369
318		- u8 reserved_at_40[0x5];
	370	+ u8 geneve_tlv_option_0_data[0x1];
	371	+ u8 reserved_at_41[0x4];
319	372	u8 outer_first_mpls_over_udp[0x4];
320	373	u8 outer_first_mpls_over_gre[0x4];
321	374	u8 inner_first_mpls[0x4];
..	..	@@ -324,8 +377,17 @@
324	377	u8 outer_esp_spi[0x1];
325	378	u8 reserved_at_58[0x2];
326	379	u8 bth_dst_qp[0x1];
	380	+ u8 reserved_at_5b[0x5];
327	381
328		- u8 reserved_at_5b[0x25];
	382	+ u8 reserved_at_60[0x18];
	383	+ u8 metadata_reg_c_7[0x1];
	384	+ u8 metadata_reg_c_6[0x1];
	385	+ u8 metadata_reg_c_5[0x1];
	386	+ u8 metadata_reg_c_4[0x1];
	387	+ u8 metadata_reg_c_3[0x1];
	388	+ u8 metadata_reg_c_2[0x1];
	389	+ u8 metadata_reg_c_1[0x1];
	390	+ u8 metadata_reg_c_0[0x1];
329	391	};
330	392
331	393	struct mlx5_ifc_flow_table_prop_layout_bits {
..	..	@@ -336,7 +398,7 @@
336	398	u8 modify_root[0x1];
337	399	u8 identified_miss_table_mode[0x1];
338	400	u8 flow_table_modify[0x1];
339		- u8 encap[0x1];
	401	+ u8 reformat[0x1];
340	402	u8 decap[0x1];
341	403	u8 reserved_at_9[0x1];
342	404	u8 pop_vlan[0x1];
..	..	@@ -344,9 +406,25 @@
344	406	u8 reserved_at_c[0x1];
345	407	u8 pop_vlan_2[0x1];
346	408	u8 push_vlan_2[0x1];
347		- u8 reserved_at_f[0x11];
	409	+ u8 reformat_and_vlan_action[0x1];
	410	+ u8 reserved_at_10[0x1];
	411	+ u8 sw_owner[0x1];
	412	+ u8 reformat_l3_tunnel_to_l2[0x1];
	413	+ u8 reformat_l2_to_l3_tunnel[0x1];
	414	+ u8 reformat_and_modify_action[0x1];
	415	+ u8 ignore_flow_level[0x1];
	416	+ u8 reserved_at_16[0x1];
	417	+ u8 table_miss_action_domain[0x1];
	418	+ u8 termination_table[0x1];
	419	+ u8 reformat_and_fwd_to_table[0x1];
	420	+ u8 reserved_at_1a[0x2];
	421	+ u8 ipsec_encrypt[0x1];
	422	+ u8 ipsec_decrypt[0x1];
	423	+ u8 sw_owner_v2[0x1];
	424	+ u8 reserved_at_1f[0x1];
348	425
349		- u8 reserved_at_20[0x2];
	426	+ u8 termination_table_raw_traffic[0x1];
	427	+ u8 reserved_at_21[0x1];
350	428	u8 log_max_ft_size[0x6];
351	429	u8 log_max_modify_header_context[0x8];
352	430	u8 max_modify_header_actions[0x8];
..	..	@@ -417,8 +495,22 @@
417	495	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
418	496	};
419	497
	498	+struct mlx5_ifc_nvgre_key_bits {
	499	+ u8 hi[0x18];
	500	+ u8 lo[0x8];
	501	+};
	502	+
	503	+union mlx5_ifc_gre_key_bits {
	504	+ struct mlx5_ifc_nvgre_key_bits nvgre;
	505	+ u8 key[0x20];
	506	+};
	507	+
420	508	struct mlx5_ifc_fte_match_set_misc_bits {
421		- u8 reserved_at_0[0x8];
	509	+ u8 gre_c_present[0x1];
	510	+ u8 reserved_at_1[0x1];
	511	+ u8 gre_k_present[0x1];
	512	+ u8 gre_s_present[0x1];
	513	+ u8 source_vhca_port[0x4];
422	514	u8 source_sqn[0x18];
423	515
424	516	u8 source_eswitch_owner_vhca_id[0x10];
..	..	@@ -438,13 +530,14 @@
438	530	u8 reserved_at_64[0xc];
439	531	u8 gre_protocol[0x10];
440	532
441		- u8 gre_key_h[0x18];
442		- u8 gre_key_l[0x8];
	533	+ union mlx5_ifc_gre_key_bits gre_key;
443	534
444	535	u8 vxlan_vni[0x18];
445	536	u8 reserved_at_b8[0x8];
446	537
447		- u8 reserved_at_c0[0x20];
	538	+ u8 geneve_vni[0x18];
	539	+ u8 reserved_at_d8[0x7];
	540	+ u8 geneve_oam[0x1];
448	541
449	542	u8 reserved_at_e0[0xc];
450	543	u8 outer_ipv6_flow_label[0x14];
..	..	@@ -452,7 +545,11 @@
452	545	u8 reserved_at_100[0xc];
453	546	u8 inner_ipv6_flow_label[0x14];
454	547
455		- u8 reserved_at_120[0x28];
	548	+ u8 reserved_at_120[0xa];
	549	+ u8 geneve_opt_len[0x6];
	550	+ u8 geneve_protocol_type[0x10];
	551	+
	552	+ u8 reserved_at_140[0x8];
456	553	u8 bth_dst_qp[0x18];
457	554	u8 reserved_at_160[0x20];
458	555	u8 outer_esp_spi[0x20];
..	..	@@ -475,11 +572,55 @@
475	572
476	573	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
477	574
478		- u8 reserved_at_80[0x100];
	575	+ u8 metadata_reg_c_7[0x20];
	576	+
	577	+ u8 metadata_reg_c_6[0x20];
	578	+
	579	+ u8 metadata_reg_c_5[0x20];
	580	+
	581	+ u8 metadata_reg_c_4[0x20];
	582	+
	583	+ u8 metadata_reg_c_3[0x20];
	584	+
	585	+ u8 metadata_reg_c_2[0x20];
	586	+
	587	+ u8 metadata_reg_c_1[0x20];
	588	+
	589	+ u8 metadata_reg_c_0[0x20];
479	590
480	591	u8 metadata_reg_a[0x20];
481	592
482	593	u8 reserved_at_1a0[0x60];
	594	+};
	595	+
	596	+struct mlx5_ifc_fte_match_set_misc3_bits {
	597	+ u8 inner_tcp_seq_num[0x20];
	598	+
	599	+ u8 outer_tcp_seq_num[0x20];
	600	+
	601	+ u8 inner_tcp_ack_num[0x20];
	602	+
	603	+ u8 outer_tcp_ack_num[0x20];
	604	+
	605	+ u8 reserved_at_80[0x8];
	606	+ u8 outer_vxlan_gpe_vni[0x18];
	607	+
	608	+ u8 outer_vxlan_gpe_next_protocol[0x8];
	609	+ u8 outer_vxlan_gpe_flags[0x8];
	610	+ u8 reserved_at_b0[0x10];
	611	+
	612	+ u8 icmp_header_data[0x20];
	613	+
	614	+ u8 icmpv6_header_data[0x20];
	615	+
	616	+ u8 icmp_type[0x8];
	617	+ u8 icmp_code[0x8];
	618	+ u8 icmpv6_type[0x8];
	619	+ u8 icmpv6_code[0x8];
	620	+
	621	+ u8 geneve_tlv_option_0_data[0x20];
	622	+
	623	+ u8 reserved_at_140[0xc0];
483	624	};
484	625
485	626	struct mlx5_ifc_cmd_pas_bits {
..	..	@@ -554,27 +695,64 @@
554	695	u8 nic_rx_multi_path_tirs[0x1];
555	696	u8 nic_rx_multi_path_tirs_fts[0x1];
556	697	u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
557		- u8 reserved_at_3[0x1fd];
	698	+ u8 reserved_at_3[0x4];
	699	+ u8 sw_owner_reformat_supported[0x1];
	700	+ u8 reserved_at_8[0x18];
	701	+
	702	+ u8 encap_general_header[0x1];
	703	+ u8 reserved_at_21[0xa];
	704	+ u8 log_max_packet_reformat_context[0x5];
	705	+ u8 reserved_at_30[0x6];
	706	+ u8 max_encap_header_size[0xa];
	707	+ u8 reserved_at_40[0x1c0];
558	708
559	709	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
560	710
561		- u8 reserved_at_400[0x200];
	711	+ struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
562	712
563	713	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
564	714
565	715	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
566	716
567		- u8 reserved_at_a00[0x200];
	717	+ struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
568	718
569	719	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
570	720
571		- u8 reserved_at_e00[0x7200];
	721	+ u8 reserved_at_e00[0x1200];
	722	+
	723	+ u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
	724	+
	725	+ u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
	726	+
	727	+ u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
	728	+
	729	+ u8 reserved_at_20c0[0x5f40];
	730	+};
	731	+
	732	+enum {
	733	+ MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
	734	+ MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
	735	+ MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
	736	+ MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
	737	+ MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
	738	+ MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
	739	+ MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
	740	+ MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
572	741	};
573	742
574	743	struct mlx5_ifc_flow_table_eswitch_cap_bits {
575		- u8 reserved_at_0[0x1c];
	744	+ u8 fdb_to_vport_reg_c_id[0x8];
	745	+ u8 reserved_at_8[0xd];
	746	+ u8 fdb_modify_header_fwd_to_table[0x1];
	747	+ u8 reserved_at_16[0x1];
	748	+ u8 flow_source[0x1];
	749	+ u8 reserved_at_18[0x2];
	750	+ u8 multi_fdb_encap[0x1];
	751	+ u8 egress_acl_forward_to_vport[0x1];
576	752	u8 fdb_multi_path_to_table[0x1];
577		- u8 reserved_at_1d[0x1e3];
	753	+ u8 reserved_at_1d[0x3];
	754	+
	755	+ u8 reserved_at_20[0x1e0];
578	756
579	757	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
580	758
..	..	@@ -582,7 +760,22 @@
582	760
583	761	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
584	762
585		- u8 reserved_at_800[0x7800];
	763	+ u8 reserved_at_800[0x1000];
	764	+
	765	+ u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
	766	+
	767	+ u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
	768	+
	769	+ u8 sw_steering_uplink_icm_address_rx[0x40];
	770	+
	771	+ u8 sw_steering_uplink_icm_address_tx[0x40];
	772	+
	773	+ u8 reserved_at_1900[0x6700];
	774	+};
	775	+
	776	+enum {
	777	+ MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
	778	+ MLX5_COUNTER_FLOW_ESWITCH = 0x1,
586	779	};
587	780
588	781	struct mlx5_ifc_e_switch_cap_bits {
..	..	@@ -591,19 +784,31 @@
591	784	u8 vport_svlan_insert[0x1];
592	785	u8 vport_cvlan_insert_if_not_exist[0x1];
593	786	u8 vport_cvlan_insert_overwrite[0x1];
594		- u8 reserved_at_5[0x18];
	787	+ u8 reserved_at_5[0x3];
	788	+ u8 esw_uplink_ingress_acl[0x1];
	789	+ u8 reserved_at_9[0x10];
	790	+ u8 esw_functions_changed[0x1];
	791	+ u8 reserved_at_1a[0x1];
	792	+ u8 ecpf_vport_exists[0x1];
	793	+ u8 counter_eswitch_affinity[0x1];
595	794	u8 merged_eswitch[0x1];
596	795	u8 nic_vport_node_guid_modify[0x1];
597	796	u8 nic_vport_port_guid_modify[0x1];
598	797
599	798	u8 vxlan_encap_decap[0x1];
600	799	u8 nvgre_encap_decap[0x1];
601		- u8 reserved_at_22[0x9];
602		- u8 log_max_encap_headers[0x5];
	800	+ u8 reserved_at_22[0x1];
	801	+ u8 log_max_fdb_encap_uplink[0x5];
	802	+ u8 reserved_at_21[0x3];
	803	+ u8 log_max_packet_reformat_context[0x5];
603	804	u8 reserved_2b[0x6];
604	805	u8 max_encap_header_size[0xa];
605	806
606		- u8 reserved_40[0x7c0];
	807	+ u8 reserved_at_40[0xb];
	808	+ u8 log_max_esw_sf[0x5];
	809	+ u8 esw_sf_base_id[0x10];
	810	+
	811	+ u8 reserved_at_60[0x7a0];
607	812
608	813	};
609	814
..	..	@@ -615,7 +820,9 @@
615	820	u8 reserved_at_4[0x1];
616	821	u8 packet_pacing_burst_bound[0x1];
617	822	u8 packet_pacing_typical_size[0x1];
618		- u8 reserved_at_7[0x19];
	823	+ u8 reserved_at_7[0x4];
	824	+ u8 packet_pacing_uid[0x1];
	825	+ u8 reserved_at_c[0x14];
619	826
620	827	u8 reserved_at_20[0x20];
621	828
..	..	@@ -638,7 +845,11 @@
638	845	};
639	846
640	847	struct mlx5_ifc_debug_cap_bits {
641		- u8 reserved_at_0[0x20];
	848	+ u8 core_dump_general[0x1];
	849	+ u8 core_dump_qp[0x1];
	850	+ u8 reserved_at_2[0x7];
	851	+ u8 resource_dump[0x1];
	852	+ u8 reserved_at_a[0x16];
642	853
643	854	u8 reserved_at_20[0x2];
644	855	u8 stall_detect[0x1];
..	..	@@ -665,7 +876,8 @@
665	876	u8 scatter_fcs[0x1];
666	877	u8 enhanced_multi_pkt_send_wqe[0x1];
667	878	u8 tunnel_lso_const_out_ip_id[0x1];
668		- u8 reserved_at_1c[0x2];
	879	+ u8 tunnel_lro_gre[0x1];
	880	+ u8 tunnel_lro_vxlan[0x1];
669	881	u8 tunnel_stateless_gre[0x1];
670	882	u8 tunnel_stateless_vxlan[0x1];
671	883
..	..	@@ -679,7 +891,8 @@
679	891	u8 tunnel_stateless_vxlan_gpe[0x1];
680	892	u8 tunnel_stateless_ipv4_over_vxlan[0x1];
681	893	u8 tunnel_stateless_ip_over_ip[0x1];
682		- u8 reserved_at_2a[0x6];
	894	+ u8 insert_trailer[0x1];
	895	+ u8 reserved_at_2b[0x5];
683	896	u8 max_vxlan_udp_ports[0x8];
684	897	u8 reserved_at_38[0x6];
685	898	u8 max_geneve_opt_len[0x1];
..	..	@@ -697,7 +910,9 @@
697	910
698	911	struct mlx5_ifc_roce_cap_bits {
699	912	u8 roce_apm[0x1];
700		- u8 reserved_at_1[0x1f];
	913	+ u8 reserved_at_1[0x3];
	914	+ u8 sw_r_roce_src_udp_port[0x1];
	915	+ u8 reserved_at_5[0x1b];
701	916
702	917	u8 reserved_at_20[0x60];
703	918
..	..	@@ -718,6 +933,25 @@
718	933	u8 reserved_at_100[0x700];
719	934	};
720	935
	936	+struct mlx5_ifc_sync_steering_in_bits {
	937	+ u8 opcode[0x10];
	938	+ u8 uid[0x10];
	939	+
	940	+ u8 reserved_at_20[0x10];
	941	+ u8 op_mod[0x10];
	942	+
	943	+ u8 reserved_at_40[0xc0];
	944	+};
	945	+
	946	+struct mlx5_ifc_sync_steering_out_bits {
	947	+ u8 status[0x8];
	948	+ u8 reserved_at_8[0x18];
	949	+
	950	+ u8 syndrome[0x20];
	951	+
	952	+ u8 reserved_at_40[0x40];
	953	+};
	954	+
721	955	struct mlx5_ifc_device_mem_cap_bits {
722	956	u8 memic[0x1];
723	957	u8 reserved_at_1[0x1f];
..	..	@@ -733,7 +967,61 @@
733	967
734	968	u8 max_memic_size[0x20];
735	969
736		- u8 reserved_at_c0[0x740];
	970	+ u8 steering_sw_icm_start_address[0x40];
	971	+
	972	+ u8 reserved_at_100[0x8];
	973	+ u8 log_header_modify_sw_icm_size[0x8];
	974	+ u8 reserved_at_110[0x2];
	975	+ u8 log_sw_icm_alloc_granularity[0x6];
	976	+ u8 log_steering_sw_icm_size[0x8];
	977	+
	978	+ u8 reserved_at_120[0x20];
	979	+
	980	+ u8 header_modify_sw_icm_start_address[0x40];
	981	+
	982	+ u8 reserved_at_180[0x680];
	983	+};
	984	+
	985	+struct mlx5_ifc_device_event_cap_bits {
	986	+ u8 user_affiliated_events[4][0x40];
	987	+
	988	+ u8 user_unaffiliated_events[4][0x40];
	989	+};
	990	+
	991	+struct mlx5_ifc_virtio_emulation_cap_bits {
	992	+ u8 desc_tunnel_offload_type[0x1];
	993	+ u8 eth_frame_offload_type[0x1];
	994	+ u8 virtio_version_1_0[0x1];
	995	+ u8 device_features_bits_mask[0xd];
	996	+ u8 event_mode[0x8];
	997	+ u8 virtio_queue_type[0x8];
	998	+
	999	+ u8 max_tunnel_desc[0x10];
	1000	+ u8 reserved_at_30[0x3];
	1001	+ u8 log_doorbell_stride[0x5];
	1002	+ u8 reserved_at_38[0x3];
	1003	+ u8 log_doorbell_bar_size[0x5];
	1004	+
	1005	+ u8 doorbell_bar_offset[0x40];
	1006	+
	1007	+ u8 max_emulated_devices[0x8];
	1008	+ u8 max_num_virtio_queues[0x18];
	1009	+
	1010	+ u8 reserved_at_a0[0x60];
	1011	+
	1012	+ u8 umem_1_buffer_param_a[0x20];
	1013	+
	1014	+ u8 umem_1_buffer_param_b[0x20];
	1015	+
	1016	+ u8 umem_2_buffer_param_a[0x20];
	1017	+
	1018	+ u8 umem_2_buffer_param_b[0x20];
	1019	+
	1020	+ u8 umem_3_buffer_param_a[0x20];
	1021	+
	1022	+ u8 umem_3_buffer_param_b[0x20];
	1023	+
	1024	+ u8 reserved_at_1c0[0x640];
737	1025	};
738	1026
739	1027	enum {
..	..	@@ -797,7 +1085,11 @@
797	1085
798	1086	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
799	1087
800		- u8 reserved_at_e0[0x720];
	1088	+ struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
	1089	+
	1090	+ struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
	1091	+
	1092	+ u8 reserved_at_120[0x6E0];
801	1093	};
802	1094
803	1095	struct mlx5_ifc_calc_op {
..	..	@@ -824,7 +1116,34 @@
824	1116	struct mlx5_ifc_calc_op calc2;
825	1117	struct mlx5_ifc_calc_op calc3;
826	1118
827		- u8 reserved_at_e0[0x720];
	1119	+ u8 reserved_at_c0[0x720];
	1120	+};
	1121	+
	1122	+struct mlx5_ifc_tls_cap_bits {
	1123	+ u8 tls_1_2_aes_gcm_128[0x1];
	1124	+ u8 tls_1_3_aes_gcm_128[0x1];
	1125	+ u8 tls_1_2_aes_gcm_256[0x1];
	1126	+ u8 tls_1_3_aes_gcm_256[0x1];
	1127	+ u8 reserved_at_4[0x1c];
	1128	+
	1129	+ u8 reserved_at_20[0x7e0];
	1130	+};
	1131	+
	1132	+struct mlx5_ifc_ipsec_cap_bits {
	1133	+ u8 ipsec_full_offload[0x1];
	1134	+ u8 ipsec_crypto_offload[0x1];
	1135	+ u8 ipsec_esn[0x1];
	1136	+ u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
	1137	+ u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
	1138	+ u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
	1139	+ u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
	1140	+ u8 reserved_at_7[0x4];
	1141	+ u8 log_max_ipsec_offload[0x5];
	1142	+ u8 reserved_at_10[0x10];
	1143	+
	1144	+ u8 min_log_ipsec_full_replay_window[0x8];
	1145	+ u8 max_log_ipsec_full_replay_window[0x8];
	1146	+ u8 reserved_at_30[0x7d0];
828	1147	};
829	1148
830	1149	enum {
..	..	@@ -878,6 +1197,40 @@
878	1197	MLX5_CAP_UMR_FENCE_NONE = 0x2,
879	1198	};
880	1199
	1200	+enum {
	1201	+ MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
	1202	+ MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
	1203	+ MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
	1204	+ MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
	1205	+};
	1206	+
	1207	+enum {
	1208	+ MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
	1209	+ MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
	1210	+};
	1211	+
	1212	+#define MLX5_FC_BULK_SIZE_FACTOR 128
	1213	+
	1214	+enum mlx5_fc_bulk_alloc_bitmask {
	1215	+ MLX5_FC_BULK_128 = (1 << 0),
	1216	+ MLX5_FC_BULK_256 = (1 << 1),
	1217	+ MLX5_FC_BULK_512 = (1 << 2),
	1218	+ MLX5_FC_BULK_1024 = (1 << 3),
	1219	+ MLX5_FC_BULK_2048 = (1 << 4),
	1220	+ MLX5_FC_BULK_4096 = (1 << 5),
	1221	+ MLX5_FC_BULK_8192 = (1 << 6),
	1222	+ MLX5_FC_BULK_16384 = (1 << 7),
	1223	+};
	1224	+
	1225	+#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
	1226	+
	1227	+#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
	1228	+
	1229	+enum {
	1230	+ MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
	1231	+ MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
	1232	+};
	1233	+
881	1234	struct mlx5_ifc_cmd_hca_cap_bits {
882	1235	u8 reserved_at_0[0x30];
883	1236	u8 vhca_id[0x10];
..	..	@@ -886,24 +1239,35 @@
886	1239
887	1240	u8 log_max_srq_sz[0x8];
888	1241	u8 log_max_qp_sz[0x8];
889		- u8 reserved_at_90[0xb];
	1242	+ u8 event_cap[0x1];
	1243	+ u8 reserved_at_91[0x7];
	1244	+ u8 prio_tag_required[0x1];
	1245	+ u8 reserved_at_99[0x2];
890	1246	u8 log_max_qp[0x5];
891	1247
892		- u8 reserved_at_a0[0xb];
	1248	+ u8 reserved_at_a0[0x3];
	1249	+ u8 ece_support[0x1];
	1250	+ u8 reserved_at_a4[0x7];
893	1251	u8 log_max_srq[0x5];
894	1252	u8 reserved_at_b0[0x10];
895	1253
896		- u8 reserved_at_c0[0x8];
	1254	+ u8 max_sgl_for_optimized_performance[0x8];
897	1255	u8 log_max_cq_sz[0x8];
898		- u8 reserved_at_d0[0xb];
	1256	+ u8 relaxed_ordering_write_umr[0x1];
	1257	+ u8 relaxed_ordering_read_umr[0x1];
	1258	+ u8 reserved_at_d2[0x7];
	1259	+ u8 virtio_net_device_emualtion_manager[0x1];
	1260	+ u8 virtio_blk_device_emualtion_manager[0x1];
899	1261	u8 log_max_cq[0x5];
900	1262
901	1263	u8 log_max_eq_sz[0x8];
902		- u8 reserved_at_e8[0x2];
	1264	+ u8 relaxed_ordering_write[0x1];
	1265	+ u8 relaxed_ordering_read[0x1];
903	1266	u8 log_max_mkey[0x6];
904	1267	u8 reserved_at_f0[0x8];
905	1268	u8 dump_fill_mkey[0x1];
906		- u8 reserved_at_f9[0x3];
	1269	+ u8 reserved_at_f9[0x2];
	1270	+ u8 fast_teardown[0x1];
907	1271	u8 log_max_eq[0x4];
908	1272
909	1273	u8 max_indirection[0x8];
..	..	@@ -921,7 +1285,10 @@
921	1285	u8 reserved_at_130[0xa];
922	1286	u8 log_max_ra_res_dc[0x6];
923	1287
924		- u8 reserved_at_140[0xa];
	1288	+ u8 reserved_at_140[0x6];
	1289	+ u8 release_all_pages[0x1];
	1290	+ u8 reserved_at_147[0x2];
	1291	+ u8 roce_accl[0x1];
925	1292	u8 log_max_ra_req_qp[0x6];
926	1293	u8 reserved_at_150[0xa];
927	1294	u8 log_max_ra_res_qp[0x6];
..	..	@@ -931,7 +1298,12 @@
931	1298	u8 cc_modify_allowed[0x1];
932	1299	u8 start_pad[0x1];
933	1300	u8 cache_line_128byte[0x1];
934		- u8 reserved_at_165[0xa];
	1301	+ u8 reserved_at_165[0x4];
	1302	+ u8 rts2rts_qp_counters_set_id[0x1];
	1303	+ u8 reserved_at_16a[0x2];
	1304	+ u8 vnic_env_int_rq_oob[0x1];
	1305	+ u8 sbcam_reg[0x1];
	1306	+ u8 reserved_at_16e[0x1];
935	1307	u8 qcam_reg[0x1];
936	1308	u8 gid_table_size[0x10];
937	1309
..	..	@@ -988,7 +1360,11 @@
988	1360	u8 wol_p[0x1];
989	1361
990	1362	u8 stat_rate_support[0x10];
991		- u8 reserved_at_1f0[0xc];
	1363	+ u8 reserved_at_1f0[0x1];
	1364	+ u8 pci_sync_for_fw_update_event[0x1];
	1365	+ u8 reserved_at_1f2[0x6];
	1366	+ u8 init2_lag_tx_port_affinity[0x1];
	1367	+ u8 reserved_at_1fa[0x3];
992	1368	u8 cqe_version[0x4];
993	1369
994	1370	u8 compact_address_vector[0x1];
..	..	@@ -1002,7 +1378,8 @@
1002	1378	u8 umr_modify_atomic_disabled[0x1];
1003	1379	u8 umr_indirect_mkey_disabled[0x1];
1004	1380	u8 umr_fence[0x2];
1005		- u8 reserved_at_20c[0x3];
	1381	+ u8 dc_req_scat_data_cqe[0x1];
	1382	+ u8 reserved_at_20d[0x2];
1006	1383	u8 drain_sigerr[0x1];
1007	1384	u8 cmdif_checksum[0x2];
1008	1385	u8 sigerr_cqe[0x1];
..	..	@@ -1036,7 +1413,8 @@
1036	1413	u8 vector_calc[0x1];
1037	1414	u8 umr_ptr_rlky[0x1];
1038	1415	u8 imaicl[0x1];
1039		- u8 reserved_at_232[0x4];
	1416	+ u8 qp_packet_based[0x1];
	1417	+ u8 reserved_at_233[0x3];
1040	1418	u8 qkv[0x1];
1041	1419	u8 pkv[0x1];
1042	1420	u8 set_deth_sqpn[0x1];
..	..	@@ -1055,10 +1433,16 @@
1055	1433	u8 bf[0x1];
1056	1434	u8 driver_version[0x1];
1057	1435	u8 pad_tx_eth_packet[0x1];
1058		- u8 reserved_at_263[0x8];
	1436	+ u8 reserved_at_263[0x3];
	1437	+ u8 mkey_by_name[0x1];
	1438	+ u8 reserved_at_267[0x4];
	1439	+
1059	1440	u8 log_bf_reg_size[0x5];
1060	1441
1061		- u8 reserved_at_270[0xb];
	1442	+ u8 reserved_at_270[0x6];
	1443	+ u8 lag_dct[0x2];
	1444	+ u8 lag_tx_port_affinity[0x1];
	1445	+ u8 reserved_at_279[0x2];
1062	1446	u8 lag_master[0x1];
1063	1447	u8 num_lag_ports[0x4];
1064	1448
..	..	@@ -1074,7 +1458,8 @@
1074	1458	u8 reserved_at_2e0[0x7];
1075	1459	u8 max_qp_mcg[0x19];
1076	1460
1077		- u8 reserved_at_300[0x18];
	1461	+ u8 reserved_at_300[0x10];
	1462	+ u8 flow_counter_bulk_alloc[0x8];
1078	1463	u8 log_max_mcg[0x8];
1079	1464
1080	1465	u8 reserved_at_320[0x3];
..	..	@@ -1144,12 +1529,20 @@
1144	1529
1145	1530	u8 general_obj_types[0x40];
1146	1531
1147		- u8 reserved_at_440[0x20];
	1532	+ u8 reserved_at_440[0x4];
	1533	+ u8 steering_format_version[0x4];
	1534	+ u8 create_qp_start_hint[0x18];
1148	1535
1149		- u8 reserved_at_460[0x10];
	1536	+ u8 reserved_at_460[0x3];
	1537	+ u8 log_max_uctx[0x5];
	1538	+ u8 reserved_at_468[0x2];
	1539	+ u8 ipsec_offload[0x1];
	1540	+ u8 log_max_umem[0x5];
1150	1541	u8 max_num_eqs[0x10];
1151	1542
1152		- u8 reserved_at_480[0x3];
	1543	+ u8 reserved_at_480[0x1];
	1544	+ u8 tls_tx[0x1];
	1545	+ u8 tls_rx[0x1];
1153	1546	u8 log_max_l2_table[0x5];
1154	1547	u8 reserved_at_488[0x8];
1155	1548	u8 log_uar_page_sz[0x10];
..	..	@@ -1162,9 +1555,15 @@
1162	1555	u8 num_of_uars_per_page[0x20];
1163	1556
1164	1557	u8 flex_parser_protocols[0x20];
1165		- u8 reserved_at_560[0x20];
1166	1558
1167		- u8 reserved_at_580[0x3c];
	1559	+ u8 max_geneve_tlv_options[0x8];
	1560	+ u8 reserved_at_568[0x3];
	1561	+ u8 max_geneve_tlv_option_data_len[0x5];
	1562	+ u8 reserved_at_570[0x10];
	1563	+
	1564	+ u8 reserved_at_580[0x33];
	1565	+ u8 log_max_dek[0x5];
	1566	+ u8 reserved_at_5b8[0x4];
1168	1567	u8 mini_cqe_resp_stride_index[0x1];
1169	1568	u8 cqe_128_always[0x1];
1170	1569	u8 cqe_compression_128[0x1];
..	..	@@ -1186,7 +1585,41 @@
1186	1585	u8 num_vhca_ports[0x8];
1187	1586	u8 reserved_at_618[0x6];
1188	1587	u8 sw_owner_id[0x1];
1189		- u8 reserved_at_61f[0x1e1];
	1588	+ u8 reserved_at_61f[0x1];
	1589	+
	1590	+ u8 max_num_of_monitor_counters[0x10];
	1591	+ u8 num_ppcnt_monitor_counters[0x10];
	1592	+
	1593	+ u8 reserved_at_640[0x10];
	1594	+ u8 num_q_monitor_counters[0x10];
	1595	+
	1596	+ u8 reserved_at_660[0x20];
	1597	+
	1598	+ u8 sf[0x1];
	1599	+ u8 sf_set_partition[0x1];
	1600	+ u8 reserved_at_682[0x1];
	1601	+ u8 log_max_sf[0x5];
	1602	+ u8 reserved_at_688[0x8];
	1603	+ u8 log_min_sf_size[0x8];
	1604	+ u8 max_num_sf_partitions[0x8];
	1605	+
	1606	+ u8 uctx_cap[0x20];
	1607	+
	1608	+ u8 reserved_at_6c0[0x4];
	1609	+ u8 flex_parser_id_geneve_tlv_option_0[0x4];
	1610	+ u8 flex_parser_id_icmp_dw1[0x4];
	1611	+ u8 flex_parser_id_icmp_dw0[0x4];
	1612	+ u8 flex_parser_id_icmpv6_dw1[0x4];
	1613	+ u8 flex_parser_id_icmpv6_dw0[0x4];
	1614	+ u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
	1615	+ u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
	1616	+
	1617	+ u8 reserved_at_6e0[0x10];
	1618	+ u8 sf_base_id[0x10];
	1619	+
	1620	+ u8 reserved_at_700[0x80];
	1621	+ u8 vhca_tunnel_commands[0x40];
	1622	+ u8 reserved_at_7c0[0x40];
1190	1623	};
1191	1624
1192	1625	enum mlx5_flow_destination_type {
..	..	@@ -1199,11 +1632,19 @@
1199	1632	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1200	1633	};
1201	1634
	1635	+enum mlx5_flow_table_miss_action {
	1636	+ MLX5_FLOW_TABLE_MISS_ACTION_DEF,
	1637	+ MLX5_FLOW_TABLE_MISS_ACTION_FWD,
	1638	+ MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
	1639	+};
	1640	+
1202	1641	struct mlx5_ifc_dest_format_struct_bits {
1203	1642	u8 destination_type[0x8];
1204	1643	u8 destination_id[0x18];
	1644	+
1205	1645	u8 destination_eswitch_owner_vhca_id_valid[0x1];
1206		- u8 reserved_at_21[0xf];
	1646	+ u8 packet_reformat[0x1];
	1647	+ u8 reserved_at_22[0xe];
1207	1648	u8 destination_eswitch_owner_vhca_id[0x10];
1208	1649	};
1209	1650
..	..	@@ -1213,10 +1654,17 @@
1213	1654	u8 reserved_at_20[0x20];
1214	1655	};
1215	1656
	1657	+struct mlx5_ifc_extended_dest_format_bits {
	1658	+ struct mlx5_ifc_dest_format_struct_bits destination_entry;
	1659	+
	1660	+ u8 packet_reformat_id[0x20];
	1661	+
	1662	+ u8 reserved_at_60[0x20];
	1663	+};
	1664	+
1216	1665	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1217		- struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
	1666	+ struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1218	1667	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1219		- u8 reserved_at_0[0x40];
1220	1668	};
1221	1669
1222	1670	struct mlx5_ifc_fte_match_param_bits {
..	..	@@ -1228,7 +1676,9 @@
1228	1676
1229	1677	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1230	1678
1231		- u8 reserved_at_800[0x800];
	1679	+ struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
	1680	+
	1681	+ u8 reserved_at_a00[0x600];
1232	1682	};
1233	1683
1234	1684	enum {
..	..	@@ -1287,7 +1737,9 @@
1287	1737	u8 reserved_at_118[0x3];
1288	1738	u8 log_wq_sz[0x5];
1289	1739
1290		- u8 reserved_at_120[0x3];
	1740	+ u8 dbr_umem_valid[0x1];
	1741	+ u8 wq_umem_valid[0x1];
	1742	+ u8 reserved_at_122[0x1];
1291	1743	u8 log_hairpin_num_packets[0x5];
1292	1744	u8 reserved_at_128[0x3];
1293	1745	u8 log_hairpin_data_sz[0x5];
..	..	@@ -1300,7 +1752,7 @@
1300	1752
1301	1753	u8 reserved_at_140[0x4c0];
1302	1754
1303		- struct mlx5_ifc_cmd_pas_bits pas[0];
	1755	+ struct mlx5_ifc_cmd_pas_bits pas[];
1304	1756	};
1305	1757
1306	1758	struct mlx5_ifc_rq_num_bits {
..	..	@@ -1416,6 +1868,132 @@
1416	1868
1417	1869	struct mlx5_ifc_resize_field_select_bits {
1418	1870	u8 resize_field_select[0x20];
	1871	+};
	1872	+
	1873	+struct mlx5_ifc_resource_dump_bits {
	1874	+ u8 more_dump[0x1];
	1875	+ u8 inline_dump[0x1];
	1876	+ u8 reserved_at_2[0xa];
	1877	+ u8 seq_num[0x4];
	1878	+ u8 segment_type[0x10];
	1879	+
	1880	+ u8 reserved_at_20[0x10];
	1881	+ u8 vhca_id[0x10];
	1882	+
	1883	+ u8 index1[0x20];
	1884	+
	1885	+ u8 index2[0x20];
	1886	+
	1887	+ u8 num_of_obj1[0x10];
	1888	+ u8 num_of_obj2[0x10];
	1889	+
	1890	+ u8 reserved_at_a0[0x20];
	1891	+
	1892	+ u8 device_opaque[0x40];
	1893	+
	1894	+ u8 mkey[0x20];
	1895	+
	1896	+ u8 size[0x20];
	1897	+
	1898	+ u8 address[0x40];
	1899	+
	1900	+ u8 inline_data[52][0x20];
	1901	+};
	1902	+
	1903	+struct mlx5_ifc_resource_dump_menu_record_bits {
	1904	+ u8 reserved_at_0[0x4];
	1905	+ u8 num_of_obj2_supports_active[0x1];
	1906	+ u8 num_of_obj2_supports_all[0x1];
	1907	+ u8 must_have_num_of_obj2[0x1];
	1908	+ u8 support_num_of_obj2[0x1];
	1909	+ u8 num_of_obj1_supports_active[0x1];
	1910	+ u8 num_of_obj1_supports_all[0x1];
	1911	+ u8 must_have_num_of_obj1[0x1];
	1912	+ u8 support_num_of_obj1[0x1];
	1913	+ u8 must_have_index2[0x1];
	1914	+ u8 support_index2[0x1];
	1915	+ u8 must_have_index1[0x1];
	1916	+ u8 support_index1[0x1];
	1917	+ u8 segment_type[0x10];
	1918	+
	1919	+ u8 segment_name[4][0x20];
	1920	+
	1921	+ u8 index1_name[4][0x20];
	1922	+
	1923	+ u8 index2_name[4][0x20];
	1924	+};
	1925	+
	1926	+struct mlx5_ifc_resource_dump_segment_header_bits {
	1927	+ u8 length_dw[0x10];
	1928	+ u8 segment_type[0x10];
	1929	+};
	1930	+
	1931	+struct mlx5_ifc_resource_dump_command_segment_bits {
	1932	+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
	1933	+
	1934	+ u8 segment_called[0x10];
	1935	+ u8 vhca_id[0x10];
	1936	+
	1937	+ u8 index1[0x20];
	1938	+
	1939	+ u8 index2[0x20];
	1940	+
	1941	+ u8 num_of_obj1[0x10];
	1942	+ u8 num_of_obj2[0x10];
	1943	+};
	1944	+
	1945	+struct mlx5_ifc_resource_dump_error_segment_bits {
	1946	+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
	1947	+
	1948	+ u8 reserved_at_20[0x10];
	1949	+ u8 syndrome_id[0x10];
	1950	+
	1951	+ u8 reserved_at_40[0x40];
	1952	+
	1953	+ u8 error[8][0x20];
	1954	+};
	1955	+
	1956	+struct mlx5_ifc_resource_dump_info_segment_bits {
	1957	+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
	1958	+
	1959	+ u8 reserved_at_20[0x18];
	1960	+ u8 dump_version[0x8];
	1961	+
	1962	+ u8 hw_version[0x20];
	1963	+
	1964	+ u8 fw_version[0x20];
	1965	+};
	1966	+
	1967	+struct mlx5_ifc_resource_dump_menu_segment_bits {
	1968	+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
	1969	+
	1970	+ u8 reserved_at_20[0x10];
	1971	+ u8 num_of_records[0x10];
	1972	+
	1973	+ struct mlx5_ifc_resource_dump_menu_record_bits record[];
	1974	+};
	1975	+
	1976	+struct mlx5_ifc_resource_dump_resource_segment_bits {
	1977	+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
	1978	+
	1979	+ u8 reserved_at_20[0x20];
	1980	+
	1981	+ u8 index1[0x20];
	1982	+
	1983	+ u8 index2[0x20];
	1984	+
	1985	+ u8 payload[][0x20];
	1986	+};
	1987	+
	1988	+struct mlx5_ifc_resource_dump_terminate_segment_bits {
	1989	+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
	1990	+};
	1991	+
	1992	+struct mlx5_ifc_menu_resource_dump_response_bits {
	1993	+ struct mlx5_ifc_resource_dump_info_segment_bits info;
	1994	+ struct mlx5_ifc_resource_dump_command_segment_bits cmd;
	1995	+ struct mlx5_ifc_resource_dump_menu_segment_bits menu;
	1996	+ struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1419	1997	};
1420	1998
1421	1999	enum {
..	..	@@ -1626,12 +2204,28 @@
1626	2204	u8 port_xmit_wait[0x20];
1627	2205	};
1628	2206
1629		-struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
	2207	+struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
1630	2208	u8 transmit_queue_high[0x20];
1631	2209
1632	2210	u8 transmit_queue_low[0x20];
1633	2211
1634		- u8 reserved_at_40[0x780];
	2212	+ u8 no_buffer_discard_uc_high[0x20];
	2213	+
	2214	+ u8 no_buffer_discard_uc_low[0x20];
	2215	+
	2216	+ u8 reserved_at_80[0x740];
	2217	+};
	2218	+
	2219	+struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
	2220	+ u8 wred_discard_high[0x20];
	2221	+
	2222	+ u8 wred_discard_low[0x20];
	2223	+
	2224	+ u8 ecn_marked_tc_high[0x20];
	2225	+
	2226	+ u8 ecn_marked_tc_low[0x20];
	2227	+
	2228	+ u8 reserved_at_80[0x740];
1635	2229	};
1636	2230
1637	2231	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
..	..	@@ -1675,7 +2269,9 @@
1675	2269
1676	2270	u8 rx_pause_transition_low[0x20];
1677	2271
1678		- u8 reserved_at_3c0[0x40];
	2272	+ u8 rx_discards_high[0x20];
	2273	+
	2274	+ u8 rx_discards_low[0x20];
1679	2275
1680	2276	u8 device_stall_minor_watermark_cnt_high[0x20];
1681	2277
..	..	@@ -2240,7 +2836,8 @@
2240	2836	u8 st[0x8];
2241	2837	u8 reserved_at_10[0x3];
2242	2838	u8 pm_state[0x2];
2243		- u8 reserved_at_15[0x3];
	2839	+ u8 reserved_at_15[0x1];
	2840	+ u8 req_e2e_credit_mode[0x2];
2244	2841	u8 offload_type[0x4];
2245	2842	u8 end_padding_mode[0x2];
2246	2843	u8 reserved_at_1e[0x2];
..	..	@@ -2361,7 +2958,10 @@
2361	2958
2362	2959	u8 dc_access_key[0x40];
2363	2960
2364		- u8 reserved_at_680[0xc0];
	2961	+ u8 reserved_at_680[0x3];
	2962	+ u8 dbr_umem_valid[0x1];
	2963	+
	2964	+ u8 reserved_at_684[0xbc];
2365	2965	};
2366	2966
2367	2967	struct mlx5_ifc_roce_addr_layout_bits {
..	..	@@ -2392,7 +2992,11 @@
2392	2992	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2393	2993	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2394	2994	struct mlx5_ifc_qos_cap_bits qos_cap;
	2995	+ struct mlx5_ifc_debug_cap_bits debug_cap;
2395	2996	struct mlx5_ifc_fpga_cap_bits fpga_cap;
	2997	+ struct mlx5_ifc_tls_cap_bits tls_cap;
	2998	+ struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
	2999	+ struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
2396	3000	u8 reserved_at_0[0x8000];
2397	3001	};
2398	3002
..	..	@@ -2401,13 +3005,21 @@
2401	3005	MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2402	3006	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2403	3007	MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2404		- MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
	3008	+ MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2405	3009	MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2406	3010	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2407	3011	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2408	3012	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2409	3013	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2410	3014	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
	3015	+ MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
	3016	+ MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
	3017	+};
	3018	+
	3019	+enum {
	3020	+ MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
	3021	+ MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
	3022	+ MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2411	3023	};
2412	3024
2413	3025	struct mlx5_ifc_vlan_bits {
..	..	@@ -2428,25 +3040,29 @@
2428	3040	u8 reserved_at_60[0x10];
2429	3041	u8 action[0x10];
2430	3042
2431		- u8 reserved_at_80[0x8];
	3043	+ u8 extended_destination[0x1];
	3044	+ u8 reserved_at_81[0x1];
	3045	+ u8 flow_source[0x2];
	3046	+ u8 reserved_at_84[0x4];
2432	3047	u8 destination_list_size[0x18];
2433	3048
2434	3049	u8 reserved_at_a0[0x8];
2435	3050	u8 flow_counter_list_size[0x18];
2436	3051
2437		- u8 encap_id[0x20];
	3052	+ u8 packet_reformat_id[0x20];
2438	3053
2439	3054	u8 modify_header_id[0x20];
2440	3055
2441	3056	struct mlx5_ifc_vlan_bits push_vlan_2;
2442	3057
2443		- u8 reserved_at_120[0xe0];
	3058	+ u8 ipsec_obj_id[0x20];
	3059	+ u8 reserved_at_140[0xc0];
2444	3060
2445	3061	struct mlx5_ifc_fte_match_param_bits match_value;
2446	3062
2447	3063	u8 reserved_at_1200[0x600];
2448	3064
2449		- union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
	3065	+ union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
2450	3066	};
2451	3067
2452	3068	enum {
..	..	@@ -2468,7 +3084,8 @@
2468	3084	u8 xrcd[0x18];
2469	3085
2470	3086	u8 page_offset[0x6];
2471		- u8 reserved_at_46[0x2];
	3087	+ u8 reserved_at_46[0x1];
	3088	+ u8 dbr_umem_valid[0x1];
2472	3089	u8 cqn[0x18];
2473	3090
2474	3091	u8 reserved_at_60[0x20];
..	..	@@ -2511,7 +3128,11 @@
2511	3128
2512	3129	u8 transmit_discard_vport_down[0x40];
2513	3130
2514		- u8 reserved_at_140[0xec0];
	3131	+ u8 reserved_at_140[0xa0];
	3132	+
	3133	+ u8 internal_rq_out_of_buffer[0x20];
	3134	+
	3135	+ u8 reserved_at_200[0xe00];
2515	3136	};
2516	3137
2517	3138	struct mlx5_ifc_traffic_counter_bits {
..	..	@@ -2522,7 +3143,8 @@
2522	3143
2523	3144	struct mlx5_ifc_tisc_bits {
2524	3145	u8 strict_lag_tx_port_affinity[0x1];
2525		- u8 reserved_at_1[0x3];
	3146	+ u8 tls_en[0x1];
	3147	+ u8 reserved_at_2[0x2];
2526	3148	u8 lag_tx_port_affinity[0x04];
2527	3149
2528	3150	u8 reserved_at_8[0x4];
..	..	@@ -2536,7 +3158,11 @@
2536	3158
2537	3159	u8 reserved_at_140[0x8];
2538	3160	u8 underlay_qpn[0x18];
2539		- u8 reserved_at_160[0x3a0];
	3161	+
	3162	+ u8 reserved_at_160[0x8];
	3163	+ u8 pd[0x18];
	3164	+
	3165	+ u8 reserved_at_180[0x380];
2540	3166	};
2541	3167
2542	3168	enum {
..	..	@@ -2556,15 +3182,16 @@
2556	3182	};
2557	3183
2558	3184	enum {
2559		- MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2560		- MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
	3185	+ MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
	3186	+ MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2561	3187	};
2562	3188
2563	3189	struct mlx5_ifc_tirc_bits {
2564	3190	u8 reserved_at_0[0x20];
2565	3191
2566	3192	u8 disp_type[0x4];
2567		- u8 reserved_at_24[0x1c];
	3193	+ u8 tls_en[0x1];
	3194	+ u8 reserved_at_25[0x1b];
2568	3195
2569	3196	u8 reserved_at_40[0x40];
2570	3197
..	..	@@ -2693,6 +3320,13 @@
2693	3320	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2694	3321	};
2695	3322
	3323	+enum {
	3324	+ ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
	3325	+ ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
	3326	+ ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
	3327	+ ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
	3328	+};
	3329	+
2696	3330	struct mlx5_ifc_scheduling_context_bits {
2697	3331	u8 element_type[0x8];
2698	3332	u8 reserved_at_8[0x18];
..	..	@@ -2711,17 +3345,20 @@
2711	3345	};
2712	3346
2713	3347	struct mlx5_ifc_rqtc_bits {
2714		- u8 reserved_at_0[0xa0];
	3348	+ u8 reserved_at_0[0xa0];
2715	3349
2716		- u8 reserved_at_a0[0x10];
2717		- u8 rqt_max_size[0x10];
	3350	+ u8 reserved_at_a0[0x5];
	3351	+ u8 list_q_type[0x3];
	3352	+ u8 reserved_at_a8[0x8];
	3353	+ u8 rqt_max_size[0x10];
2718	3354
2719		- u8 reserved_at_c0[0x10];
2720		- u8 rqt_actual_size[0x10];
	3355	+ u8 rq_vhca_id_format[0x1];
	3356	+ u8 reserved_at_c1[0xf];
	3357	+ u8 rqt_actual_size[0x10];
2721	3358
2722		- u8 reserved_at_e0[0x6a0];
	3359	+ u8 reserved_at_e0[0x6a0];
2723	3360
2724		- struct mlx5_ifc_rq_num_bits rq_num[0];
	3361	+ struct mlx5_ifc_rq_num_bits rq_num[];
2725	3362	};
2726	3363
2727	3364	enum {
..	..	@@ -2833,7 +3470,7 @@
2833	3470
2834	3471	u8 reserved_at_7e0[0x20];
2835	3472
2836		- u8 current_uc_mac_address[0][0x40];
	3473	+ u8 current_uc_mac_address[][0x40];
2837	3474	};
2838	3475
2839	3476	enum {
..	..	@@ -2841,6 +3478,7 @@
2841	3478	MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2842	3479	MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2843	3480	MLX5_MKC_ACCESS_MODE_KSM = 0x3,
	3481	+ MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
2844	3482	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2845	3483	};
2846	3484
..	..	@@ -2886,7 +3524,9 @@
2886	3524
2887	3525	u8 translations_octword_size[0x20];
2888	3526
2889		- u8 reserved_at_1c0[0x1b];
	3527	+ u8 reserved_at_1c0[0x19];
	3528	+ u8 relaxed_ordering_read[0x1];
	3529	+ u8 reserved_at_1d9[0x1];
2890	3530	u8 log_page_size[0x5];
2891	3531
2892	3532	u8 reserved_at_1e0[0x20];
..	..	@@ -2951,12 +3591,14 @@
2951	3591	};
2952	3592
2953	3593	struct mlx5_ifc_esw_vport_context_bits {
2954		- u8 reserved_at_0[0x3];
	3594	+ u8 fdb_to_vport_reg_c[0x1];
	3595	+ u8 reserved_at_1[0x2];
2955	3596	u8 vport_svlan_strip[0x1];
2956	3597	u8 vport_cvlan_strip[0x1];
2957	3598	u8 vport_svlan_insert[0x1];
2958	3599	u8 vport_cvlan_insert[0x2];
2959		- u8 reserved_at_8[0x18];
	3600	+ u8 fdb_to_vport_reg_c_id[0x8];
	3601	+ u8 reserved_at_10[0x10];
2960	3602
2961	3603	u8 reserved_at_20[0x20];
2962	3604
..	..	@@ -2967,7 +3609,11 @@
2967	3609	u8 cvlan_pcp[0x3];
2968	3610	u8 cvlan_id[0xc];
2969	3611
2970		- u8 reserved_at_60[0x7a0];
	3612	+ u8 reserved_at_60[0x720];
	3613	+
	3614	+ u8 sw_steering_vport_icm_address_rx[0x40];
	3615	+
	3616	+ u8 sw_steering_vport_icm_address_tx[0x40];
2971	3617	};
2972	3618
2973	3619	enum {
..	..	@@ -3097,7 +3743,8 @@
3097	3743	u8 ecn[0x2];
3098	3744	u8 dscp[0x6];
3099	3745
3100		- u8 reserved_at_1c0[0x40];
	3746	+ u8 reserved_at_1c0[0x20];
	3747	+ u8 ece[0x20];
3101	3748	};
3102	3749
3103	3750	enum {
..	..	@@ -3125,7 +3772,9 @@
3125	3772
3126	3773	struct mlx5_ifc_cqc_bits {
3127	3774	u8 status[0x4];
3128		- u8 reserved_at_4[0x4];
	3775	+ u8 reserved_at_4[0x2];
	3776	+ u8 dbr_umem_valid[0x1];
	3777	+ u8 reserved_at_7[0x1];
3129	3778	u8 cqe_sz[0x3];
3130	3779	u8 cc[0x1];
3131	3780	u8 reserved_at_c[0x1];
..	..	@@ -3266,7 +3915,8 @@
3266	3915	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3267	3916	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3268	3917	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3269		- struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
	3918	+ struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
	3919	+ struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3270	3920	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3271	3921	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3272	3922	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
..	..	@@ -3359,12 +4009,13 @@
3359	4009
3360	4010	u8 reserved_at_40[0x3f];
3361	4011
3362		- u8 force_state[0x1];
	4012	+ u8 state[0x1];
3363	4013	};
3364	4014
3365	4015	enum {
3366	4016	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3367	4017	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
	4018	+ MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3368	4019	};
3369	4020
3370	4021	struct mlx5_ifc_teardown_hca_in_bits {
..	..	@@ -3391,7 +4042,7 @@
3391	4042
3392	4043	struct mlx5_ifc_sqerr2rts_qp_in_bits {
3393	4044	u8 opcode[0x10];
3394		- u8 reserved_at_10[0x10];
	4045	+ u8 uid[0x10];
3395	4046
3396	4047	u8 reserved_at_20[0x10];
3397	4048	u8 op_mod[0x10];
..	..	@@ -3421,7 +4072,7 @@
3421	4072
3422	4073	struct mlx5_ifc_sqd2rts_qp_in_bits {
3423	4074	u8 opcode[0x10];
3424		- u8 reserved_at_10[0x10];
	4075	+ u8 uid[0x10];
3425	4076
3426	4077	u8 reserved_at_20[0x10];
3427	4078	u8 op_mod[0x10];
..	..	@@ -3572,7 +4223,8 @@
3572	4223	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3573	4224	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3574	4225	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3575		- MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
	4226	+ MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
	4227	+ MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
3576	4228	};
3577	4229
3578	4230	struct mlx5_ifc_set_fte_out_bits {
..	..	@@ -3603,7 +4255,8 @@
3603	4255	u8 reserved_at_a0[0x8];
3604	4256	u8 table_id[0x18];
3605	4257
3606		- u8 reserved_at_c0[0x18];
	4258	+ u8 ignore_flow_level[0x1];
	4259	+ u8 reserved_at_c1[0x17];
3607	4260	u8 modify_enable_mask[0x8];
3608	4261
3609	4262	u8 reserved_at_e0[0x20];
..	..	@@ -3621,12 +4274,13 @@
3621	4274
3622	4275	u8 syndrome[0x20];
3623	4276
3624		- u8 reserved_at_40[0x40];
	4277	+ u8 reserved_at_40[0x20];
	4278	+ u8 ece[0x20];
3625	4279	};
3626	4280
3627	4281	struct mlx5_ifc_rts2rts_qp_in_bits {
3628	4282	u8 opcode[0x10];
3629		- u8 reserved_at_10[0x10];
	4283	+ u8 uid[0x10];
3630	4284
3631	4285	u8 reserved_at_20[0x10];
3632	4286	u8 op_mod[0x10];
..	..	@@ -3638,7 +4292,7 @@
3638	4292
3639	4293	u8 opt_param_mask[0x20];
3640	4294
3641		- u8 reserved_at_a0[0x20];
	4295	+ u8 ece[0x20];
3642	4296
3643	4297	struct mlx5_ifc_qpc_bits qpc;
3644	4298
..	..	@@ -3651,12 +4305,13 @@
3651	4305
3652	4306	u8 syndrome[0x20];
3653	4307
3654		- u8 reserved_at_40[0x40];
	4308	+ u8 reserved_at_40[0x20];
	4309	+ u8 ece[0x20];
3655	4310	};
3656	4311
3657	4312	struct mlx5_ifc_rtr2rts_qp_in_bits {
3658	4313	u8 opcode[0x10];
3659		- u8 reserved_at_10[0x10];
	4314	+ u8 uid[0x10];
3660	4315
3661	4316	u8 reserved_at_20[0x10];
3662	4317	u8 op_mod[0x10];
..	..	@@ -3668,7 +4323,7 @@
3668	4323
3669	4324	u8 opt_param_mask[0x20];
3670	4325
3671		- u8 reserved_at_a0[0x20];
	4326	+ u8 ece[0x20];
3672	4327
3673	4328	struct mlx5_ifc_qpc_bits qpc;
3674	4329
..	..	@@ -3681,12 +4336,13 @@
3681	4336
3682	4337	u8 syndrome[0x20];
3683	4338
3684		- u8 reserved_at_40[0x40];
	4339	+ u8 reserved_at_40[0x20];
	4340	+ u8 ece[0x20];
3685	4341	};
3686	4342
3687	4343	struct mlx5_ifc_rst2init_qp_in_bits {
3688	4344	u8 opcode[0x10];
3689		- u8 reserved_at_10[0x10];
	4345	+ u8 uid[0x10];
3690	4346
3691	4347	u8 reserved_at_20[0x10];
3692	4348	u8 op_mod[0x10];
..	..	@@ -3698,7 +4354,7 @@
3698	4354
3699	4355	u8 opt_param_mask[0x20];
3700	4356
3701		- u8 reserved_at_a0[0x20];
	4357	+ u8 ece[0x20];
3702	4358
3703	4359	struct mlx5_ifc_qpc_bits qpc;
3704	4360
..	..	@@ -3741,7 +4397,7 @@
3741	4397
3742	4398	u8 reserved_at_280[0x600];
3743	4399
3744		- u8 pas[0][0x40];
	4400	+ u8 pas[][0x40];
3745	4401	};
3746	4402
3747	4403	struct mlx5_ifc_query_xrc_srq_in_bits {
..	..	@@ -3778,6 +4434,84 @@
3778	4434	enum {
3779	4435	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3780	4436	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
	4437	+ MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
	4438	+};
	4439	+
	4440	+struct mlx5_ifc_arm_monitor_counter_in_bits {
	4441	+ u8 opcode[0x10];
	4442	+ u8 uid[0x10];
	4443	+
	4444	+ u8 reserved_at_20[0x10];
	4445	+ u8 op_mod[0x10];
	4446	+
	4447	+ u8 reserved_at_40[0x20];
	4448	+
	4449	+ u8 reserved_at_60[0x20];
	4450	+};
	4451	+
	4452	+struct mlx5_ifc_arm_monitor_counter_out_bits {
	4453	+ u8 status[0x8];
	4454	+ u8 reserved_at_8[0x18];
	4455	+
	4456	+ u8 syndrome[0x20];
	4457	+
	4458	+ u8 reserved_at_40[0x40];
	4459	+};
	4460	+
	4461	+enum {
	4462	+ MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
	4463	+ MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
	4464	+};
	4465	+
	4466	+enum mlx5_monitor_counter_ppcnt {
	4467	+ MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
	4468	+ MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
	4469	+ MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
	4470	+ MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
	4471	+ MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
	4472	+ MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
	4473	+};
	4474	+
	4475	+enum {
	4476	+ MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
	4477	+};
	4478	+
	4479	+struct mlx5_ifc_monitor_counter_output_bits {
	4480	+ u8 reserved_at_0[0x4];
	4481	+ u8 type[0x4];
	4482	+ u8 reserved_at_8[0x8];
	4483	+ u8 counter[0x10];
	4484	+
	4485	+ u8 counter_group_id[0x20];
	4486	+};
	4487	+
	4488	+#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
	4489	+#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
	4490	+#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
	4491	+ MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
	4492	+
	4493	+struct mlx5_ifc_set_monitor_counter_in_bits {
	4494	+ u8 opcode[0x10];
	4495	+ u8 uid[0x10];
	4496	+
	4497	+ u8 reserved_at_20[0x10];
	4498	+ u8 op_mod[0x10];
	4499	+
	4500	+ u8 reserved_at_40[0x10];
	4501	+ u8 num_of_counters[0x10];
	4502	+
	4503	+ u8 reserved_at_60[0x20];
	4504	+
	4505	+ struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
	4506	+};
	4507	+
	4508	+struct mlx5_ifc_set_monitor_counter_out_bits {
	4509	+ u8 status[0x8];
	4510	+ u8 reserved_at_8[0x18];
	4511	+
	4512	+ u8 syndrome[0x20];
	4513	+
	4514	+ u8 reserved_at_40[0x40];
3781	4515	};
3782	4516
3783	4517	struct mlx5_ifc_query_vport_state_in_bits {
..	..	@@ -3942,7 +4676,7 @@
3942	4676
3943	4677	u8 reserved_at_280[0x600];
3944	4678
3945		- u8 pas[0][0x40];
	4679	+ u8 pas[][0x40];
3946	4680	};
3947	4681
3948	4682	struct mlx5_ifc_query_srq_in_bits {
..	..	@@ -4147,13 +4881,13 @@
4147	4881
4148	4882	u8 opt_param_mask[0x20];
4149	4883
4150		- u8 reserved_at_a0[0x20];
	4884	+ u8 ece[0x20];
4151	4885
4152	4886	struct mlx5_ifc_qpc_bits qpc;
4153	4887
4154	4888	u8 reserved_at_800[0x80];
4155	4889
4156		- u8 pas[0][0x40];
	4890	+ u8 pas[][0x40];
4157	4891	};
4158	4892
4159	4893	struct mlx5_ifc_query_qp_in_bits {
..	..	@@ -4259,7 +4993,19 @@
4259	4993
4260	4994	u8 req_cqe_flush_error[0x20];
4261	4995
4262		- u8 reserved_at_620[0x1e0];
	4996	+ u8 reserved_at_620[0x20];
	4997	+
	4998	+ u8 roce_adp_retrans[0x20];
	4999	+
	5000	+ u8 roce_adp_retrans_to[0x20];
	5001	+
	5002	+ u8 roce_slow_restart[0x20];
	5003	+
	5004	+ u8 roce_slow_restart_cnps[0x20];
	5005	+
	5006	+ u8 roce_slow_restart_trans[0x20];
	5007	+
	5008	+ u8 reserved_at_6e0[0x120];
4263	5009	};
4264	5010
4265	5011	struct mlx5_ifc_query_q_counter_in_bits {
..	..	@@ -4284,7 +5030,8 @@
4284	5030
4285	5031	u8 syndrome[0x20];
4286	5032
4287		- u8 reserved_at_40[0x10];
	5033	+ u8 embedded_cpu_function[0x1];
	5034	+ u8 reserved_at_41[0xf];
4288	5035	u8 function_id[0x10];
4289	5036
4290	5037	u8 num_pages[0x20];
..	..	@@ -4303,7 +5050,8 @@
4303	5050	u8 reserved_at_20[0x10];
4304	5051	u8 op_mod[0x10];
4305	5052
4306		- u8 reserved_at_40[0x10];
	5053	+ u8 embedded_cpu_function[0x1];
	5054	+ u8 reserved_at_41[0xf];
4307	5055	u8 function_id[0x10];
4308	5056
4309	5057	u8 reserved_at_60[0x20];
..	..	@@ -4472,7 +5220,7 @@
4472	5220
4473	5221	u8 reserved_at_40[0x40];
4474	5222
4475		- struct mlx5_ifc_pkey_bits pkey[0];
	5223	+ struct mlx5_ifc_pkey_bits pkey[];
4476	5224	};
4477	5225
4478	5226	struct mlx5_ifc_query_hca_vport_pkey_in_bits {
..	..	@@ -4508,7 +5256,7 @@
4508	5256	u8 gids_num[0x10];
4509	5257	u8 reserved_at_70[0x10];
4510	5258
4511		- struct mlx5_ifc_array128_auto_bits gid[0];
	5259	+ struct mlx5_ifc_array128_auto_bits gid[];
4512	5260	};
4513	5261
4514	5262	struct mlx5_ifc_query_hca_vport_gid_in_bits {
..	..	@@ -4571,7 +5319,87 @@
4571	5319	u8 reserved_at_20[0x10];
4572	5320	u8 op_mod[0x10];
4573	5321
	5322	+ u8 other_function[0x1];
	5323	+ u8 reserved_at_41[0xf];
	5324	+ u8 function_id[0x10];
	5325	+
	5326	+ u8 reserved_at_60[0x20];
	5327	+};
	5328	+
	5329	+struct mlx5_ifc_other_hca_cap_bits {
	5330	+ u8 roce[0x1];
	5331	+ u8 reserved_at_1[0x27f];
	5332	+};
	5333	+
	5334	+struct mlx5_ifc_query_other_hca_cap_out_bits {
	5335	+ u8 status[0x8];
	5336	+ u8 reserved_at_8[0x18];
	5337	+
	5338	+ u8 syndrome[0x20];
	5339	+
4574	5340	u8 reserved_at_40[0x40];
	5341	+
	5342	+ struct mlx5_ifc_other_hca_cap_bits other_capability;
	5343	+};
	5344	+
	5345	+struct mlx5_ifc_query_other_hca_cap_in_bits {
	5346	+ u8 opcode[0x10];
	5347	+ u8 reserved_at_10[0x10];
	5348	+
	5349	+ u8 reserved_at_20[0x10];
	5350	+ u8 op_mod[0x10];
	5351	+
	5352	+ u8 reserved_at_40[0x10];
	5353	+ u8 function_id[0x10];
	5354	+
	5355	+ u8 reserved_at_60[0x20];
	5356	+};
	5357	+
	5358	+struct mlx5_ifc_modify_other_hca_cap_out_bits {
	5359	+ u8 status[0x8];
	5360	+ u8 reserved_at_8[0x18];
	5361	+
	5362	+ u8 syndrome[0x20];
	5363	+
	5364	+ u8 reserved_at_40[0x40];
	5365	+};
	5366	+
	5367	+struct mlx5_ifc_modify_other_hca_cap_in_bits {
	5368	+ u8 opcode[0x10];
	5369	+ u8 reserved_at_10[0x10];
	5370	+
	5371	+ u8 reserved_at_20[0x10];
	5372	+ u8 op_mod[0x10];
	5373	+
	5374	+ u8 reserved_at_40[0x10];
	5375	+ u8 function_id[0x10];
	5376	+ u8 field_select[0x20];
	5377	+
	5378	+ struct mlx5_ifc_other_hca_cap_bits other_capability;
	5379	+};
	5380	+
	5381	+struct mlx5_ifc_flow_table_context_bits {
	5382	+ u8 reformat_en[0x1];
	5383	+ u8 decap_en[0x1];
	5384	+ u8 sw_owner[0x1];
	5385	+ u8 termination_table[0x1];
	5386	+ u8 table_miss_action[0x4];
	5387	+ u8 level[0x8];
	5388	+ u8 reserved_at_10[0x8];
	5389	+ u8 log_size[0x8];
	5390	+
	5391	+ u8 reserved_at_20[0x8];
	5392	+ u8 table_miss_id[0x18];
	5393	+
	5394	+ u8 reserved_at_40[0x8];
	5395	+ u8 lag_master_next_table_id[0x18];
	5396	+
	5397	+ u8 reserved_at_60[0x60];
	5398	+
	5399	+ u8 sw_owner_icm_root_1[0x40];
	5400	+
	5401	+ u8 sw_owner_icm_root_0[0x40];
	5402	+
4575	5403	};
4576	5404
4577	5405	struct mlx5_ifc_query_flow_table_out_bits {
..	..	@@ -4582,12 +5410,7 @@
4582	5410
4583	5411	u8 reserved_at_40[0x80];
4584	5412
4585		- u8 reserved_at_c0[0x8];
4586		- u8 level[0x8];
4587		- u8 reserved_at_d0[0x8];
4588		- u8 log_size[0x8];
4589		-
4590		- u8 reserved_at_e0[0x120];
	5413	+ struct mlx5_ifc_flow_table_context_bits flow_table_context;
4591	5414	};
4592	5415
4593	5416	struct mlx5_ifc_query_flow_table_in_bits {
..	..	@@ -4645,7 +5468,8 @@
4645	5468	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4646	5469	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4647	5470	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4648		- MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
	5471	+ MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
	5472	+ MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
4649	5473	};
4650	5474
4651	5475	struct mlx5_ifc_query_flow_group_out_bits {
..	..	@@ -4700,7 +5524,7 @@
4700	5524
4701	5525	u8 reserved_at_40[0x40];
4702	5526
4703		- struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
	5527	+ struct mlx5_ifc_traffic_counter_bits flow_statistics[];
4704	5528	};
4705	5529
4706	5530	struct mlx5_ifc_query_flow_counter_in_bits {
..	..	@@ -4754,7 +5578,8 @@
4754	5578	};
4755	5579
4756	5580	struct mlx5_ifc_esw_vport_context_fields_select_bits {
4757		- u8 reserved_at_0[0x1c];
	5581	+ u8 reserved_at_0[0x1b];
	5582	+ u8 fdb_to_vport_reg_c_id[0x1];
4758	5583	u8 vport_cvlan_insert[0x1];
4759	5584	u8 vport_svlan_insert[0x1];
4760	5585	u8 vport_cvlan_strip[0x1];
..	..	@@ -4793,7 +5618,7 @@
4793	5618
4794	5619	u8 reserved_at_300[0x580];
4795	5620
4796		- u8 pas[0][0x40];
	5621	+ u8 pas[][0x40];
4797	5622	};
4798	5623
4799	5624	struct mlx5_ifc_query_eq_in_bits {
..	..	@@ -4809,19 +5634,19 @@
4809	5634	u8 reserved_at_60[0x20];
4810	5635	};
4811	5636
4812		-struct mlx5_ifc_encap_header_in_bits {
	5637	+struct mlx5_ifc_packet_reformat_context_in_bits {
4813	5638	u8 reserved_at_0[0x5];
4814		- u8 header_type[0x3];
	5639	+ u8 reformat_type[0x3];
4815	5640	u8 reserved_at_8[0xe];
4816		- u8 encap_header_size[0xa];
	5641	+ u8 reformat_data_size[0xa];
4817	5642
4818	5643	u8 reserved_at_20[0x10];
4819		- u8 encap_header[2][0x8];
	5644	+ u8 reformat_data[2][0x8];
4820	5645
4821		- u8 more_encap_header[0][0x8];
	5646	+ u8 more_reformat_data[][0x8];
4822	5647	};
4823	5648
4824		-struct mlx5_ifc_query_encap_header_out_bits {
	5649	+struct mlx5_ifc_query_packet_reformat_context_out_bits {
4825	5650	u8 status[0x8];
4826	5651	u8 reserved_at_8[0x18];
4827	5652
..	..	@@ -4829,33 +5654,41 @@
4829	5654
4830	5655	u8 reserved_at_40[0xa0];
4831	5656
4832		- struct mlx5_ifc_encap_header_in_bits encap_header[0];
	5657	+ struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
4833	5658	};
4834	5659
4835		-struct mlx5_ifc_query_encap_header_in_bits {
	5660	+struct mlx5_ifc_query_packet_reformat_context_in_bits {
4836	5661	u8 opcode[0x10];
4837	5662	u8 reserved_at_10[0x10];
4838	5663
4839	5664	u8 reserved_at_20[0x10];
4840	5665	u8 op_mod[0x10];
4841	5666
4842		- u8 encap_id[0x20];
	5667	+ u8 packet_reformat_id[0x20];
4843	5668
4844	5669	u8 reserved_at_60[0xa0];
4845	5670	};
4846	5671
4847		-struct mlx5_ifc_alloc_encap_header_out_bits {
	5672	+struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
4848	5673	u8 status[0x8];
4849	5674	u8 reserved_at_8[0x18];
4850	5675
4851	5676	u8 syndrome[0x20];
4852	5677
4853		- u8 encap_id[0x20];
	5678	+ u8 packet_reformat_id[0x20];
4854	5679
4855	5680	u8 reserved_at_60[0x20];
4856	5681	};
4857	5682
4858		-struct mlx5_ifc_alloc_encap_header_in_bits {
	5683	+enum mlx5_reformat_ctx_type {
	5684	+ MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
	5685	+ MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
	5686	+ MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
	5687	+ MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
	5688	+ MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
	5689	+};
	5690	+
	5691	+struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
4859	5692	u8 opcode[0x10];
4860	5693	u8 reserved_at_10[0x10];
4861	5694
..	..	@@ -4864,10 +5697,10 @@
4864	5697
4865	5698	u8 reserved_at_40[0xa0];
4866	5699
4867		- struct mlx5_ifc_encap_header_in_bits encap_header;
	5700	+ struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
4868	5701	};
4869	5702
4870		-struct mlx5_ifc_dealloc_encap_header_out_bits {
	5703	+struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
4871	5704	u8 status[0x8];
4872	5705	u8 reserved_at_8[0x18];
4873	5706
..	..	@@ -4876,14 +5709,14 @@
4876	5709	u8 reserved_at_40[0x40];
4877	5710	};
4878	5711
4879		-struct mlx5_ifc_dealloc_encap_header_in_bits {
	5712	+struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
4880	5713	u8 opcode[0x10];
4881	5714	u8 reserved_at_10[0x10];
4882	5715
4883	5716	u8 reserved_20[0x10];
4884	5717	u8 op_mod[0x10];
4885	5718
4886		- u8 encap_id[0x20];
	5719	+ u8 packet_reformat_id[0x20];
4887	5720
4888	5721	u8 reserved_60[0x20];
4889	5722	};
..	..	@@ -4907,15 +5740,32 @@
4907	5740	u8 data[0x20];
4908	5741	};
4909	5742
4910		-union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4911		- struct mlx5_ifc_set_action_in_bits set_action_in;
4912		- struct mlx5_ifc_add_action_in_bits add_action_in;
	5743	+struct mlx5_ifc_copy_action_in_bits {
	5744	+ u8 action_type[0x4];
	5745	+ u8 src_field[0xc];
	5746	+ u8 reserved_at_10[0x3];
	5747	+ u8 src_offset[0x5];
	5748	+ u8 reserved_at_18[0x3];
	5749	+ u8 length[0x5];
	5750	+
	5751	+ u8 reserved_at_20[0x4];
	5752	+ u8 dst_field[0xc];
	5753	+ u8 reserved_at_30[0x3];
	5754	+ u8 dst_offset[0x5];
	5755	+ u8 reserved_at_38[0x8];
	5756	+};
	5757	+
	5758	+union mlx5_ifc_set_add_copy_action_in_auto_bits {
	5759	+ struct mlx5_ifc_set_action_in_bits set_action_in;
	5760	+ struct mlx5_ifc_add_action_in_bits add_action_in;
	5761	+ struct mlx5_ifc_copy_action_in_bits copy_action_in;
4913	5762	u8 reserved_at_0[0x40];
4914	5763	};
4915	5764
4916	5765	enum {
4917	5766	MLX5_ACTION_TYPE_SET = 0x1,
4918	5767	MLX5_ACTION_TYPE_ADD = 0x2,
	5768	+ MLX5_ACTION_TYPE_COPY = 0x3,
4919	5769	};
4920	5770
4921	5771	enum {
..	..	@@ -4941,7 +5791,21 @@
4941	5791	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4942	5792	MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4943	5793	MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
	5794	+ MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
4944	5795	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
	5796	+ MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
	5797	+ MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
	5798	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
	5799	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
	5800	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
	5801	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
	5802	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
	5803	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
	5804	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
	5805	+ MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
	5806	+ MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
	5807	+ MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
	5808	+ MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
4945	5809	};
4946	5810
4947	5811	struct mlx5_ifc_alloc_modify_header_context_out_bits {
..	..	@@ -4968,7 +5832,7 @@
4968	5832	u8 reserved_at_68[0x10];
4969	5833	u8 num_of_actions[0x8];
4970	5834
4971		- union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
	5835	+ union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
4972	5836	};
4973	5837
4974	5838	struct mlx5_ifc_dealloc_modify_header_context_out_bits {
..	..	@@ -5030,7 +5894,7 @@
5030	5894
5031	5895	u8 reserved_at_280[0x600];
5032	5896
5033		- u8 pas[0][0x40];
	5897	+ u8 pas[][0x40];
5034	5898	};
5035	5899
5036	5900	struct mlx5_ifc_query_cq_in_bits {
..	..	@@ -5181,7 +6045,7 @@
5181	6045
5182	6046	struct mlx5_ifc_qp_2rst_in_bits {
5183	6047	u8 opcode[0x10];
5184		- u8 reserved_at_10[0x10];
	6048	+ u8 uid[0x10];
5185	6049
5186	6050	u8 reserved_at_20[0x10];
5187	6051	u8 op_mod[0x10];
..	..	@@ -5203,7 +6067,7 @@
5203	6067
5204	6068	struct mlx5_ifc_qp_2err_in_bits {
5205	6069	u8 opcode[0x10];
5206		- u8 reserved_at_10[0x10];
	6070	+ u8 uid[0x10];
5207	6071
5208	6072	u8 reserved_at_20[0x10];
5209	6073	u8 op_mod[0x10];
..	..	@@ -5303,7 +6167,7 @@
5303	6167
5304	6168	struct mlx5_ifc_modify_tis_in_bits {
5305	6169	u8 opcode[0x10];
5306		- u8 reserved_at_10[0x10];
	6170	+ u8 uid[0x10];
5307	6171
5308	6172	u8 reserved_at_20[0x10];
5309	6173	u8 op_mod[0x10];
..	..	@@ -5342,7 +6206,7 @@
5342	6206
5343	6207	struct mlx5_ifc_modify_tir_in_bits {
5344	6208	u8 opcode[0x10];
5345		- u8 reserved_at_10[0x10];
	6209	+ u8 uid[0x10];
5346	6210
5347	6211	u8 reserved_at_20[0x10];
5348	6212	u8 op_mod[0x10];
..	..	@@ -5370,7 +6234,7 @@
5370	6234
5371	6235	struct mlx5_ifc_modify_sq_in_bits {
5372	6236	u8 opcode[0x10];
5373		- u8 reserved_at_10[0x10];
	6237	+ u8 uid[0x10];
5374	6238
5375	6239	u8 reserved_at_20[0x10];
5376	6240	u8 op_mod[0x10];
..	..	@@ -5443,7 +6307,7 @@
5443	6307
5444	6308	struct mlx5_ifc_modify_rqt_in_bits {
5445	6309	u8 opcode[0x10];
5446		- u8 reserved_at_10[0x10];
	6310	+ u8 uid[0x10];
5447	6311
5448	6312	u8 reserved_at_20[0x10];
5449	6313	u8 op_mod[0x10];
..	..	@@ -5477,7 +6341,7 @@
5477	6341
5478	6342	struct mlx5_ifc_modify_rq_in_bits {
5479	6343	u8 opcode[0x10];
5480		- u8 reserved_at_10[0x10];
	6344	+ u8 uid[0x10];
5481	6345
5482	6346	u8 reserved_at_20[0x10];
5483	6347	u8 op_mod[0x10];
..	..	@@ -5513,7 +6377,7 @@
5513	6377
5514	6378	struct mlx5_ifc_modify_rmp_in_bits {
5515	6379	u8 opcode[0x10];
5516		- u8 reserved_at_10[0x10];
	6380	+ u8 uid[0x10];
5517	6381
5518	6382	u8 reserved_at_20[0x10];
5519	6383	u8 op_mod[0x10];
..	..	@@ -5543,7 +6407,7 @@
5543	6407	struct mlx5_ifc_modify_nic_vport_field_select_bits {
5544	6408	u8 reserved_at_0[0x12];
5545	6409	u8 affiliation[0x1];
5546		- u8 reserved_at_e[0x1];
	6410	+ u8 reserved_at_13[0x1];
5547	6411	u8 disable_uc_local_lb[0x1];
5548	6412	u8 disable_mc_local_lb[0x1];
5549	6413	u8 node_guid[0x1];
..	..	@@ -5618,7 +6482,7 @@
5618	6482
5619	6483	struct mlx5_ifc_modify_cq_in_bits {
5620	6484	u8 opcode[0x10];
5621		- u8 reserved_at_10[0x10];
	6485	+ u8 uid[0x10];
5622	6486
5623	6487	u8 reserved_at_20[0x10];
5624	6488	u8 op_mod[0x10];
..	..	@@ -5632,12 +6496,12 @@
5632	6496
5633	6497	u8 reserved_at_280[0x60];
5634	6498
5635		- u8 cq_umem_valid[0x1];
	6499	+ u8 cq_umem_valid[0x1];
5636	6500	u8 reserved_at_2e1[0x1f];
5637	6501
5638	6502	u8 reserved_at_300[0x580];
5639	6503
5640		- u8 pas[0][0x40];
	6504	+ u8 pas[][0x40];
5641	6505	};
5642	6506
5643	6507	struct mlx5_ifc_modify_cong_status_out_bits {
..	..	@@ -5701,7 +6565,7 @@
5701	6565
5702	6566	u8 reserved_at_60[0x20];
5703	6567
5704		- u8 pas[0][0x40];
	6568	+ u8 pas[][0x40];
5705	6569	};
5706	6570
5707	6571	enum {
..	..	@@ -5717,12 +6581,13 @@
5717	6581	u8 reserved_at_20[0x10];
5718	6582	u8 op_mod[0x10];
5719	6583
5720		- u8 reserved_at_40[0x10];
	6584	+ u8 embedded_cpu_function[0x1];
	6585	+ u8 reserved_at_41[0xf];
5721	6586	u8 function_id[0x10];
5722	6587
5723	6588	u8 input_num_entries[0x20];
5724	6589
5725		- u8 pas[0][0x40];
	6590	+ u8 pas[][0x40];
5726	6591	};
5727	6592
5728	6593	struct mlx5_ifc_mad_ifc_out_bits {
..	..	@@ -5778,12 +6643,13 @@
5778	6643
5779	6644	u8 syndrome[0x20];
5780	6645
5781		- u8 reserved_at_40[0x40];
	6646	+ u8 reserved_at_40[0x20];
	6647	+ u8 ece[0x20];
5782	6648	};
5783	6649
5784	6650	struct mlx5_ifc_init2rtr_qp_in_bits {
5785	6651	u8 opcode[0x10];
5786		- u8 reserved_at_10[0x10];
	6652	+ u8 uid[0x10];
5787	6653
5788	6654	u8 reserved_at_20[0x10];
5789	6655	u8 op_mod[0x10];
..	..	@@ -5795,7 +6661,7 @@
5795	6661
5796	6662	u8 opt_param_mask[0x20];
5797	6663
5798		- u8 reserved_at_a0[0x20];
	6664	+ u8 ece[0x20];
5799	6665
5800	6666	struct mlx5_ifc_qpc_bits qpc;
5801	6667
..	..	@@ -5808,12 +6674,13 @@
5808	6674
5809	6675	u8 syndrome[0x20];
5810	6676
5811		- u8 reserved_at_40[0x40];
	6677	+ u8 reserved_at_40[0x20];
	6678	+ u8 ece[0x20];
5812	6679	};
5813	6680
5814	6681	struct mlx5_ifc_init2init_qp_in_bits {
5815	6682	u8 opcode[0x10];
5816		- u8 reserved_at_10[0x10];
	6683	+ u8 uid[0x10];
5817	6684
5818	6685	u8 reserved_at_20[0x10];
5819	6686	u8 op_mod[0x10];
..	..	@@ -5825,7 +6692,7 @@
5825	6692
5826	6693	u8 opt_param_mask[0x20];
5827	6694
5828		- u8 reserved_at_a0[0x20];
	6695	+ u8 ece[0x20];
5829	6696
5830	6697	struct mlx5_ifc_qpc_bits qpc;
5831	6698
..	..	@@ -5895,7 +6762,8 @@
5895	6762	u8 reserved_at_20[0x10];
5896	6763	u8 op_mod[0x10];
5897	6764
5898		- u8 reserved_at_40[0x10];
	6765	+ u8 embedded_cpu_function[0x1];
	6766	+ u8 reserved_at_41[0xf];
5899	6767	u8 function_id[0x10];
5900	6768
5901	6769	u8 reserved_at_60[0x20];
..	..	@@ -5912,7 +6780,7 @@
5912	6780
5913	6781	struct mlx5_ifc_drain_dct_in_bits {
5914	6782	u8 opcode[0x10];
5915		- u8 reserved_at_10[0x10];
	6783	+ u8 uid[0x10];
5916	6784
5917	6785	u8 reserved_at_20[0x10];
5918	6786	u8 op_mod[0x10];
..	..	@@ -5939,7 +6807,8 @@
5939	6807	u8 reserved_at_20[0x10];
5940	6808	u8 op_mod[0x10];
5941	6809
5942		- u8 reserved_at_40[0x10];
	6810	+ u8 embedded_cpu_function[0x1];
	6811	+ u8 reserved_at_41[0xf];
5943	6812	u8 function_id[0x10];
5944	6813
5945	6814	u8 reserved_at_60[0x20];
..	..	@@ -5956,7 +6825,7 @@
5956	6825
5957	6826	struct mlx5_ifc_detach_from_mcg_in_bits {
5958	6827	u8 opcode[0x10];
5959		- u8 reserved_at_10[0x10];
	6828	+ u8 uid[0x10];
5960	6829
5961	6830	u8 reserved_at_20[0x10];
5962	6831	u8 op_mod[0x10];
..	..	@@ -5980,7 +6849,7 @@
5980	6849
5981	6850	struct mlx5_ifc_destroy_xrq_in_bits {
5982	6851	u8 opcode[0x10];
5983		- u8 reserved_at_10[0x10];
	6852	+ u8 uid[0x10];
5984	6853
5985	6854	u8 reserved_at_20[0x10];
5986	6855	u8 op_mod[0x10];
..	..	@@ -6002,7 +6871,7 @@
6002	6871
6003	6872	struct mlx5_ifc_destroy_xrc_srq_in_bits {
6004	6873	u8 opcode[0x10];
6005		- u8 reserved_at_10[0x10];
	6874	+ u8 uid[0x10];
6006	6875
6007	6876	u8 reserved_at_20[0x10];
6008	6877	u8 op_mod[0x10];
..	..	@@ -6024,7 +6893,7 @@
6024	6893
6025	6894	struct mlx5_ifc_destroy_tis_in_bits {
6026	6895	u8 opcode[0x10];
6027		- u8 reserved_at_10[0x10];
	6896	+ u8 uid[0x10];
6028	6897
6029	6898	u8 reserved_at_20[0x10];
6030	6899	u8 op_mod[0x10];
..	..	@@ -6046,7 +6915,7 @@
6046	6915
6047	6916	struct mlx5_ifc_destroy_tir_in_bits {
6048	6917	u8 opcode[0x10];
6049		- u8 reserved_at_10[0x10];
	6918	+ u8 uid[0x10];
6050	6919
6051	6920	u8 reserved_at_20[0x10];
6052	6921	u8 op_mod[0x10];
..	..	@@ -6068,7 +6937,7 @@
6068	6937
6069	6938	struct mlx5_ifc_destroy_srq_in_bits {
6070	6939	u8 opcode[0x10];
6071		- u8 reserved_at_10[0x10];
	6940	+ u8 uid[0x10];
6072	6941
6073	6942	u8 reserved_at_20[0x10];
6074	6943	u8 op_mod[0x10];
..	..	@@ -6090,7 +6959,7 @@
6090	6959
6091	6960	struct mlx5_ifc_destroy_sq_in_bits {
6092	6961	u8 opcode[0x10];
6093		- u8 reserved_at_10[0x10];
	6962	+ u8 uid[0x10];
6094	6963
6095	6964	u8 reserved_at_20[0x10];
6096	6965	u8 op_mod[0x10];
..	..	@@ -6136,7 +7005,7 @@
6136	7005
6137	7006	struct mlx5_ifc_destroy_rqt_in_bits {
6138	7007	u8 opcode[0x10];
6139		- u8 reserved_at_10[0x10];
	7008	+ u8 uid[0x10];
6140	7009
6141	7010	u8 reserved_at_20[0x10];
6142	7011	u8 op_mod[0x10];
..	..	@@ -6158,7 +7027,7 @@
6158	7027
6159	7028	struct mlx5_ifc_destroy_rq_in_bits {
6160	7029	u8 opcode[0x10];
6161		- u8 reserved_at_10[0x10];
	7030	+ u8 uid[0x10];
6162	7031
6163	7032	u8 reserved_at_20[0x10];
6164	7033	u8 op_mod[0x10];
..	..	@@ -6202,7 +7071,7 @@
6202	7071
6203	7072	struct mlx5_ifc_destroy_rmp_in_bits {
6204	7073	u8 opcode[0x10];
6205		- u8 reserved_at_10[0x10];
	7074	+ u8 uid[0x10];
6206	7075
6207	7076	u8 reserved_at_20[0x10];
6208	7077	u8 op_mod[0x10];
..	..	@@ -6224,7 +7093,7 @@
6224	7093
6225	7094	struct mlx5_ifc_destroy_qp_in_bits {
6226	7095	u8 opcode[0x10];
6227		- u8 reserved_at_10[0x10];
	7096	+ u8 uid[0x10];
6228	7097
6229	7098	u8 reserved_at_20[0x10];
6230	7099	u8 op_mod[0x10];
..	..	@@ -6268,7 +7137,7 @@
6268	7137
6269	7138	struct mlx5_ifc_destroy_mkey_in_bits {
6270	7139	u8 opcode[0x10];
6271		- u8 reserved_at_10[0x10];
	7140	+ u8 uid[0x10];
6272	7141
6273	7142	u8 reserved_at_20[0x10];
6274	7143	u8 op_mod[0x10];
..	..	@@ -6376,7 +7245,7 @@
6376	7245
6377	7246	struct mlx5_ifc_destroy_dct_in_bits {
6378	7247	u8 opcode[0x10];
6379		- u8 reserved_at_10[0x10];
	7248	+ u8 uid[0x10];
6380	7249
6381	7250	u8 reserved_at_20[0x10];
6382	7251	u8 op_mod[0x10];
..	..	@@ -6398,7 +7267,7 @@
6398	7267
6399	7268	struct mlx5_ifc_destroy_cq_in_bits {
6400	7269	u8 opcode[0x10];
6401		- u8 reserved_at_10[0x10];
	7270	+ u8 uid[0x10];
6402	7271
6403	7272	u8 reserved_at_20[0x10];
6404	7273	u8 op_mod[0x10];
..	..	@@ -6501,7 +7370,7 @@
6501	7370
6502	7371	struct mlx5_ifc_dealloc_xrcd_in_bits {
6503	7372	u8 opcode[0x10];
6504		- u8 reserved_at_10[0x10];
	7373	+ u8 uid[0x10];
6505	7374
6506	7375	u8 reserved_at_20[0x10];
6507	7376	u8 op_mod[0x10];
..	..	@@ -6545,7 +7414,7 @@
6545	7414
6546	7415	struct mlx5_ifc_dealloc_transport_domain_in_bits {
6547	7416	u8 opcode[0x10];
6548		- u8 reserved_at_10[0x10];
	7417	+ u8 uid[0x10];
6549	7418
6550	7419	u8 reserved_at_20[0x10];
6551	7420	u8 op_mod[0x10];
..	..	@@ -6589,7 +7458,7 @@
6589	7458
6590	7459	struct mlx5_ifc_dealloc_pd_in_bits {
6591	7460	u8 opcode[0x10];
6592		- u8 reserved_at_10[0x10];
	7461	+ u8 uid[0x10];
6593	7462
6594	7463	u8 reserved_at_20[0x10];
6595	7464	u8 op_mod[0x10];
..	..	@@ -6635,7 +7504,7 @@
6635	7504
6636	7505	struct mlx5_ifc_create_xrq_in_bits {
6637	7506	u8 opcode[0x10];
6638		- u8 reserved_at_10[0x10];
	7507	+ u8 uid[0x10];
6639	7508
6640	7509	u8 reserved_at_20[0x10];
6641	7510	u8 op_mod[0x10];
..	..	@@ -6659,7 +7528,7 @@
6659	7528
6660	7529	struct mlx5_ifc_create_xrc_srq_in_bits {
6661	7530	u8 opcode[0x10];
6662		- u8 reserved_at_10[0x10];
	7531	+ u8 uid[0x10];
6663	7532
6664	7533	u8 reserved_at_20[0x10];
6665	7534	u8 op_mod[0x10];
..	..	@@ -6668,9 +7537,14 @@
6668	7537
6669	7538	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6670	7539
6671		- u8 reserved_at_280[0x600];
	7540	+ u8 reserved_at_280[0x60];
6672	7541
6673		- u8 pas[0][0x40];
	7542	+ u8 xrc_srq_umem_valid[0x1];
	7543	+ u8 reserved_at_2e1[0x1f];
	7544	+
	7545	+ u8 reserved_at_300[0x580];
	7546	+
	7547	+ u8 pas[][0x40];
6674	7548	};
6675	7549
6676	7550	struct mlx5_ifc_create_tis_out_bits {
..	..	@@ -6687,7 +7561,7 @@
6687	7561
6688	7562	struct mlx5_ifc_create_tis_in_bits {
6689	7563	u8 opcode[0x10];
6690		- u8 reserved_at_10[0x10];
	7564	+ u8 uid[0x10];
6691	7565
6692	7566	u8 reserved_at_20[0x10];
6693	7567	u8 op_mod[0x10];
..	..	@@ -6699,19 +7573,19 @@
6699	7573
6700	7574	struct mlx5_ifc_create_tir_out_bits {
6701	7575	u8 status[0x8];
6702		- u8 reserved_at_8[0x18];
	7576	+ u8 icm_address_63_40[0x18];
6703	7577
6704	7578	u8 syndrome[0x20];
6705	7579
6706		- u8 reserved_at_40[0x8];
	7580	+ u8 icm_address_39_32[0x8];
6707	7581	u8 tirn[0x18];
6708	7582
6709		- u8 reserved_at_60[0x20];
	7583	+ u8 icm_address_31_0[0x20];
6710	7584	};
6711	7585
6712	7586	struct mlx5_ifc_create_tir_in_bits {
6713	7587	u8 opcode[0x10];
6714		- u8 reserved_at_10[0x10];
	7588	+ u8 uid[0x10];
6715	7589
6716	7590	u8 reserved_at_20[0x10];
6717	7591	u8 op_mod[0x10];
..	..	@@ -6735,7 +7609,7 @@
6735	7609
6736	7610	struct mlx5_ifc_create_srq_in_bits {
6737	7611	u8 opcode[0x10];
6738		- u8 reserved_at_10[0x10];
	7612	+ u8 uid[0x10];
6739	7613
6740	7614	u8 reserved_at_20[0x10];
6741	7615	u8 op_mod[0x10];
..	..	@@ -6746,7 +7620,7 @@
6746	7620
6747	7621	u8 reserved_at_280[0x600];
6748	7622
6749		- u8 pas[0][0x40];
	7623	+ u8 pas[][0x40];
6750	7624	};
6751	7625
6752	7626	struct mlx5_ifc_create_sq_out_bits {
..	..	@@ -6763,7 +7637,7 @@
6763	7637
6764	7638	struct mlx5_ifc_create_sq_in_bits {
6765	7639	u8 opcode[0x10];
6766		- u8 reserved_at_10[0x10];
	7640	+ u8 uid[0x10];
6767	7641
6768	7642	u8 reserved_at_20[0x10];
6769	7643	u8 op_mod[0x10];
..	..	@@ -6817,7 +7691,7 @@
6817	7691
6818	7692	struct mlx5_ifc_create_rqt_in_bits {
6819	7693	u8 opcode[0x10];
6820		- u8 reserved_at_10[0x10];
	7694	+ u8 uid[0x10];
6821	7695
6822	7696	u8 reserved_at_20[0x10];
6823	7697	u8 op_mod[0x10];
..	..	@@ -6841,7 +7715,7 @@
6841	7715
6842	7716	struct mlx5_ifc_create_rq_in_bits {
6843	7717	u8 opcode[0x10];
6844		- u8 reserved_at_10[0x10];
	7718	+ u8 uid[0x10];
6845	7719
6846	7720	u8 reserved_at_20[0x10];
6847	7721	u8 op_mod[0x10];
..	..	@@ -6865,7 +7739,7 @@
6865	7739
6866	7740	struct mlx5_ifc_create_rmp_in_bits {
6867	7741	u8 opcode[0x10];
6868		- u8 reserved_at_10[0x10];
	7742	+ u8 uid[0x10];
6869	7743
6870	7744	u8 reserved_at_20[0x10];
6871	7745	u8 op_mod[0x10];
..	..	@@ -6884,27 +7758,32 @@
6884	7758	u8 reserved_at_40[0x8];
6885	7759	u8 qpn[0x18];
6886	7760
6887		- u8 reserved_at_60[0x20];
	7761	+ u8 ece[0x20];
6888	7762	};
6889	7763
6890	7764	struct mlx5_ifc_create_qp_in_bits {
6891	7765	u8 opcode[0x10];
6892		- u8 reserved_at_10[0x10];
	7766	+ u8 uid[0x10];
6893	7767
6894	7768	u8 reserved_at_20[0x10];
6895	7769	u8 op_mod[0x10];
6896	7770
6897		- u8 reserved_at_40[0x40];
	7771	+ u8 reserved_at_40[0x8];
	7772	+ u8 input_qpn[0x18];
6898	7773
	7774	+ u8 reserved_at_60[0x20];
6899	7775	u8 opt_param_mask[0x20];
6900	7776
6901		- u8 reserved_at_a0[0x20];
	7777	+ u8 ece[0x20];
6902	7778
6903	7779	struct mlx5_ifc_qpc_bits qpc;
6904	7780
6905		- u8 reserved_at_800[0x80];
	7781	+ u8 reserved_at_800[0x60];
6906	7782
6907		- u8 pas[0][0x40];
	7783	+ u8 wq_umem_valid[0x1];
	7784	+ u8 reserved_at_861[0x1f];
	7785	+
	7786	+ u8 pas[][0x40];
6908	7787	};
6909	7788
6910	7789	struct mlx5_ifc_create_psv_out_bits {
..	..	@@ -6956,7 +7835,7 @@
6956	7835
6957	7836	struct mlx5_ifc_create_mkey_in_bits {
6958	7837	u8 opcode[0x10];
6959		- u8 reserved_at_10[0x10];
	7838	+ u8 uid[0x10];
6960	7839
6961	7840	u8 reserved_at_20[0x10];
6962	7841	u8 op_mod[0x10];
..	..	@@ -6964,7 +7843,8 @@
6964	7843	u8 reserved_at_40[0x20];
6965	7844
6966	7845	u8 pg_access[0x1];
6967		- u8 reserved_at_61[0x1f];
	7846	+ u8 mkey_umem_valid[0x1];
	7847	+ u8 reserved_at_62[0x1e];
6968	7848
6969	7849	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6970	7850
..	..	@@ -6974,37 +7854,29 @@
6974	7854
6975	7855	u8 reserved_at_320[0x560];
6976	7856
6977		- u8 klm_pas_mtt[0][0x20];
	7857	+ u8 klm_pas_mtt[][0x20];
	7858	+};
	7859	+
	7860	+enum {
	7861	+ MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
	7862	+ MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
	7863	+ MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
	7864	+ MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
	7865	+ MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
	7866	+ MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
	7867	+ MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
6978	7868	};
6979	7869
6980	7870	struct mlx5_ifc_create_flow_table_out_bits {
6981	7871	u8 status[0x8];
6982		- u8 reserved_at_8[0x18];
	7872	+ u8 icm_address_63_40[0x18];
6983	7873
6984	7874	u8 syndrome[0x20];
6985	7875
6986		- u8 reserved_at_40[0x8];
	7876	+ u8 icm_address_39_32[0x8];
6987	7877	u8 table_id[0x18];
6988	7878
6989		- u8 reserved_at_60[0x20];
6990		-};
6991		-
6992		-struct mlx5_ifc_flow_table_context_bits {
6993		- u8 encap_en[0x1];
6994		- u8 decap_en[0x1];
6995		- u8 reserved_at_2[0x2];
6996		- u8 table_miss_action[0x4];
6997		- u8 level[0x8];
6998		- u8 reserved_at_10[0x8];
6999		- u8 log_size[0x8];
7000		-
7001		- u8 reserved_at_20[0x8];
7002		- u8 table_miss_id[0x18];
7003		-
7004		- u8 reserved_at_40[0x8];
7005		- u8 lag_master_next_table_id[0x18];
7006		-
7007		- u8 reserved_at_60[0xe0];
	7879	+ u8 icm_address_31_0[0x20];
7008	7880	};
7009	7881
7010	7882	struct mlx5_ifc_create_flow_table_in_bits {
..	..	@@ -7100,7 +7972,7 @@
7100	7972
7101	7973	struct mlx5_ifc_create_eq_in_bits {
7102	7974	u8 opcode[0x10];
7103		- u8 reserved_at_10[0x10];
	7975	+ u8 uid[0x10];
7104	7976
7105	7977	u8 reserved_at_20[0x10];
7106	7978	u8 op_mod[0x10];
..	..	@@ -7111,11 +7983,11 @@
7111	7983
7112	7984	u8 reserved_at_280[0x40];
7113	7985
7114		- u8 event_bitmask[0x40];
	7986	+ u8 event_bitmask[4][0x40];
7115	7987
7116		- u8 reserved_at_300[0x580];
	7988	+ u8 reserved_at_3c0[0x4c0];
7117	7989
7118		- u8 pas[0][0x40];
	7990	+ u8 pas[][0x40];
7119	7991	};
7120	7992
7121	7993	struct mlx5_ifc_create_dct_out_bits {
..	..	@@ -7127,12 +7999,12 @@
7127	7999	u8 reserved_at_40[0x8];
7128	8000	u8 dctn[0x18];
7129	8001
7130		- u8 reserved_at_60[0x20];
	8002	+ u8 ece[0x20];
7131	8003	};
7132	8004
7133	8005	struct mlx5_ifc_create_dct_in_bits {
7134	8006	u8 opcode[0x10];
7135		- u8 reserved_at_10[0x10];
	8007	+ u8 uid[0x10];
7136	8008
7137	8009	u8 reserved_at_20[0x10];
7138	8010	u8 op_mod[0x10];
..	..	@@ -7158,7 +8030,7 @@
7158	8030
7159	8031	struct mlx5_ifc_create_cq_in_bits {
7160	8032	u8 opcode[0x10];
7161		- u8 reserved_at_10[0x10];
	8033	+ u8 uid[0x10];
7162	8034
7163	8035	u8 reserved_at_20[0x10];
7164	8036	u8 op_mod[0x10];
..	..	@@ -7167,9 +8039,12 @@
7167	8039
7168	8040	struct mlx5_ifc_cqc_bits cq_context;
7169	8041
7170		- u8 reserved_at_280[0x600];
	8042	+ u8 reserved_at_280[0x60];
7171	8043
7172		- u8 pas[0][0x40];
	8044	+ u8 cq_umem_valid[0x1];
	8045	+ u8 reserved_at_2e1[0x59f];
	8046	+
	8047	+ u8 pas[][0x40];
7173	8048	};
7174	8049
7175	8050	struct mlx5_ifc_config_int_moderation_out_bits {
..	..	@@ -7215,7 +8090,7 @@
7215	8090
7216	8091	struct mlx5_ifc_attach_to_mcg_in_bits {
7217	8092	u8 opcode[0x10];
7218		- u8 reserved_at_10[0x10];
	8093	+ u8 uid[0x10];
7219	8094
7220	8095	u8 reserved_at_20[0x10];
7221	8096	u8 op_mod[0x10];
..	..	@@ -7266,7 +8141,7 @@
7266	8141
7267	8142	struct mlx5_ifc_arm_xrc_srq_in_bits {
7268	8143	u8 opcode[0x10];
7269		- u8 reserved_at_10[0x10];
	8144	+ u8 uid[0x10];
7270	8145
7271	8146	u8 reserved_at_20[0x10];
7272	8147	u8 op_mod[0x10];
..	..	@@ -7294,7 +8169,7 @@
7294	8169
7295	8170	struct mlx5_ifc_arm_rq_in_bits {
7296	8171	u8 opcode[0x10];
7297		- u8 reserved_at_10[0x10];
	8172	+ u8 uid[0x10];
7298	8173
7299	8174	u8 reserved_at_20[0x10];
7300	8175	u8 op_mod[0x10];
..	..	@@ -7342,7 +8217,7 @@
7342	8217
7343	8218	struct mlx5_ifc_alloc_xrcd_in_bits {
7344	8219	u8 opcode[0x10];
7345		- u8 reserved_at_10[0x10];
	8220	+ u8 uid[0x10];
7346	8221
7347	8222	u8 reserved_at_20[0x10];
7348	8223	u8 op_mod[0x10];
..	..	@@ -7386,7 +8261,7 @@
7386	8261
7387	8262	struct mlx5_ifc_alloc_transport_domain_in_bits {
7388	8263	u8 opcode[0x10];
7389		- u8 reserved_at_10[0x10];
	8264	+ u8 uid[0x10];
7390	8265
7391	8266	u8 reserved_at_20[0x10];
7392	8267	u8 op_mod[0x10];
..	..	@@ -7408,7 +8283,7 @@
7408	8283
7409	8284	struct mlx5_ifc_alloc_q_counter_in_bits {
7410	8285	u8 opcode[0x10];
7411		- u8 reserved_at_10[0x10];
	8286	+ u8 uid[0x10];
7412	8287
7413	8288	u8 reserved_at_20[0x10];
7414	8289	u8 op_mod[0x10];
..	..	@@ -7430,7 +8305,7 @@
7430	8305
7431	8306	struct mlx5_ifc_alloc_pd_in_bits {
7432	8307	u8 opcode[0x10];
7433		- u8 reserved_at_10[0x10];
	8308	+ u8 uid[0x10];
7434	8309
7435	8310	u8 reserved_at_20[0x10];
7436	8311	u8 op_mod[0x10];
..	..	@@ -7456,7 +8331,9 @@
7456	8331	u8 reserved_at_20[0x10];
7457	8332	u8 op_mod[0x10];
7458	8333
7459		- u8 reserved_at_40[0x40];
	8334	+ u8 reserved_at_40[0x33];
	8335	+ u8 flow_counter_bulk_log_size[0x5];
	8336	+ u8 flow_counter_bulk[0x8];
7460	8337	};
7461	8338
7462	8339	struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
..	..	@@ -7490,9 +8367,20 @@
7490	8367	u8 reserved_at_40[0x40];
7491	8368	};
7492	8369
	8370	+struct mlx5_ifc_set_pp_rate_limit_context_bits {
	8371	+ u8 rate_limit[0x20];
	8372	+
	8373	+ u8 burst_upper_bound[0x20];
	8374	+
	8375	+ u8 reserved_at_40[0x10];
	8376	+ u8 typical_packet_size[0x10];
	8377	+
	8378	+ u8 reserved_at_60[0x120];
	8379	+};
	8380	+
7493	8381	struct mlx5_ifc_set_pp_rate_limit_in_bits {
7494	8382	u8 opcode[0x10];
7495		- u8 reserved_at_10[0x10];
	8383	+ u8 uid[0x10];
7496	8384
7497	8385	u8 reserved_at_20[0x10];
7498	8386	u8 op_mod[0x10];
..	..	@@ -7502,14 +8390,7 @@
7502	8390
7503	8391	u8 reserved_at_60[0x20];
7504	8392
7505		- u8 rate_limit[0x20];
7506		-
7507		- u8 burst_upper_bound[0x20];
7508		-
7509		- u8 reserved_at_c0[0x10];
7510		- u8 typical_packet_size[0x10];
7511		-
7512		- u8 reserved_at_e0[0x120];
	8393	+ struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7513	8394	};
7514	8395
7515	8396	struct mlx5_ifc_access_register_out_bits {
..	..	@@ -7520,7 +8401,7 @@
7520	8401
7521	8402	u8 reserved_at_40[0x40];
7522	8403
7523		- u8 register_data[0][0x20];
	8404	+ u8 register_data[][0x20];
7524	8405	};
7525	8406
7526	8407	enum {
..	..	@@ -7540,7 +8421,7 @@
7540	8421
7541	8422	u8 argument[0x20];
7542	8423
7543		- u8 register_data[0][0x20];
	8424	+ u8 register_data[][0x20];
7544	8425	};
7545	8426
7546	8427	struct mlx5_ifc_sltp_reg_bits {
..	..	@@ -7645,21 +8526,24 @@
7645	8526	u8 proto_mask[0x3];
7646	8527
7647	8528	u8 an_status[0x4];
7648		- u8 reserved_at_24[0x3c];
	8529	+ u8 reserved_at_24[0xc];
	8530	+ u8 data_rate_oper[0x10];
	8531	+
	8532	+ u8 ext_eth_proto_capability[0x20];
7649	8533
7650	8534	u8 eth_proto_capability[0x20];
7651	8535
7652	8536	u8 ib_link_width_capability[0x10];
7653	8537	u8 ib_proto_capability[0x10];
7654	8538
7655		- u8 reserved_at_a0[0x20];
	8539	+ u8 ext_eth_proto_admin[0x20];
7656	8540
7657	8541	u8 eth_proto_admin[0x20];
7658	8542
7659	8543	u8 ib_link_width_admin[0x10];
7660	8544	u8 ib_proto_admin[0x10];
7661	8545
7662		- u8 reserved_at_100[0x20];
	8546	+ u8 ext_eth_proto_oper[0x20];
7663	8547
7664	8548	u8 eth_proto_oper[0x20];
7665	8549
..	..	@@ -7798,20 +8682,48 @@
7798	8682
7799	8683	struct mlx5_ifc_pplm_reg_bits {
7800	8684	u8 reserved_at_0[0x8];
7801		- u8 local_port[0x8];
7802		- u8 reserved_at_10[0x10];
	8685	+ u8 local_port[0x8];
	8686	+ u8 reserved_at_10[0x10];
7803	8687
7804		- u8 reserved_at_20[0x20];
	8688	+ u8 reserved_at_20[0x20];
7805	8689
7806		- u8 port_profile_mode[0x8];
7807		- u8 static_port_profile[0x8];
7808		- u8 active_port_profile[0x8];
7809		- u8 reserved_at_58[0x8];
	8690	+ u8 port_profile_mode[0x8];
	8691	+ u8 static_port_profile[0x8];
	8692	+ u8 active_port_profile[0x8];
	8693	+ u8 reserved_at_58[0x8];
7810	8694
7811		- u8 retransmission_active[0x8];
7812		- u8 fec_mode_active[0x18];
	8695	+ u8 retransmission_active[0x8];
	8696	+ u8 fec_mode_active[0x18];
7813	8697
7814		- u8 reserved_at_80[0x20];
	8698	+ u8 rs_fec_correction_bypass_cap[0x4];
	8699	+ u8 reserved_at_84[0x8];
	8700	+ u8 fec_override_cap_56g[0x4];
	8701	+ u8 fec_override_cap_100g[0x4];
	8702	+ u8 fec_override_cap_50g[0x4];
	8703	+ u8 fec_override_cap_25g[0x4];
	8704	+ u8 fec_override_cap_10g_40g[0x4];
	8705	+
	8706	+ u8 rs_fec_correction_bypass_admin[0x4];
	8707	+ u8 reserved_at_a4[0x8];
	8708	+ u8 fec_override_admin_56g[0x4];
	8709	+ u8 fec_override_admin_100g[0x4];
	8710	+ u8 fec_override_admin_50g[0x4];
	8711	+ u8 fec_override_admin_25g[0x4];
	8712	+ u8 fec_override_admin_10g_40g[0x4];
	8713	+
	8714	+ u8 fec_override_cap_400g_8x[0x10];
	8715	+ u8 fec_override_cap_200g_4x[0x10];
	8716	+
	8717	+ u8 fec_override_cap_100g_2x[0x10];
	8718	+ u8 fec_override_cap_50g_1x[0x10];
	8719	+
	8720	+ u8 fec_override_admin_400g_8x[0x10];
	8721	+ u8 fec_override_admin_200g_4x[0x10];
	8722	+
	8723	+ u8 fec_override_admin_100g_2x[0x10];
	8724	+ u8 fec_override_admin_50g_1x[0x10];
	8725	+
	8726	+ u8 reserved_at_140[0x140];
7815	8727	};
7816	8728
7817	8729	struct mlx5_ifc_ppcnt_reg_bits {
..	..	@@ -7826,6 +8738,52 @@
7826	8738	u8 prio_tc[0x3];
7827	8739
7828	8740	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
	8741	+};
	8742	+
	8743	+struct mlx5_ifc_mpein_reg_bits {
	8744	+ u8 reserved_at_0[0x2];
	8745	+ u8 depth[0x6];
	8746	+ u8 pcie_index[0x8];
	8747	+ u8 node[0x8];
	8748	+ u8 reserved_at_18[0x8];
	8749	+
	8750	+ u8 capability_mask[0x20];
	8751	+
	8752	+ u8 reserved_at_40[0x8];
	8753	+ u8 link_width_enabled[0x8];
	8754	+ u8 link_speed_enabled[0x10];
	8755	+
	8756	+ u8 lane0_physical_position[0x8];
	8757	+ u8 link_width_active[0x8];
	8758	+ u8 link_speed_active[0x10];
	8759	+
	8760	+ u8 num_of_pfs[0x10];
	8761	+ u8 num_of_vfs[0x10];
	8762	+
	8763	+ u8 bdf0[0x10];
	8764	+ u8 reserved_at_b0[0x10];
	8765	+
	8766	+ u8 max_read_request_size[0x4];
	8767	+ u8 max_payload_size[0x4];
	8768	+ u8 reserved_at_c8[0x5];
	8769	+ u8 pwr_status[0x3];
	8770	+ u8 port_type[0x4];
	8771	+ u8 reserved_at_d4[0xb];
	8772	+ u8 lane_reversal[0x1];
	8773	+
	8774	+ u8 reserved_at_e0[0x14];
	8775	+ u8 pci_power[0xc];
	8776	+
	8777	+ u8 reserved_at_100[0x20];
	8778	+
	8779	+ u8 device_status[0x10];
	8780	+ u8 port_state[0x8];
	8781	+ u8 reserved_at_138[0x8];
	8782	+
	8783	+ u8 reserved_at_140[0x10];
	8784	+ u8 receiver_detect_result[0x10];
	8785	+
	8786	+ u8 reserved_at_160[0x20];
7829	8787	};
7830	8788
7831	8789	struct mlx5_ifc_mpcnt_reg_bits {
..	..	@@ -8092,11 +9050,16 @@
8092	9050	};
8093	9051
8094	9052	struct mlx5_ifc_pcam_enhanced_features_bits {
8095		- u8 reserved_at_0[0x6d];
	9053	+ u8 reserved_at_0[0x68];
	9054	+ u8 fec_50G_per_lane_in_pplm[0x1];
	9055	+ u8 reserved_at_69[0x4];
8096	9056	u8 rx_icrc_encapsulated_counter[0x1];
8097		- u8 reserved_at_6e[0x8];
	9057	+ u8 reserved_at_6e[0x4];
	9058	+ u8 ptys_extended_ethernet[0x1];
	9059	+ u8 reserved_at_73[0x3];
8098	9060	u8 pfcc_mask[0x1];
8099		- u8 reserved_at_77[0x4];
	9061	+ u8 reserved_at_77[0x3];
	9062	+ u8 per_lane_error_counters[0x1];
8100	9063	u8 rx_buffer_fullness_counters[0x1];
8101	9064	u8 ptys_connector_type[0x1];
8102	9065	u8 reserved_at_7d[0x1];
..	..	@@ -8107,12 +9070,17 @@
8107	9070	struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8108	9071	u8 port_access_reg_cap_mask_127_to_96[0x20];
8109	9072	u8 port_access_reg_cap_mask_95_to_64[0x20];
8110		- u8 port_access_reg_cap_mask_63_to_32[0x20];
	9073	+
	9074	+ u8 port_access_reg_cap_mask_63_to_36[0x1c];
	9075	+ u8 pplm[0x1];
	9076	+ u8 port_access_reg_cap_mask_34_to_32[0x3];
8111	9077
8112	9078	u8 port_access_reg_cap_mask_31_to_13[0x13];
8113	9079	u8 pbmc[0x1];
8114	9080	u8 pptb[0x1];
8115		- u8 port_access_reg_cap_mask_10_to_0[0xb];
	9081	+ u8 port_access_reg_cap_mask_10_to_09[0x2];
	9082	+ u8 ppcnt[0x1];
	9083	+ u8 port_access_reg_cap_mask_07_to_00[0x8];
8116	9084	};
8117	9085
8118	9086	struct mlx5_ifc_pcam_reg_bits {
..	..	@@ -8139,7 +9107,9 @@
8139	9107	};
8140	9108
8141	9109	struct mlx5_ifc_mcam_enhanced_features_bits {
8142		- u8 reserved_at_0[0x74];
	9110	+ u8 reserved_at_0[0x6e];
	9111	+ u8 pci_status_and_power[0x1];
	9112	+ u8 reserved_at_6f[0x5];
8143	9113	u8 mark_tx_action_cnp[0x1];
8144	9114	u8 mark_tx_action_cqe[0x1];
8145	9115	u8 dynamic_tx_overflow[0x1];
..	..	@@ -8156,7 +9126,7 @@
8156	9126	u8 mcda[0x1];
8157	9127	u8 mcc[0x1];
8158	9128	u8 mcqi[0x1];
8159		- u8 reserved_at_1f[0x1];
	9129	+ u8 mcqs[0x1];
8160	9130
8161	9131	u8 regs_95_to_87[0x9];
8162	9132	u8 mpegc[0x1];
..	..	@@ -8164,6 +9134,28 @@
8164	9134	u8 tracer_registers[0x4];
8165	9135
8166	9136	u8 regs_63_to_32[0x20];
	9137	+ u8 regs_31_to_0[0x20];
	9138	+};
	9139	+
	9140	+struct mlx5_ifc_mcam_access_reg_bits1 {
	9141	+ u8 regs_127_to_96[0x20];
	9142	+
	9143	+ u8 regs_95_to_64[0x20];
	9144	+
	9145	+ u8 regs_63_to_32[0x20];
	9146	+
	9147	+ u8 regs_31_to_0[0x20];
	9148	+};
	9149	+
	9150	+struct mlx5_ifc_mcam_access_reg_bits2 {
	9151	+ u8 regs_127_to_99[0x1d];
	9152	+ u8 mirc[0x1];
	9153	+ u8 regs_97_to_96[0x2];
	9154	+
	9155	+ u8 regs_95_to_64[0x20];
	9156	+
	9157	+ u8 regs_63_to_32[0x20];
	9158	+
8167	9159	u8 regs_31_to_0[0x20];
8168	9160	};
8169	9161
..	..	@@ -8177,6 +9169,8 @@
8177	9169
8178	9170	union {
8179	9171	struct mlx5_ifc_mcam_access_reg_bits access_regs;
	9172	+ struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
	9173	+ struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
8180	9174	u8 reserved_at_0[0x80];
8181	9175	} mng_access_reg_cap_mask;
8182	9176
..	..	@@ -8227,6 +9221,18 @@
8227	9221	u8 reserved_at_1c0[0x80];
8228	9222	};
8229	9223
	9224	+struct mlx5_ifc_core_dump_reg_bits {
	9225	+ u8 reserved_at_0[0x18];
	9226	+ u8 core_dump_type[0x8];
	9227	+
	9228	+ u8 reserved_at_20[0x30];
	9229	+ u8 vhca_id[0x10];
	9230	+
	9231	+ u8 reserved_at_60[0x8];
	9232	+ u8 qpn[0x18];
	9233	+ u8 reserved_at_80[0x180];
	9234	+};
	9235	+
8230	9236	struct mlx5_ifc_pcap_reg_bits {
8231	9237	u8 reserved_at_0[0x8];
8232	9238	u8 local_port[0x8];
..	..	@@ -8267,9 +9273,23 @@
8267	9273	struct mlx5_ifc_pcmr_reg_bits {
8268	9274	u8 reserved_at_0[0x8];
8269	9275	u8 local_port[0x8];
8270		- u8 reserved_at_10[0x2e];
	9276	+ u8 reserved_at_10[0x10];
	9277	+
	9278	+ u8 entropy_force_cap[0x1];
	9279	+ u8 entropy_calc_cap[0x1];
	9280	+ u8 entropy_gre_calc_cap[0x1];
	9281	+ u8 reserved_at_23[0xf];
	9282	+ u8 rx_ts_over_crc_cap[0x1];
	9283	+ u8 reserved_at_33[0xb];
8271	9284	u8 fcs_cap[0x1];
8272		- u8 reserved_at_3f[0x1f];
	9285	+ u8 reserved_at_3f[0x1];
	9286	+
	9287	+ u8 entropy_force[0x1];
	9288	+ u8 entropy_calc[0x1];
	9289	+ u8 entropy_gre_calc[0x1];
	9290	+ u8 reserved_at_43[0xf];
	9291	+ u8 rx_ts_over_crc[0x1];
	9292	+ u8 reserved_at_53[0xb];
8273	9293	u8 fcs_chk[0x1];
8274	9294	u8 reserved_at_5f[0x1];
8275	9295	};
..	..	@@ -8287,8 +9307,8 @@
8287	9307	u8 reserved_at_0[0x6];
8288	9308	u8 lossy[0x1];
8289	9309	u8 epsb[0x1];
8290		- u8 reserved_at_8[0xc];
8291		- u8 size[0xc];
	9310	+ u8 reserved_at_8[0x8];
	9311	+ u8 size[0x10];
8292	9312
8293	9313	u8 xoff_threshold[0x10];
8294	9314	u8 xon_threshold[0x10];
..	..	@@ -8426,7 +9446,7 @@
8426	9446	u8 reserved_at_20[0x10];
8427	9447	u8 op_mod[0x10];
8428	9448
8429		- u8 command[0][0x20];
	9449	+ u8 command[][0x20];
8430	9450	};
8431	9451
8432	9452	struct mlx5_ifc_cmd_if_box_bits {
..	..	@@ -8554,7 +9574,8 @@
8554	9574	u8 initializing[0x1];
8555	9575	u8 reserved_at_fe1[0x4];
8556	9576	u8 nic_interface_supported[0x3];
8557		- u8 reserved_at_fe8[0x18];
	9577	+ u8 embedded_cpu[0x1];
	9578	+ u8 reserved_at_fe9[0x17];
8558	9579
8559	9580	struct mlx5_ifc_health_buffer_bits health_buffer;
8560	9581
..	..	@@ -8627,6 +9648,24 @@
8627	9648	u8 reserved_at_40[0x40];
8628	9649	};
8629	9650
	9651	+struct mlx5_ifc_mcqs_reg_bits {
	9652	+ u8 last_index_flag[0x1];
	9653	+ u8 reserved_at_1[0x7];
	9654	+ u8 fw_device[0x8];
	9655	+ u8 component_index[0x10];
	9656	+
	9657	+ u8 reserved_at_20[0x10];
	9658	+ u8 identifier[0x10];
	9659	+
	9660	+ u8 reserved_at_40[0x17];
	9661	+ u8 component_status[0x5];
	9662	+ u8 component_update_state[0x4];
	9663	+
	9664	+ u8 last_update_state_changer_type[0x4];
	9665	+ u8 last_update_state_changer_host_id[0x4];
	9666	+ u8 reserved_at_68[0x18];
	9667	+};
	9668	+
8630	9669	struct mlx5_ifc_mcqi_cap_bits {
8631	9670	u8 supported_info_bitmask[0x20];
8632	9671
..	..	@@ -8647,6 +9686,43 @@
8647	9686	u8 reserved_at_86[0x1a];
8648	9687	};
8649	9688
	9689	+struct mlx5_ifc_mcqi_version_bits {
	9690	+ u8 reserved_at_0[0x2];
	9691	+ u8 build_time_valid[0x1];
	9692	+ u8 user_defined_time_valid[0x1];
	9693	+ u8 reserved_at_4[0x14];
	9694	+ u8 version_string_length[0x8];
	9695	+
	9696	+ u8 version[0x20];
	9697	+
	9698	+ u8 build_time[0x40];
	9699	+
	9700	+ u8 user_defined_time[0x40];
	9701	+
	9702	+ u8 build_tool_version[0x20];
	9703	+
	9704	+ u8 reserved_at_e0[0x20];
	9705	+
	9706	+ u8 version_string[92][0x8];
	9707	+};
	9708	+
	9709	+struct mlx5_ifc_mcqi_activation_method_bits {
	9710	+ u8 pending_server_ac_power_cycle[0x1];
	9711	+ u8 pending_server_dc_power_cycle[0x1];
	9712	+ u8 pending_server_reboot[0x1];
	9713	+ u8 pending_fw_reset[0x1];
	9714	+ u8 auto_activate[0x1];
	9715	+ u8 all_hosts_sync[0x1];
	9716	+ u8 device_hw_reset[0x1];
	9717	+ u8 reserved_at_7[0x19];
	9718	+};
	9719	+
	9720	+union mlx5_ifc_mcqi_reg_data_bits {
	9721	+ struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
	9722	+ struct mlx5_ifc_mcqi_version_bits mcqi_version;
	9723	+ struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
	9724	+};
	9725	+
8650	9726	struct mlx5_ifc_mcqi_reg_bits {
8651	9727	u8 read_pending_component[0x1];
8652	9728	u8 reserved_at_1[0xf];
..	..	@@ -8664,7 +9740,7 @@
8664	9740	u8 reserved_at_a0[0x10];
8665	9741	u8 data_size[0x10];
8666	9742
8667		- u8 data[0][0x20];
	9743	+ union mlx5_ifc_mcqi_reg_data_bits data[];
8668	9744	};
8669	9745
8670	9746	struct mlx5_ifc_mcc_reg_bits {
..	..	@@ -8703,7 +9779,37 @@
8703	9779
8704	9780	u8 reserved_at_60[0x20];
8705	9781
8706		- u8 data[0][0x20];
	9782	+ u8 data[][0x20];
	9783	+};
	9784	+
	9785	+enum {
	9786	+ MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
	9787	+ MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
	9788	+};
	9789	+
	9790	+enum {
	9791	+ MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
	9792	+ MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
	9793	+ MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
	9794	+};
	9795	+
	9796	+struct mlx5_ifc_mfrl_reg_bits {
	9797	+ u8 reserved_at_0[0x20];
	9798	+
	9799	+ u8 reserved_at_20[0x2];
	9800	+ u8 pci_sync_for_fw_update_start[0x1];
	9801	+ u8 pci_sync_for_fw_update_resp[0x2];
	9802	+ u8 rst_type_sel[0x3];
	9803	+ u8 reserved_at_28[0x8];
	9804	+ u8 reset_type[0x8];
	9805	+ u8 reset_level[0x8];
	9806	+};
	9807	+
	9808	+struct mlx5_ifc_mirc_reg_bits {
	9809	+ u8 reserved_at_0[0x18];
	9810	+ u8 status_code[0x8];
	9811	+
	9812	+ u8 reserved_at_20[0x20];
8707	9813	};
8708	9814
8709	9815	union mlx5_ifc_ports_control_registers_document_bits {
..	..	@@ -8714,7 +9820,8 @@
8714	9820	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8715	9821	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8716	9822	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8717		- struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
	9823	+ struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
	9824	+ struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
8718	9825	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8719	9826	struct mlx5_ifc_pamp_reg_bits pamp_reg;
8720	9827	struct mlx5_ifc_paos_reg_bits paos_reg;
..	..	@@ -8738,6 +9845,7 @@
8738	9845	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8739	9846	struct mlx5_ifc_ppad_reg_bits ppad_reg;
8740	9847	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
	9848	+ struct mlx5_ifc_mpein_reg_bits mpein_reg;
8741	9849	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8742	9850	struct mlx5_ifc_pplm_reg_bits pplm_reg;
8743	9851	struct mlx5_ifc_pplr_reg_bits pplr_reg;
..	..	@@ -8759,6 +9867,8 @@
8759	9867	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8760	9868	struct mlx5_ifc_mcc_reg_bits mcc_reg;
8761	9869	struct mlx5_ifc_mcda_reg_bits mcda_reg;
	9870	+ struct mlx5_ifc_mirc_reg_bits mirc_reg;
	9871	+ struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
8762	9872	u8 reserved_at_0[0x60e0];
8763	9873	};
8764	9874
..	..	@@ -8915,6 +10025,34 @@
8915	10025	u8 untagged_buff[0x4];
8916	10026	};
8917	10027
	10028	+struct mlx5_ifc_sbcam_reg_bits {
	10029	+ u8 reserved_at_0[0x8];
	10030	+ u8 feature_group[0x8];
	10031	+ u8 reserved_at_10[0x8];
	10032	+ u8 access_reg_group[0x8];
	10033	+
	10034	+ u8 reserved_at_20[0x20];
	10035	+
	10036	+ u8 sb_access_reg_cap_mask[4][0x20];
	10037	+
	10038	+ u8 reserved_at_c0[0x80];
	10039	+
	10040	+ u8 sb_feature_cap_mask[4][0x20];
	10041	+
	10042	+ u8 reserved_at_1c0[0x40];
	10043	+
	10044	+ u8 cap_total_buffer_size[0x20];
	10045	+
	10046	+ u8 cap_cell_size[0x10];
	10047	+ u8 cap_max_pg_buffers[0x8];
	10048	+ u8 cap_num_pool_supported[0x8];
	10049	+
	10050	+ u8 reserved_at_240[0x8];
	10051	+ u8 cap_sbsr_stat_size[0x8];
	10052	+ u8 cap_max_tclass_data[0x8];
	10053	+ u8 cap_max_cpu_ingress_tclass_sb[0x8];
	10054	+};
	10055	+
8918	10056	struct mlx5_ifc_pbmc_reg_bits {
8919	10057	u8 reserved_at_0[0x8];
8920	10058	u8 local_port[0x8];
..	..	@@ -8976,7 +10114,7 @@
8976	10114	u8 dcbx_cee_cap[0x1];
8977	10115	u8 dcbx_ieee_cap[0x1];
8978	10116	u8 dcbx_standby_cap[0x1];
8979		- u8 reserved_at_0[0x5];
	10117	+ u8 reserved_at_3[0x5];
8980	10118	u8 port_number[0x8];
8981	10119	u8 reserved_at_10[0xa];
8982	10120	u8 max_application_table_size[6];
..	..	@@ -9187,7 +10325,7 @@
9187	10325	u8 opcode[0x10];
9188	10326	u8 uid[0x10];
9189	10327
9190		- u8 reserved_at_20[0x10];
	10328	+ u8 vhca_tunnel_id[0x10];
9191	10329	u8 obj_type[0x10];
9192	10330
9193	10331	u8 obj_id[0x20];
..	..	@@ -9207,32 +10345,151 @@
9207	10345	};
9208	10346
9209	10347	struct mlx5_ifc_umem_bits {
9210		- u8 modify_field_select[0x40];
	10348	+ u8 reserved_at_0[0x80];
9211	10349
9212		- u8 reserved_at_40[0x5b];
	10350	+ u8 reserved_at_80[0x1b];
9213	10351	u8 log_page_size[0x5];
9214	10352
9215	10353	u8 page_offset[0x20];
9216	10354
9217	10355	u8 num_of_mtt[0x40];
9218	10356
9219		- struct mlx5_ifc_mtt_bits mtt[0];
	10357	+ struct mlx5_ifc_mtt_bits mtt[];
9220	10358	};
9221	10359
9222	10360	struct mlx5_ifc_uctx_bits {
	10361	+ u8 cap[0x20];
	10362	+
	10363	+ u8 reserved_at_20[0x160];
	10364	+};
	10365	+
	10366	+struct mlx5_ifc_sw_icm_bits {
9223	10367	u8 modify_field_select[0x40];
9224	10368
9225		- u8 reserved_at_40[0x1c0];
	10369	+ u8 reserved_at_40[0x18];
	10370	+ u8 log_sw_icm_size[0x8];
	10371	+
	10372	+ u8 reserved_at_60[0x20];
	10373	+
	10374	+ u8 sw_icm_start_addr[0x40];
	10375	+
	10376	+ u8 reserved_at_c0[0x140];
	10377	+};
	10378	+
	10379	+struct mlx5_ifc_geneve_tlv_option_bits {
	10380	+ u8 modify_field_select[0x40];
	10381	+
	10382	+ u8 reserved_at_40[0x18];
	10383	+ u8 geneve_option_fte_index[0x8];
	10384	+
	10385	+ u8 option_class[0x10];
	10386	+ u8 option_type[0x8];
	10387	+ u8 reserved_at_78[0x3];
	10388	+ u8 option_data_length[0x5];
	10389	+
	10390	+ u8 reserved_at_80[0x180];
9226	10391	};
9227	10392
9228	10393	struct mlx5_ifc_create_umem_in_bits {
9229		- struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9230		- struct mlx5_ifc_umem_bits umem;
	10394	+ u8 opcode[0x10];
	10395	+ u8 uid[0x10];
	10396	+
	10397	+ u8 reserved_at_20[0x10];
	10398	+ u8 op_mod[0x10];
	10399	+
	10400	+ u8 reserved_at_40[0x40];
	10401	+
	10402	+ struct mlx5_ifc_umem_bits umem;
	10403	+};
	10404	+
	10405	+struct mlx5_ifc_create_umem_out_bits {
	10406	+ u8 status[0x8];
	10407	+ u8 reserved_at_8[0x18];
	10408	+
	10409	+ u8 syndrome[0x20];
	10410	+
	10411	+ u8 reserved_at_40[0x8];
	10412	+ u8 umem_id[0x18];
	10413	+
	10414	+ u8 reserved_at_60[0x20];
	10415	+};
	10416	+
	10417	+struct mlx5_ifc_destroy_umem_in_bits {
	10418	+ u8 opcode[0x10];
	10419	+ u8 uid[0x10];
	10420	+
	10421	+ u8 reserved_at_20[0x10];
	10422	+ u8 op_mod[0x10];
	10423	+
	10424	+ u8 reserved_at_40[0x8];
	10425	+ u8 umem_id[0x18];
	10426	+
	10427	+ u8 reserved_at_60[0x20];
	10428	+};
	10429	+
	10430	+struct mlx5_ifc_destroy_umem_out_bits {
	10431	+ u8 status[0x8];
	10432	+ u8 reserved_at_8[0x18];
	10433	+
	10434	+ u8 syndrome[0x20];
	10435	+
	10436	+ u8 reserved_at_40[0x40];
9231	10437	};
9232	10438
9233	10439	struct mlx5_ifc_create_uctx_in_bits {
	10440	+ u8 opcode[0x10];
	10441	+ u8 reserved_at_10[0x10];
	10442	+
	10443	+ u8 reserved_at_20[0x10];
	10444	+ u8 op_mod[0x10];
	10445	+
	10446	+ u8 reserved_at_40[0x40];
	10447	+
	10448	+ struct mlx5_ifc_uctx_bits uctx;
	10449	+};
	10450	+
	10451	+struct mlx5_ifc_create_uctx_out_bits {
	10452	+ u8 status[0x8];
	10453	+ u8 reserved_at_8[0x18];
	10454	+
	10455	+ u8 syndrome[0x20];
	10456	+
	10457	+ u8 reserved_at_40[0x10];
	10458	+ u8 uid[0x10];
	10459	+
	10460	+ u8 reserved_at_60[0x20];
	10461	+};
	10462	+
	10463	+struct mlx5_ifc_destroy_uctx_in_bits {
	10464	+ u8 opcode[0x10];
	10465	+ u8 reserved_at_10[0x10];
	10466	+
	10467	+ u8 reserved_at_20[0x10];
	10468	+ u8 op_mod[0x10];
	10469	+
	10470	+ u8 reserved_at_40[0x10];
	10471	+ u8 uid[0x10];
	10472	+
	10473	+ u8 reserved_at_60[0x20];
	10474	+};
	10475	+
	10476	+struct mlx5_ifc_destroy_uctx_out_bits {
	10477	+ u8 status[0x8];
	10478	+ u8 reserved_at_8[0x18];
	10479	+
	10480	+ u8 syndrome[0x20];
	10481	+
	10482	+ u8 reserved_at_40[0x40];
	10483	+};
	10484	+
	10485	+struct mlx5_ifc_create_sw_icm_in_bits {
9234	10486	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9235		- struct mlx5_ifc_uctx_bits uctx;
	10487	+ struct mlx5_ifc_sw_icm_bits sw_icm;
	10488	+};
	10489	+
	10490	+struct mlx5_ifc_create_geneve_tlv_option_in_bits {
	10491	+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
	10492	+ struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
9236	10493	};
9237	10494
9238	10495	struct mlx5_ifc_mtrc_string_db_param_bits {
..	..	@@ -9277,7 +10534,7 @@
9277	10534	u8 reserved_at_4[0x4];
9278	10535	u8 read_size[0x18];
9279	10536	u8 start_offset[0x20];
9280		- u8 string_db_data[0];
	10537	+ u8 string_db_data[];
9281	10538	};
9282	10539
9283	10540	struct mlx5_ifc_mtrc_ctrl_bits {
..	..	@@ -9292,4 +10549,259 @@
9292	10549	u8 reserved_at_80[0x180];
9293	10550	};
9294	10551
	10552	+struct mlx5_ifc_host_params_context_bits {
	10553	+ u8 host_number[0x8];
	10554	+ u8 reserved_at_8[0x7];
	10555	+ u8 host_pf_disabled[0x1];
	10556	+ u8 host_num_of_vfs[0x10];
	10557	+
	10558	+ u8 host_total_vfs[0x10];
	10559	+ u8 host_pci_bus[0x10];
	10560	+
	10561	+ u8 reserved_at_40[0x10];
	10562	+ u8 host_pci_device[0x10];
	10563	+
	10564	+ u8 reserved_at_60[0x10];
	10565	+ u8 host_pci_function[0x10];
	10566	+
	10567	+ u8 reserved_at_80[0x180];
	10568	+};
	10569	+
	10570	+struct mlx5_ifc_query_esw_functions_in_bits {
	10571	+ u8 opcode[0x10];
	10572	+ u8 reserved_at_10[0x10];
	10573	+
	10574	+ u8 reserved_at_20[0x10];
	10575	+ u8 op_mod[0x10];
	10576	+
	10577	+ u8 reserved_at_40[0x40];
	10578	+};
	10579	+
	10580	+struct mlx5_ifc_query_esw_functions_out_bits {
	10581	+ u8 status[0x8];
	10582	+ u8 reserved_at_8[0x18];
	10583	+
	10584	+ u8 syndrome[0x20];
	10585	+
	10586	+ u8 reserved_at_40[0x40];
	10587	+
	10588	+ struct mlx5_ifc_host_params_context_bits host_params_context;
	10589	+
	10590	+ u8 reserved_at_280[0x180];
	10591	+ u8 host_sf_enable[][0x40];
	10592	+};
	10593	+
	10594	+struct mlx5_ifc_sf_partition_bits {
	10595	+ u8 reserved_at_0[0x10];
	10596	+ u8 log_num_sf[0x8];
	10597	+ u8 log_sf_bar_size[0x8];
	10598	+};
	10599	+
	10600	+struct mlx5_ifc_query_sf_partitions_out_bits {
	10601	+ u8 status[0x8];
	10602	+ u8 reserved_at_8[0x18];
	10603	+
	10604	+ u8 syndrome[0x20];
	10605	+
	10606	+ u8 reserved_at_40[0x18];
	10607	+ u8 num_sf_partitions[0x8];
	10608	+
	10609	+ u8 reserved_at_60[0x20];
	10610	+
	10611	+ struct mlx5_ifc_sf_partition_bits sf_partition[];
	10612	+};
	10613	+
	10614	+struct mlx5_ifc_query_sf_partitions_in_bits {
	10615	+ u8 opcode[0x10];
	10616	+ u8 reserved_at_10[0x10];
	10617	+
	10618	+ u8 reserved_at_20[0x10];
	10619	+ u8 op_mod[0x10];
	10620	+
	10621	+ u8 reserved_at_40[0x40];
	10622	+};
	10623	+
	10624	+struct mlx5_ifc_dealloc_sf_out_bits {
	10625	+ u8 status[0x8];
	10626	+ u8 reserved_at_8[0x18];
	10627	+
	10628	+ u8 syndrome[0x20];
	10629	+
	10630	+ u8 reserved_at_40[0x40];
	10631	+};
	10632	+
	10633	+struct mlx5_ifc_dealloc_sf_in_bits {
	10634	+ u8 opcode[0x10];
	10635	+ u8 reserved_at_10[0x10];
	10636	+
	10637	+ u8 reserved_at_20[0x10];
	10638	+ u8 op_mod[0x10];
	10639	+
	10640	+ u8 reserved_at_40[0x10];
	10641	+ u8 function_id[0x10];
	10642	+
	10643	+ u8 reserved_at_60[0x20];
	10644	+};
	10645	+
	10646	+struct mlx5_ifc_alloc_sf_out_bits {
	10647	+ u8 status[0x8];
	10648	+ u8 reserved_at_8[0x18];
	10649	+
	10650	+ u8 syndrome[0x20];
	10651	+
	10652	+ u8 reserved_at_40[0x40];
	10653	+};
	10654	+
	10655	+struct mlx5_ifc_alloc_sf_in_bits {
	10656	+ u8 opcode[0x10];
	10657	+ u8 reserved_at_10[0x10];
	10658	+
	10659	+ u8 reserved_at_20[0x10];
	10660	+ u8 op_mod[0x10];
	10661	+
	10662	+ u8 reserved_at_40[0x10];
	10663	+ u8 function_id[0x10];
	10664	+
	10665	+ u8 reserved_at_60[0x20];
	10666	+};
	10667	+
	10668	+struct mlx5_ifc_affiliated_event_header_bits {
	10669	+ u8 reserved_at_0[0x10];
	10670	+ u8 obj_type[0x10];
	10671	+
	10672	+ u8 obj_id[0x20];
	10673	+};
	10674	+
	10675	+enum {
	10676	+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
	10677	+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
	10678	+};
	10679	+
	10680	+enum {
	10681	+ MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
	10682	+ MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
	10683	+};
	10684	+
	10685	+enum {
	10686	+ MLX5_IPSEC_OBJECT_ICV_LEN_16B,
	10687	+ MLX5_IPSEC_OBJECT_ICV_LEN_12B,
	10688	+ MLX5_IPSEC_OBJECT_ICV_LEN_8B,
	10689	+};
	10690	+
	10691	+struct mlx5_ifc_ipsec_obj_bits {
	10692	+ u8 modify_field_select[0x40];
	10693	+ u8 full_offload[0x1];
	10694	+ u8 reserved_at_41[0x1];
	10695	+ u8 esn_en[0x1];
	10696	+ u8 esn_overlap[0x1];
	10697	+ u8 reserved_at_44[0x2];
	10698	+ u8 icv_length[0x2];
	10699	+ u8 reserved_at_48[0x4];
	10700	+ u8 aso_return_reg[0x4];
	10701	+ u8 reserved_at_50[0x10];
	10702	+
	10703	+ u8 esn_msb[0x20];
	10704	+
	10705	+ u8 reserved_at_80[0x8];
	10706	+ u8 dekn[0x18];
	10707	+
	10708	+ u8 salt[0x20];
	10709	+
	10710	+ u8 implicit_iv[0x40];
	10711	+
	10712	+ u8 reserved_at_100[0x700];
	10713	+};
	10714	+
	10715	+struct mlx5_ifc_create_ipsec_obj_in_bits {
	10716	+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
	10717	+ struct mlx5_ifc_ipsec_obj_bits ipsec_object;
	10718	+};
	10719	+
	10720	+enum {
	10721	+ MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
	10722	+ MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
	10723	+};
	10724	+
	10725	+struct mlx5_ifc_query_ipsec_obj_out_bits {
	10726	+ struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
	10727	+ struct mlx5_ifc_ipsec_obj_bits ipsec_object;
	10728	+};
	10729	+
	10730	+struct mlx5_ifc_modify_ipsec_obj_in_bits {
	10731	+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
	10732	+ struct mlx5_ifc_ipsec_obj_bits ipsec_object;
	10733	+};
	10734	+
	10735	+struct mlx5_ifc_encryption_key_obj_bits {
	10736	+ u8 modify_field_select[0x40];
	10737	+
	10738	+ u8 reserved_at_40[0x14];
	10739	+ u8 key_size[0x4];
	10740	+ u8 reserved_at_58[0x4];
	10741	+ u8 key_type[0x4];
	10742	+
	10743	+ u8 reserved_at_60[0x8];
	10744	+ u8 pd[0x18];
	10745	+
	10746	+ u8 reserved_at_80[0x180];
	10747	+ u8 key[8][0x20];
	10748	+
	10749	+ u8 reserved_at_300[0x500];
	10750	+};
	10751	+
	10752	+struct mlx5_ifc_create_encryption_key_in_bits {
	10753	+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
	10754	+ struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
	10755	+};
	10756	+
	10757	+enum {
	10758	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
	10759	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
	10760	+};
	10761	+
	10762	+enum {
	10763	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
	10764	+ MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
	10765	+};
	10766	+
	10767	+struct mlx5_ifc_tls_static_params_bits {
	10768	+ u8 const_2[0x2];
	10769	+ u8 tls_version[0x4];
	10770	+ u8 const_1[0x2];
	10771	+ u8 reserved_at_8[0x14];
	10772	+ u8 encryption_standard[0x4];
	10773	+
	10774	+ u8 reserved_at_20[0x20];
	10775	+
	10776	+ u8 initial_record_number[0x40];
	10777	+
	10778	+ u8 resync_tcp_sn[0x20];
	10779	+
	10780	+ u8 gcm_iv[0x20];
	10781	+
	10782	+ u8 implicit_iv[0x40];
	10783	+
	10784	+ u8 reserved_at_100[0x8];
	10785	+ u8 dek_index[0x18];
	10786	+
	10787	+ u8 reserved_at_120[0xe0];
	10788	+};
	10789	+
	10790	+struct mlx5_ifc_tls_progress_params_bits {
	10791	+ u8 next_record_tcp_sn[0x20];
	10792	+
	10793	+ u8 hw_resync_tcp_sn[0x20];
	10794	+
	10795	+ u8 record_tracker_state[0x2];
	10796	+ u8 auth_state[0x2];
	10797	+ u8 reserved_at_44[0x4];
	10798	+ u8 hw_offset_record_number[0x18];
	10799	+};
	10800	+
	10801	+enum {
	10802	+ MLX5_MTT_PERM_READ = 1 << 0,
	10803	+ MLX5_MTT_PERM_WRITE = 1 << 1,
	10804	+ MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ \| MLX5_MTT_PERM_WRITE,
	10805	+};
	10806	+
9295	10807	#endif /* MLX5_IFC_H */