.. | .. |
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156 | 156 | break; |
---|
157 | 157 | } |
---|
158 | 158 | |
---|
| 159 | + /* For Coverity check */ |
---|
| 160 | + if (idx == DW_WDT_NUM_TOPS) |
---|
| 161 | + idx = 0; |
---|
| 162 | + |
---|
159 | 163 | return dw_wdt->timeouts[idx].sec; |
---|
160 | 164 | } |
---|
161 | 165 | |
---|
.. | .. |
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178 | 182 | if (dw_wdt->timeouts[idx].top_val == top_val) |
---|
179 | 183 | break; |
---|
180 | 184 | } |
---|
| 185 | + |
---|
| 186 | + if (idx == DW_WDT_NUM_TOPS) |
---|
| 187 | + idx = 0; |
---|
181 | 188 | |
---|
182 | 189 | /* |
---|
183 | 190 | * In IRQ mode due to the two stages counter, the actual timeout is |
---|
.. | .. |
---|
638 | 645 | |
---|
639 | 646 | ret = dw_wdt_init_timeouts(dw_wdt, dev); |
---|
640 | 647 | if (ret) |
---|
641 | | - goto out_disable_clk; |
---|
| 648 | + goto out_assert_rst; |
---|
642 | 649 | |
---|
643 | 650 | wdd = &dw_wdt->wdd; |
---|
644 | 651 | wdd->ops = &dw_wdt_ops; |
---|
.. | .. |
---|
669 | 676 | |
---|
670 | 677 | ret = watchdog_register_device(wdd); |
---|
671 | 678 | if (ret) |
---|
672 | | - goto out_disable_pclk; |
---|
| 679 | + goto out_assert_rst; |
---|
673 | 680 | |
---|
674 | 681 | dw_wdt_dbgfs_init(dw_wdt); |
---|
675 | 682 | |
---|
676 | 683 | return 0; |
---|
677 | 684 | |
---|
| 685 | +out_assert_rst: |
---|
| 686 | + reset_control_assert(dw_wdt->rst); |
---|
| 687 | + |
---|
678 | 688 | out_disable_pclk: |
---|
679 | 689 | clk_disable_unprepare(dw_wdt->pclk); |
---|
680 | 690 | |
---|