~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,7 +4,7 @@
4	4	*
5	5	* High-speed serial driver for NVIDIA Tegra SoCs
6	6	*
7		- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
	7	+ * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
8	8	*
9	9	* Author: Laxman Dewangan <ldewangan@nvidia.com>
10	10	*/
..	..	@@ -62,7 +62,7 @@
62	62	#define TEGRA_UART_TX_TRIG_4B 0x20
63	63	#define TEGRA_UART_TX_TRIG_1B 0x30
64	64
65		-#define TEGRA_UART_MAXIMUM 5
	65	+#define TEGRA_UART_MAXIMUM 8
66	66
67	67	/* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68	68	#define TEGRA_UART_DEFAULT_BAUD 115200
..	..	@@ -71,6 +71,8 @@
71	71	/* Tx transfer mode */
72	72	#define TEGRA_TX_PIO 1
73	73	#define TEGRA_TX_DMA 2
	74	+
	75	+#define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
74	76
75	77	/**
76	78	* tegra_uart_chip_data: SOC specific data.
..	..	@@ -84,6 +86,17 @@
84	86	bool tx_fifo_full_status;
85	87	bool allow_txfifo_reset_fifo_mode;
86	88	bool support_clk_src_div;
	89	+ bool fifo_mode_enable_status;
	90	+ int uart_max_port;
	91	+ int max_dma_burst_bytes;
	92	+ int error_tolerance_low_range;
	93	+ int error_tolerance_high_range;
	94	+};
	95	+
	96	+struct tegra_baud_tolerance {
	97	+ u32 lower_range_baud;
	98	+ u32 upper_range_baud;
	99	+ s32 tolerance;
87	100	};
88	101
89	102	struct tegra_uart_port {
..	..	@@ -122,10 +135,19 @@
122	135	dma_cookie_t rx_cookie;
123	136	unsigned int tx_bytes_requested;
124	137	unsigned int rx_bytes_requested;
	138	+ struct tegra_baud_tolerance *baud_tolerance;
	139	+ int n_adjustable_baud_rates;
	140	+ int required_rate;
	141	+ int configured_rate;
	142	+ bool use_rx_pio;
	143	+ bool use_tx_pio;
	144	+ bool rx_dma_active;
125	145	};
126	146
127	147	static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
128	148	static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
	149	+static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
	150	+ bool dma_to_memory);
129	151
130	152	static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
131	153	unsigned long reg)
..	..	@@ -192,16 +214,34 @@
192	214	}
193	215	}
194	216
	217	+static void set_loopbk(struct tegra_uart_port *tup, bool active)
	218	+{
	219	+ unsigned long mcr = tup->mcr_shadow;
	220	+
	221	+ if (active)
	222	+ mcr \|= UART_MCR_LOOP;
	223	+ else
	224	+ mcr &= ~UART_MCR_LOOP;
	225	+
	226	+ if (mcr != tup->mcr_shadow) {
	227	+ tegra_uart_write(tup, mcr, UART_MCR);
	228	+ tup->mcr_shadow = mcr;
	229	+ }
	230	+}
	231	+
195	232	static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
196	233	{
197	234	struct tegra_uart_port *tup = to_tegra_uport(u);
198		- int dtr_enable;
	235	+ int enable;
199	236
200	237	tup->rts_active = !!(mctrl & TIOCM_RTS);
201	238	set_rts(tup, tup->rts_active);
202	239
203		- dtr_enable = !!(mctrl & TIOCM_DTR);
204		- set_dtr(tup, dtr_enable);
	240	+ enable = !!(mctrl & TIOCM_DTR);
	241	+ set_dtr(tup, enable);
	242	+
	243	+ enable = !!(mctrl & TIOCM_LOOP);
	244	+ set_loopbk(tup, enable);
205	245	}
206	246
207	247	static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
..	..	@@ -243,9 +283,28 @@
243	283	tup->current_baud));
244	284	}
245	285
	286	+static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
	287	+{
	288	+ unsigned long iir;
	289	+ unsigned int tmout = 100;
	290	+
	291	+ do {
	292	+ iir = tegra_uart_read(tup, UART_IIR);
	293	+ if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
	294	+ return 0;
	295	+ udelay(1);
	296	+ } while (--tmout);
	297	+
	298	+ return -ETIMEDOUT;
	299	+}
	300	+
246	301	static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
247	302	{
248	303	unsigned long fcr = tup->fcr_shadow;
	304	+ unsigned int lsr, tmout = 10000;
	305	+
	306	+ if (tup->rts_active)
	307	+ set_rts(tup, false);
249	308
250	309	if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251	310	fcr \|= fcr_bits & (UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
..	..	@@ -258,6 +317,8 @@
258	317	tegra_uart_write(tup, fcr, UART_FCR);
259	318	fcr \|= UART_FCR_ENABLE_FIFO;
260	319	tegra_uart_write(tup, fcr, UART_FCR);
	320	+ if (tup->cdata->fifo_mode_enable_status)
	321	+ tegra_uart_wait_fifo_mode_enabled(tup);
261	322	}
262	323
263	324	/* Dummy read to ensure the write is posted */
..	..	@@ -269,6 +330,47 @@
269	330	* to propagate, otherwise data could be lost.
270	331	*/
271	332	tegra_uart_wait_cycle_time(tup, 32);
	333	+
	334	+ do {
	335	+ lsr = tegra_uart_read(tup, UART_LSR);
	336	+ if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
	337	+ break;
	338	+ udelay(1);
	339	+ } while (--tmout);
	340	+
	341	+ if (tup->rts_active)
	342	+ set_rts(tup, true);
	343	+}
	344	+
	345	+static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
	346	+ unsigned int baud, long rate)
	347	+{
	348	+ int i;
	349	+
	350	+ for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
	351	+ if (baud >= tup->baud_tolerance[i].lower_range_baud &&
	352	+ baud <= tup->baud_tolerance[i].upper_range_baud)
	353	+ return (rate + (rate *
	354	+ tup->baud_tolerance[i].tolerance) / 10000);
	355	+ }
	356	+
	357	+ return rate;
	358	+}
	359	+
	360	+static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
	361	+{
	362	+ long diff;
	363	+
	364	+ diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
	365	+ / tup->required_rate;
	366	+ if (diff < (tup->cdata->error_tolerance_low_range * 100) \|\|
	367	+ diff > (tup->cdata->error_tolerance_high_range * 100)) {
	368	+ dev_err(tup->uport.dev,
	369	+ "configured baud rate is out of range by %ld", diff);
	370	+ return -EIO;
	371	+ }
	372	+
	373	+ return 0;
272	374	}
273	375
274	376	static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
..	..	@@ -276,6 +378,7 @@
276	378	unsigned long rate;
277	379	unsigned int divisor;
278	380	unsigned long lcr;
	381	+ unsigned long flags;
279	382	int ret;
280	383
281	384	if (tup->current_baud == baud)
..	..	@@ -283,18 +386,28 @@
283	386
284	387	if (tup->cdata->support_clk_src_div) {
285	388	rate = baud * 16;
	389	+ tup->required_rate = rate;
	390	+
	391	+ if (tup->n_adjustable_baud_rates)
	392	+ rate = tegra_get_tolerance_rate(tup, baud, rate);
	393	+
286	394	ret = clk_set_rate(tup->uart_clk, rate);
287	395	if (ret < 0) {
288	396	dev_err(tup->uport.dev,
289	397	"clk_set_rate() failed for rate %lu\n", rate);
290	398	return ret;
291	399	}
	400	+ tup->configured_rate = clk_get_rate(tup->uart_clk);
292	401	divisor = 1;
	402	+ ret = tegra_check_rate_in_range(tup);
	403	+ if (ret < 0)
	404	+ return ret;
293	405	} else {
294	406	rate = clk_get_rate(tup->uart_clk);
295	407	divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
296	408	}
297	409
	410	+ spin_lock_irqsave(&tup->uport.lock, flags);
298	411	lcr = tup->lcr_shadow;
299	412	lcr \|= UART_LCR_DLAB;
300	413	tegra_uart_write(tup, lcr, UART_LCR);
..	..	@@ -307,6 +420,7 @@
307	420
308	421	/* Dummy read to ensure the write is posted */
309	422	tegra_uart_read(tup, UART_SCR);
	423	+ spin_unlock_irqrestore(&tup->uport.lock, flags);
310	424
311	425	tup->current_baud = baud;
312	426
..	..	@@ -325,24 +439,32 @@
325	439	/* Overrrun error */
326	440	flag = TTY_OVERRUN;
327	441	tup->uport.icount.overrun++;
328		- dev_err(tup->uport.dev, "Got overrun errors\n");
	442	+ dev_dbg(tup->uport.dev, "Got overrun errors\n");
329	443	} else if (lsr & UART_LSR_PE) {
330	444	/* Parity error */
331	445	flag = TTY_PARITY;
332	446	tup->uport.icount.parity++;
333		- dev_err(tup->uport.dev, "Got Parity errors\n");
	447	+ dev_dbg(tup->uport.dev, "Got Parity errors\n");
334	448	} else if (lsr & UART_LSR_FE) {
335	449	flag = TTY_FRAME;
336	450	tup->uport.icount.frame++;
337		- dev_err(tup->uport.dev, "Got frame errors\n");
	451	+ dev_dbg(tup->uport.dev, "Got frame errors\n");
338	452	} else if (lsr & UART_LSR_BI) {
339		- dev_err(tup->uport.dev, "Got Break\n");
340		- tup->uport.icount.brk++;
341		- /* If FIFO read error without any data, reset Rx FIFO */
	453	+ /*
	454	+ * Break error
	455	+ * If FIFO read error without any data, reset Rx FIFO
	456	+ */
342	457	if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
343	458	tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
	459	+ if (tup->uport.ignore_status_mask & UART_LSR_BI)
	460	+ return TTY_BREAK;
	461	+ flag = TTY_BREAK;
	462	+ tup->uport.icount.brk++;
	463	+ dev_dbg(tup->uport.dev, "Got Break\n");
344	464	}
	465	+ uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
345	466	}
	467	+
346	468	return flag;
347	469	}
348	470
..	..	@@ -398,7 +520,7 @@
398	520	count = tup->tx_bytes_requested - state.residue;
399	521	async_tx_ack(tup->tx_dma_desc);
400	522	spin_lock_irqsave(&tup->uport.lock, flags);
401		- xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
	523	+ uart_xmit_advance(&tup->uport, count);
402	524	tup->tx_in_progress = 0;
403	525	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
404	526	uart_write_wakeup(&tup->uport);
..	..	@@ -412,11 +534,12 @@
412	534	struct circ_buf *xmit = &tup->uport.state->xmit;
413	535	dma_addr_t tx_phys_addr;
414	536
415		- dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
416		- UART_XMIT_SIZE, DMA_TO_DEVICE);
417		-
418	537	tup->tx_bytes = count & ~(0xF);
419	538	tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
	539	+
	540	+ dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
	541	+ tup->tx_bytes, DMA_TO_DEVICE);
	542	+
420	543	tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
421	544	tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
422	545	DMA_PREP_INTERRUPT);
..	..	@@ -440,12 +563,15 @@
440	563	unsigned long count;
441	564	struct circ_buf *xmit = &tup->uport.state->xmit;
442	565
	566	+ if (!tup->current_baud)
	567	+ return;
	568	+
443	569	tail = (unsigned long)&xmit->buf[xmit->tail];
444	570	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
445	571	if (!count)
446	572	return;
447	573
448		- if (count < TEGRA_UART_MIN_DMA)
	574	+ if (tup->use_tx_pio \|\| count < TEGRA_UART_MIN_DMA)
449	575	tegra_uart_start_pio_tx(tup, count);
450	576	else if (BYTES_TO_ALIGN(tail) > 0)
451	577	tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
..	..	@@ -482,18 +608,18 @@
482	608	static void tegra_uart_stop_tx(struct uart_port *u)
483	609	{
484	610	struct tegra_uart_port *tup = to_tegra_uport(u);
485		- struct circ_buf *xmit = &tup->uport.state->xmit;
486	611	struct dma_tx_state state;
487	612	unsigned int count;
488	613
489	614	if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
490	615	return;
491	616
492		- dmaengine_terminate_all(tup->tx_dma_chan);
	617	+ dmaengine_pause(tup->tx_dma_chan);
493	618	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
	619	+ dmaengine_terminate_all(tup->tx_dma_chan);
494	620	count = tup->tx_bytes_requested - state.residue;
495	621	async_tx_ack(tup->tx_dma_desc);
496		- xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
	622	+ uart_xmit_advance(&tup->uport, count);
497	623	tup->tx_in_progress = 0;
498	624	}
499	625
..	..	@@ -509,7 +635,7 @@
509	635	}
510	636
511	637	static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
512		- struct tty_port *tty)
	638	+ struct tty_port *port)
513	639	{
514	640	do {
515	641	char flag = TTY_NORMAL;
..	..	@@ -521,16 +647,24 @@
521	647	break;
522	648
523	649	flag = tegra_uart_decode_rx_error(tup, lsr);
	650	+ if (flag != TTY_NORMAL)
	651	+ continue;
	652	+
524	653	ch = (unsigned char) tegra_uart_read(tup, UART_RX);
525	654	tup->uport.icount.rx++;
526	655
527		- if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
528		- tty_insert_flip_char(tty, ch, flag);
	656	+ if (uart_handle_sysrq_char(&tup->uport, ch))
	657	+ continue;
	658	+
	659	+ if (tup->uport.ignore_status_mask & UART_LSR_DR)
	660	+ continue;
	661	+
	662	+ tty_insert_flip_char(port, ch, flag);
529	663	} while (1);
530	664	}
531	665
532	666	static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
533		- struct tty_port *tty,
	667	+ struct tty_port *port,
534	668	unsigned int count)
535	669	{
536	670	int copied;
..	..	@@ -540,27 +674,38 @@
540	674	return;
541	675
542	676	tup->uport.icount.rx += count;
543		- if (!tty) {
544		- dev_err(tup->uport.dev, "No tty port\n");
	677	+
	678	+ if (tup->uport.ignore_status_mask & UART_LSR_DR)
545	679	return;
546		- }
	680	+
547	681	dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
548		- TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
549		- copied = tty_insert_flip_string(tty,
	682	+ count, DMA_FROM_DEVICE);
	683	+ copied = tty_insert_flip_string(port,
550	684	((unsigned char *)(tup->rx_dma_buf_virt)), count);
551	685	if (copied != count) {
552	686	WARN_ON(1);
553	687	dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
554	688	}
555	689	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
556		- TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
	690	+ count, DMA_TO_DEVICE);
	691	+}
	692	+
	693	+static void do_handle_rx_pio(struct tegra_uart_port *tup)
	694	+{
	695	+ struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
	696	+ struct tty_port *port = &tup->uport.state->port;
	697	+
	698	+ tegra_uart_handle_rx_pio(tup, port);
	699	+ if (tty) {
	700	+ tty_flip_buffer_push(port);
	701	+ tty_kref_put(tty);
	702	+ }
557	703	}
558	704
559	705	static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
560	706	unsigned int residue)
561	707	{
562	708	struct tty_port *port = &tup->uport.state->port;
563		- struct tty_struct *tty = tty_port_tty_get(port);
564	709	unsigned int count;
565	710
566	711	async_tx_ack(tup->rx_dma_desc);
..	..	@@ -569,11 +714,7 @@
569	714	/* If we are here, DMA is stopped */
570	715	tegra_uart_copy_rx_to_tty(tup, port, count);
571	716
572		- tegra_uart_handle_rx_pio(tup, port);
573		- if (tty) {
574		- tty_flip_buffer_push(port);
575		- tty_kref_put(tty);
576		- }
	717	+ do_handle_rx_pio(tup);
577	718	}
578	719
579	720	static void tegra_uart_rx_dma_complete(void *args)
..	..	@@ -597,6 +738,7 @@
597	738	if (tup->rts_active)
598	739	set_rts(tup, false);
599	740
	741	+ tup->rx_dma_active = false;
600	742	tegra_uart_rx_buffer_push(tup, 0);
601	743	tegra_uart_start_rx_dma(tup);
602	744
..	..	@@ -608,18 +750,30 @@
608	750	spin_unlock_irqrestore(&u->lock, flags);
609	751	}
610	752
611		-static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
	753	+static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
612	754	{
613	755	struct dma_tx_state state;
614	756
	757	+ if (!tup->rx_dma_active) {
	758	+ do_handle_rx_pio(tup);
	759	+ return;
	760	+ }
	761	+
	762	+ dmaengine_pause(tup->rx_dma_chan);
	763	+ dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
	764	+ dmaengine_terminate_all(tup->rx_dma_chan);
	765	+
	766	+ tegra_uart_rx_buffer_push(tup, state.residue);
	767	+ tup->rx_dma_active = false;
	768	+}
	769	+
	770	+static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
	771	+{
615	772	/* Deactivate flow control to stop sender */
616	773	if (tup->rts_active)
617	774	set_rts(tup, false);
618	775
619		- dmaengine_terminate_all(tup->rx_dma_chan);
620		- dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
621		- tegra_uart_rx_buffer_push(tup, state.residue);
622		- tegra_uart_start_rx_dma(tup);
	776	+ tegra_uart_terminate_rx_dma(tup);
623	777
624	778	if (tup->rts_active)
625	779	set_rts(tup, true);
..	..	@@ -629,6 +783,9 @@
629	783	{
630	784	unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
631	785
	786	+ if (tup->rx_dma_active)
	787	+ return 0;
	788	+
632	789	tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
633	790	tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
634	791	DMA_PREP_INTERRUPT);
..	..	@@ -637,10 +794,9 @@
637	794	return -EIO;
638	795	}
639	796
	797	+ tup->rx_dma_active = true;
640	798	tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
641	799	tup->rx_dma_desc->callback_param = tup;
642		- dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
643		- count, DMA_TO_DEVICE);
644	800	tup->rx_bytes_requested = count;
645	801	tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
646	802	dma_async_issue_pending(tup->rx_dma_chan);
..	..	@@ -674,6 +830,7 @@
674	830	struct uart_port *u = &tup->uport;
675	831	unsigned long iir;
676	832	unsigned long ier;
	833	+ bool is_rx_start = false;
677	834	bool is_rx_int = false;
678	835	unsigned long flags;
679	836
..	..	@@ -681,15 +838,17 @@
681	838	while (1) {
682	839	iir = tegra_uart_read(tup, UART_IIR);
683	840	if (iir & UART_IIR_NO_INT) {
684		- if (is_rx_int) {
	841	+ if (!tup->use_rx_pio && is_rx_int) {
685	842	tegra_uart_handle_rx_dma(tup);
686	843	if (tup->rx_in_progress) {
687	844	ier = tup->ier_shadow;
688	845	ier \|= (UART_IER_RLSI \| UART_IER_RTOIE \|
689		- TEGRA_UART_IER_EORD);
	846	+ TEGRA_UART_IER_EORD \| UART_IER_RDI);
690	847	tup->ier_shadow = ier;
691	848	tegra_uart_write(tup, ier, UART_IER);
692	849	}
	850	+ } else if (is_rx_start) {
	851	+ tegra_uart_start_rx_dma(tup);
693	852	}
694	853	spin_unlock_irqrestore(&u->lock, flags);
695	854	return IRQ_HANDLED;
..	..	@@ -708,17 +867,25 @@
708	867
709	868	case 4: /* End of data */
710	869	case 6: /* Rx timeout */
711		- case 2: /* Receive */
712		- if (!is_rx_int) {
713		- is_rx_int = true;
	870	+ if (!tup->use_rx_pio) {
	871	+ is_rx_int = tup->rx_in_progress;
714	872	/* Disable Rx interrupts */
715	873	ier = tup->ier_shadow;
716		- ier \|= UART_IER_RDI;
717		- tegra_uart_write(tup, ier, UART_IER);
718	874	ier &= ~(UART_IER_RDI \| UART_IER_RLSI \|
719	875	UART_IER_RTOIE \| TEGRA_UART_IER_EORD);
720	876	tup->ier_shadow = ier;
721	877	tegra_uart_write(tup, ier, UART_IER);
	878	+ break;
	879	+ }
	880	+ fallthrough;
	881	+ case 2: /* Receive */
	882	+ if (!tup->use_rx_pio) {
	883	+ is_rx_start = tup->rx_in_progress;
	884	+ tup->ier_shadow &= ~UART_IER_RDI;
	885	+ tegra_uart_write(tup, tup->ier_shadow,
	886	+ UART_IER);
	887	+ } else {
	888	+ do_handle_rx_pio(tup);
722	889	}
723	890	break;
724	891
..	..	@@ -737,7 +904,7 @@
737	904	static void tegra_uart_stop_rx(struct uart_port *u)
738	905	{
739	906	struct tegra_uart_port *tup = to_tegra_uport(u);
740		- struct dma_tx_state state;
	907	+ struct tty_port *port = &tup->uport.state->port;
741	908	unsigned long ier;
742	909
743	910	if (tup->rts_active)
..	..	@@ -746,7 +913,7 @@
746	913	if (!tup->rx_in_progress)
747	914	return;
748	915
749		- tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
	916	+ tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
750	917
751	918	ier = tup->ier_shadow;
752	919	ier &= ~(UART_IER_RDI \| UART_IER_RLSI \| UART_IER_RTOIE \|
..	..	@@ -754,9 +921,11 @@
754	921	tup->ier_shadow = ier;
755	922	tegra_uart_write(tup, ier, UART_IER);
756	923	tup->rx_in_progress = 0;
757		- dmaengine_terminate_all(tup->rx_dma_chan);
758		- dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
759		- tegra_uart_rx_buffer_push(tup, state.residue);
	924	+
	925	+ if (!tup->use_rx_pio)
	926	+ tegra_uart_terminate_rx_dma(tup);
	927	+ else
	928	+ tegra_uart_handle_rx_pio(tup, port);
760	929	}
761	930
762	931	static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
..	..	@@ -804,6 +973,14 @@
804	973	tup->current_baud = 0;
805	974	spin_unlock_irqrestore(&tup->uport.lock, flags);
806	975
	976	+ tup->rx_in_progress = 0;
	977	+ tup->tx_in_progress = 0;
	978	+
	979	+ if (!tup->use_rx_pio)
	980	+ tegra_uart_dma_channel_free(tup, true);
	981	+ if (!tup->use_tx_pio)
	982	+ tegra_uart_dma_channel_free(tup, false);
	983	+
807	984	clk_disable_unprepare(tup->uart_clk);
808	985	}
809	986
..	..	@@ -817,7 +994,11 @@
817	994	tup->ier_shadow = 0;
818	995	tup->current_baud = 0;
819	996
820		- clk_prepare_enable(tup->uart_clk);
	997	+ ret = clk_prepare_enable(tup->uart_clk);
	998	+ if (ret) {
	999	+ dev_err(tup->uport.dev, "could not enable clk\n");
	1000	+ return ret;
	1001	+ }
821	1002
822	1003	/* Reset the UART controller to clear all previous status.*/
823	1004	reset_control_assert(tup->rst);
..	..	@@ -846,34 +1027,55 @@
846	1027	* programmed in the DMA registers.
847	1028	*/
848	1029	tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
849		- tup->fcr_shadow \|= UART_FCR_R_TRIG_01;
	1030	+
	1031	+ if (tup->use_rx_pio) {
	1032	+ tup->fcr_shadow \|= UART_FCR_R_TRIG_11;
	1033	+ } else {
	1034	+ if (tup->cdata->max_dma_burst_bytes == 8)
	1035	+ tup->fcr_shadow \|= UART_FCR_R_TRIG_10;
	1036	+ else
	1037	+ tup->fcr_shadow \|= UART_FCR_R_TRIG_01;
	1038	+ }
	1039	+
850	1040	tup->fcr_shadow \|= TEGRA_UART_TX_TRIG_16B;
851	1041	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
852	1042
853	1043	/* Dummy read to ensure the write is posted */
854	1044	tegra_uart_read(tup, UART_SCR);
855	1045
856		- /*
857		- * For all tegra devices (up to t210), there is a hardware issue that
858		- * requires software to wait for 3 UART clock periods after enabling
859		- * the TX fifo, otherwise data could be lost.
860		- */
861		- tegra_uart_wait_cycle_time(tup, 3);
	1046	+ if (tup->cdata->fifo_mode_enable_status) {
	1047	+ ret = tegra_uart_wait_fifo_mode_enabled(tup);
	1048	+ if (ret < 0) {
	1049	+ dev_err(tup->uport.dev,
	1050	+ "Failed to enable FIFO mode: %d\n", ret);
	1051	+ return ret;
	1052	+ }
	1053	+ } else {
	1054	+ /*
	1055	+ * For all tegra devices (up to t210), there is a hardware
	1056	+ * issue that requires software to wait for 3 UART clock
	1057	+ * periods after enabling the TX fifo, otherwise data could
	1058	+ * be lost.
	1059	+ */
	1060	+ tegra_uart_wait_cycle_time(tup, 3);
	1061	+ }
862	1062
863	1063	/*
864	1064	* Initialize the UART with default configuration
865	1065	* (115200, N, 8, 1) so that the receive DMA buffer may be
866	1066	* enqueued
867	1067	*/
868		- tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
869		- tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
870		- tup->fcr_shadow \|= UART_FCR_DMA_SELECT;
871		- tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
872		-
873		- ret = tegra_uart_start_rx_dma(tup);
	1068	+ ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
874	1069	if (ret < 0) {
875		- dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
	1070	+ dev_err(tup->uport.dev, "Failed to set baud rate\n");
876	1071	return ret;
	1072	+ }
	1073	+ if (!tup->use_rx_pio) {
	1074	+ tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
	1075	+ tup->fcr_shadow \|= UART_FCR_DMA_SELECT;
	1076	+ tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
	1077	+ } else {
	1078	+ tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
877	1079	}
878	1080	tup->rx_in_progress = 1;
879	1081
..	..	@@ -881,13 +1083,9 @@
881	1083	* Enable IE_RXS for the receive status interrupts like line errros.
882	1084	* Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
883	1085	*
884		- * If using DMA mode, enable EORD instead of receive interrupt which
885		- * will interrupt after the UART is done with the receive instead of
886		- * the interrupt when the FIFO "threshold" is reached.
887		- *
888	1086	* EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
889	1087	* the DATA is sitting in the FIFO and couldn't be transferred to the
890		- * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
	1088	+ * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
891	1089	* triggered when there is a pause of the incomming data stream for 4
892	1090	* characters long.
893	1091	*
..	..	@@ -895,7 +1093,15 @@
895	1093	* both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
896	1094	* then the EORD.
897	1095	*/
898		- tup->ier_shadow = UART_IER_RLSI \| UART_IER_RTOIE \| TEGRA_UART_IER_EORD;
	1096	+ tup->ier_shadow = UART_IER_RLSI \| UART_IER_RTOIE \| UART_IER_RDI;
	1097	+
	1098	+ /*
	1099	+ * If using DMA mode, enable EORD interrupt to notify about RX
	1100	+ * completion.
	1101	+ */
	1102	+ if (!tup->use_rx_pio)
	1103	+ tup->ier_shadow \|= TEGRA_UART_IER_EORD;
	1104	+
899	1105	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
900	1106	return 0;
901	1107	}
..	..	@@ -931,8 +1137,7 @@
931	1137	int ret;
932	1138	struct dma_slave_config dma_sconfig;
933	1139
934		- dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
935		- dma_to_memory ? "rx" : "tx");
	1140	+ dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
936	1141	if (IS_ERR(dma_chan)) {
937	1142	ret = PTR_ERR(dma_chan);
938	1143	dev_err(tup->uport.dev,
..	..	@@ -950,9 +1155,12 @@
950	1155	dma_release_channel(dma_chan);
951	1156	return -ENOMEM;
952	1157	}
	1158	+ dma_sync_single_for_device(tup->uport.dev, dma_phys,
	1159	+ TEGRA_UART_RX_DMA_BUFFER_SIZE,
	1160	+ DMA_TO_DEVICE);
953	1161	dma_sconfig.src_addr = tup->uport.mapbase;
954	1162	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
955		- dma_sconfig.src_maxburst = 4;
	1163	+ dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
956	1164	tup->rx_dma_chan = dma_chan;
957	1165	tup->rx_dma_buf_virt = dma_buf;
958	1166	tup->rx_dma_buf_phys = dma_phys;
..	..	@@ -990,16 +1198,22 @@
990	1198	struct tegra_uart_port *tup = to_tegra_uport(u);
991	1199	int ret;
992	1200
993		- ret = tegra_uart_dma_channel_allocate(tup, false);
994		- if (ret < 0) {
995		- dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
996		- return ret;
	1201	+ if (!tup->use_tx_pio) {
	1202	+ ret = tegra_uart_dma_channel_allocate(tup, false);
	1203	+ if (ret < 0) {
	1204	+ dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
	1205	+ ret);
	1206	+ return ret;
	1207	+ }
997	1208	}
998	1209
999		- ret = tegra_uart_dma_channel_allocate(tup, true);
1000		- if (ret < 0) {
1001		- dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1002		- goto fail_rx_dma;
	1210	+ if (!tup->use_rx_pio) {
	1211	+ ret = tegra_uart_dma_channel_allocate(tup, true);
	1212	+ if (ret < 0) {
	1213	+ dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
	1214	+ ret);
	1215	+ goto fail_rx_dma;
	1216	+ }
1003	1217	}
1004	1218
1005	1219	ret = tegra_uart_hw_init(tup);
..	..	@@ -1017,9 +1231,11 @@
1017	1231	return 0;
1018	1232
1019	1233	fail_hw_init:
1020		- tegra_uart_dma_channel_free(tup, true);
	1234	+ if (!tup->use_rx_pio)
	1235	+ tegra_uart_dma_channel_free(tup, true);
1021	1236	fail_rx_dma:
1022		- tegra_uart_dma_channel_free(tup, false);
	1237	+ if (!tup->use_tx_pio)
	1238	+ tegra_uart_dma_channel_free(tup, false);
1023	1239	return ret;
1024	1240	}
1025	1241
..	..	@@ -1041,12 +1257,6 @@
1041	1257	struct tegra_uart_port *tup = to_tegra_uport(u);
1042	1258
1043	1259	tegra_uart_hw_deinit(tup);
1044		-
1045		- tup->rx_in_progress = 0;
1046		- tup->tx_in_progress = 0;
1047		-
1048		- tegra_uart_dma_channel_free(tup, true);
1049		- tegra_uart_dma_channel_free(tup, false);
1050	1260	free_irq(u->irq, tup);
1051	1261	}
1052	1262
..	..	@@ -1071,6 +1281,7 @@
1071	1281	struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1072	1282	unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1073	1283	int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
	1284	+ int ret;
1074	1285
1075	1286	max_divider *= 16;
1076	1287	spin_lock_irqsave(&u->lock, flags);
..	..	@@ -1079,7 +1290,7 @@
1079	1290	if (tup->rts_active)
1080	1291	set_rts(tup, false);
1081	1292
1082		- /* Clear all interrupts as configuration is going to be change */
	1293	+ /* Clear all interrupts as configuration is going to be changed */
1083	1294	tegra_uart_write(tup, tup->ier_shadow \| UART_IER_RDI, UART_IER);
1084	1295	tegra_uart_read(tup, UART_IER);
1085	1296	tegra_uart_write(tup, 0, UART_IER);
..	..	@@ -1143,7 +1354,11 @@
1143	1354	parent_clk_rate/max_divider,
1144	1355	parent_clk_rate/16);
1145	1356	spin_unlock_irqrestore(&u->lock, flags);
1146		- tegra_set_baudrate(tup, baud);
	1357	+ ret = tegra_set_baudrate(tup, baud);
	1358	+ if (ret < 0) {
	1359	+ dev_err(tup->uport.dev, "Failed to set baud rate\n");
	1360	+ return;
	1361	+ }
1147	1362	if (tty_termios_baud_rate(termios))
1148	1363	tty_termios_encode_baud_rate(termios, baud, baud);
1149	1364	spin_lock_irqsave(&u->lock, flags);
..	..	@@ -1165,12 +1380,19 @@
1165	1380	/* update the port timeout based on new settings */
1166	1381	uart_update_timeout(u, termios->c_cflag, baud);
1167	1382
1168		- /* Make sure all write has completed */
	1383	+ /* Make sure all writes have completed */
1169	1384	tegra_uart_read(tup, UART_IER);
1170	1385
1171		- /* Reenable interrupt */
	1386	+ /* Re-enable interrupt */
1172	1387	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1173	1388	tegra_uart_read(tup, UART_IER);
	1389	+
	1390	+ tup->uport.ignore_status_mask = 0;
	1391	+ /* Ignore all characters if CREAD is not set */
	1392	+ if ((termios->c_cflag & CREAD) == 0)
	1393	+ tup->uport.ignore_status_mask \|= UART_LSR_DR;
	1394	+ if (termios->c_iflag & IGNBRK)
	1395	+ tup->uport.ignore_status_mask \|= UART_LSR_BI;
1174	1396
1175	1397	spin_unlock_irqrestore(&u->lock, flags);
1176	1398	}
..	..	@@ -1211,6 +1433,11 @@
1211	1433	{
1212	1434	struct device_node *np = pdev->dev.of_node;
1213	1435	int port;
	1436	+ int ret;
	1437	+ int index;
	1438	+ u32 pval;
	1439	+ int count;
	1440	+ int n_entries;
1214	1441
1215	1442	port = of_alias_get_id(np, "serial");
1216	1443	if (port < 0) {
..	..	@@ -1221,6 +1448,54 @@
1221	1448
1222	1449	tup->enable_modem_interrupt = of_property_read_bool(np,
1223	1450	"nvidia,enable-modem-interrupt");
	1451	+
	1452	+ index = of_property_match_string(np, "dma-names", "rx");
	1453	+ if (index < 0) {
	1454	+ tup->use_rx_pio = true;
	1455	+ dev_info(&pdev->dev, "RX in PIO mode\n");
	1456	+ }
	1457	+ index = of_property_match_string(np, "dma-names", "tx");
	1458	+ if (index < 0) {
	1459	+ tup->use_tx_pio = true;
	1460	+ dev_info(&pdev->dev, "TX in PIO mode\n");
	1461	+ }
	1462	+
	1463	+ n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
	1464	+ if (n_entries > 0) {
	1465	+ tup->n_adjustable_baud_rates = n_entries / 3;
	1466	+ tup->baud_tolerance =
	1467	+ devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
	1468	+ sizeof(*tup->baud_tolerance), GFP_KERNEL);
	1469	+ if (!tup->baud_tolerance)
	1470	+ return -ENOMEM;
	1471	+ for (count = 0, index = 0; count < n_entries; count += 3,
	1472	+ index++) {
	1473	+ ret =
	1474	+ of_property_read_u32_index(np,
	1475	+ "nvidia,adjust-baud-rates",
	1476	+ count, &pval);
	1477	+ if (!ret)
	1478	+ tup->baud_tolerance[index].lower_range_baud =
	1479	+ pval;
	1480	+ ret =
	1481	+ of_property_read_u32_index(np,
	1482	+ "nvidia,adjust-baud-rates",
	1483	+ count + 1, &pval);
	1484	+ if (!ret)
	1485	+ tup->baud_tolerance[index].upper_range_baud =
	1486	+ pval;
	1487	+ ret =
	1488	+ of_property_read_u32_index(np,
	1489	+ "nvidia,adjust-baud-rates",
	1490	+ count + 2, &pval);
	1491	+ if (!ret)
	1492	+ tup->baud_tolerance[index].tolerance =
	1493	+ (s32)pval;
	1494	+ }
	1495	+ } else {
	1496	+ tup->n_adjustable_baud_rates = 0;
	1497	+ }
	1498	+
1224	1499	return 0;
1225	1500	}
1226	1501
..	..	@@ -1228,12 +1503,44 @@
1228	1503	.tx_fifo_full_status = false,
1229	1504	.allow_txfifo_reset_fifo_mode = true,
1230	1505	.support_clk_src_div = false,
	1506	+ .fifo_mode_enable_status = false,
	1507	+ .uart_max_port = 5,
	1508	+ .max_dma_burst_bytes = 4,
	1509	+ .error_tolerance_low_range = -4,
	1510	+ .error_tolerance_high_range = 4,
1231	1511	};
1232	1512
1233	1513	static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1234	1514	.tx_fifo_full_status = true,
1235	1515	.allow_txfifo_reset_fifo_mode = false,
1236	1516	.support_clk_src_div = true,
	1517	+ .fifo_mode_enable_status = false,
	1518	+ .uart_max_port = 5,
	1519	+ .max_dma_burst_bytes = 4,
	1520	+ .error_tolerance_low_range = -4,
	1521	+ .error_tolerance_high_range = 4,
	1522	+};
	1523	+
	1524	+static struct tegra_uart_chip_data tegra186_uart_chip_data = {
	1525	+ .tx_fifo_full_status = true,
	1526	+ .allow_txfifo_reset_fifo_mode = false,
	1527	+ .support_clk_src_div = true,
	1528	+ .fifo_mode_enable_status = true,
	1529	+ .uart_max_port = 8,
	1530	+ .max_dma_burst_bytes = 8,
	1531	+ .error_tolerance_low_range = 0,
	1532	+ .error_tolerance_high_range = 4,
	1533	+};
	1534	+
	1535	+static struct tegra_uart_chip_data tegra194_uart_chip_data = {
	1536	+ .tx_fifo_full_status = true,
	1537	+ .allow_txfifo_reset_fifo_mode = false,
	1538	+ .support_clk_src_div = true,
	1539	+ .fifo_mode_enable_status = true,
	1540	+ .uart_max_port = 8,
	1541	+ .max_dma_burst_bytes = 8,
	1542	+ .error_tolerance_low_range = -2,
	1543	+ .error_tolerance_high_range = 2,
1237	1544	};
1238	1545
1239	1546	static const struct of_device_id tegra_uart_of_match[] = {
..	..	@@ -1243,6 +1550,12 @@
1243	1550	}, {
1244	1551	.compatible = "nvidia,tegra20-hsuart",
1245	1552	.data = &tegra20_uart_chip_data,
	1553	+ }, {
	1554	+ .compatible = "nvidia,tegra186-hsuart",
	1555	+ .data = &tegra186_uart_chip_data,
	1556	+ }, {
	1557	+ .compatible = "nvidia,tegra194-hsuart",
	1558	+ .data = &tegra194_uart_chip_data,
1246	1559	}, {
1247	1560	},
1248	1561	};
..	..	@@ -1307,10 +1620,8 @@
1307	1620
1308	1621	u->iotype = UPIO_MEM32;
1309	1622	ret = platform_get_irq(pdev, 0);
1310		- if (ret < 0) {
1311		- dev_err(&pdev->dev, "Couldn't get IRQ\n");
	1623	+ if (ret < 0)
1312	1624	return ret;
1313		- }
1314	1625	u->irq = ret;
1315	1626	u->regshift = 2;
1316	1627	ret = uart_add_one_port(&tegra_uart_driver, u);
..	..	@@ -1365,11 +1676,22 @@
1365	1676	static int __init tegra_uart_init(void)
1366	1677	{
1367	1678	int ret;
	1679	+ struct device_node *node;
	1680	+ const struct of_device_id *match = NULL;
	1681	+ const struct tegra_uart_chip_data *cdata = NULL;
	1682	+
	1683	+ node = of_find_matching_node(NULL, tegra_uart_of_match);
	1684	+ if (node)
	1685	+ match = of_match_node(tegra_uart_of_match, node);
	1686	+ if (match)
	1687	+ cdata = match->data;
	1688	+ if (cdata)
	1689	+ tegra_uart_driver.nr = cdata->uart_max_port;
1368	1690
1369	1691	ret = uart_register_driver(&tegra_uart_driver);
1370	1692	if (ret < 0) {
1371	1693	pr_err("Could not register %s driver\n",
1372		- tegra_uart_driver.driver_name);
	1694	+ tegra_uart_driver.driver_name);
1373	1695	return ret;
1374	1696	}
1375	1697