hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/tty/serial/serial-tegra.c
....@@ -614,8 +614,9 @@
614614 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
615615 return;
616616
617
- dmaengine_terminate_all(tup->tx_dma_chan);
617
+ dmaengine_pause(tup->tx_dma_chan);
618618 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
619
+ dmaengine_terminate_all(tup->tx_dma_chan);
619620 count = tup->tx_bytes_requested - state.residue;
620621 async_tx_ack(tup->tx_dma_desc);
621622 uart_xmit_advance(&tup->uport, count);
....@@ -758,8 +759,9 @@
758759 return;
759760 }
760761
761
- dmaengine_terminate_all(tup->rx_dma_chan);
762
+ dmaengine_pause(tup->rx_dma_chan);
762763 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
764
+ dmaengine_terminate_all(tup->rx_dma_chan);
763765
764766 tegra_uart_rx_buffer_push(tup, state.residue);
765767 tup->rx_dma_active = false;
....@@ -992,7 +994,11 @@
992994 tup->ier_shadow = 0;
993995 tup->current_baud = 0;
994996
995
- clk_prepare_enable(tup->uart_clk);
997
+ ret = clk_prepare_enable(tup->uart_clk);
998
+ if (ret) {
999
+ dev_err(tup->uport.dev, "could not enable clk\n");
1000
+ return ret;
1001
+ }
9961002
9971003 /* Reset the UART controller to clear all previous status.*/
9981004 reset_control_assert(tup->rst);