.. | .. |
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614 | 614 | if (tup->tx_in_progress != TEGRA_UART_TX_DMA) |
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615 | 615 | return; |
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616 | 616 | |
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617 | | - dmaengine_terminate_all(tup->tx_dma_chan); |
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| 617 | + dmaengine_pause(tup->tx_dma_chan); |
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618 | 618 | dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); |
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| 619 | + dmaengine_terminate_all(tup->tx_dma_chan); |
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619 | 620 | count = tup->tx_bytes_requested - state.residue; |
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620 | 621 | async_tx_ack(tup->tx_dma_desc); |
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621 | 622 | uart_xmit_advance(&tup->uport, count); |
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.. | .. |
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758 | 759 | return; |
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759 | 760 | } |
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760 | 761 | |
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761 | | - dmaengine_terminate_all(tup->rx_dma_chan); |
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| 762 | + dmaengine_pause(tup->rx_dma_chan); |
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762 | 763 | dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); |
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| 764 | + dmaengine_terminate_all(tup->rx_dma_chan); |
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763 | 765 | |
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764 | 766 | tegra_uart_rx_buffer_push(tup, state.residue); |
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765 | 767 | tup->rx_dma_active = false; |
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.. | .. |
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992 | 994 | tup->ier_shadow = 0; |
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993 | 995 | tup->current_baud = 0; |
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994 | 996 | |
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995 | | - clk_prepare_enable(tup->uart_clk); |
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| 997 | + ret = clk_prepare_enable(tup->uart_clk); |
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| 998 | + if (ret) { |
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| 999 | + dev_err(tup->uport.dev, "could not enable clk\n"); |
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| 1000 | + return ret; |
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| 1001 | + } |
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996 | 1002 | |
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997 | 1003 | /* Reset the UART controller to clear all previous status.*/ |
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998 | 1004 | reset_control_assert(tup->rst); |
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