forked from ~ljy/RK356X_SDK_RELEASE

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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/tty/serial/sc16is7xx.c
....@@ -1170,9 +1170,18 @@
11701170 		state |= BIT(offset);
11711171 	else
11721172 		state &= ~BIT(offset);
1173
-	sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1173
+
1174
+	/*
1175
+	 * If we write IOSTATE first, and then IODIR, the output value is not
1176
+	 * transferred to the corresponding I/O pin.
1177
+	 * The datasheet states that each register bit will be transferred to
1178
+	 * the corresponding I/O pin programmed as output when writing to
1179
+	 * IOSTATE. Therefore, configure direction first with IODIR, and then
1180
+	 * set value after with IOSTATE.
1181
+	 */
11741182 	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
11751183 			      BIT(offset));
1184
+	sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
11761185 
11771186 	return 0;
11781187 }
....@@ -1243,25 +1252,6 @@
12431252 	}
12441253 	sched_set_fifo(s->kworker_task);
12451254 
1246
-#ifdef CONFIG_GPIOLIB
1247
-	if (devtype->nr_gpio) {
1248
-		/* Setup GPIO cotroller */
1249
-		s->gpio.owner		 = THIS_MODULE;
1250
-		s->gpio.parent		 = dev;
1251
-		s->gpio.label		 = dev_name(dev);
1252
-		s->gpio.direction_input	 = sc16is7xx_gpio_direction_input;
1253
-		s->gpio.get		 = sc16is7xx_gpio_get;
1254
-		s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1255
-		s->gpio.set		 = sc16is7xx_gpio_set;
1256
-		s->gpio.base		 = -1;
1257
-		s->gpio.ngpio		 = devtype->nr_gpio;
1258
-		s->gpio.can_sleep	 = 1;
1259
-		ret = gpiochip_add_data(&s->gpio, s);
1260
-		if (ret)
1261
-			goto out_thread;
1262
-	}
1263
-#endif
1264
-
12651255 	/* reset device, purging any pending irq / data */
12661256 	regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
12671257 			SC16IS7XX_IOCONTROL_SRESET_BIT);
....@@ -1275,6 +1265,12 @@
12751265 		s->p[i].port.fifosize	= SC16IS7XX_FIFO_SIZE;
12761266 		s->p[i].port.flags	= UPF_FIXED_TYPE | UPF_LOW_LATENCY;
12771267 		s->p[i].port.iobase	= i;
1268
+		/*
1269
+		 * Use all ones as membase to make sure uart_configure_port() in
1270
+		 * serial_core.c does not abort for SPI/I2C devices where the
1271
+		 * membase address is not applicable.
1272
+		 */
1273
+		s->p[i].port.membase	= (void __iomem *)~0;
12781274 		s->p[i].port.iotype	= UPIO_PORT;
12791275 		s->p[i].port.uartclk	= freq;
12801276 		s->p[i].port.rs485_config = sc16is7xx_config_rs485;
....@@ -1327,6 +1323,25 @@
13271323 				s->p[u].irda_mode = true;
13281324 	}
13291325 
1326
+#ifdef CONFIG_GPIOLIB
1327
+	if (devtype->nr_gpio) {
1328
+		/* Setup GPIO cotroller */
1329
+		s->gpio.owner		 = THIS_MODULE;
1330
+		s->gpio.parent		 = dev;
1331
+		s->gpio.label		 = dev_name(dev);
1332
+		s->gpio.direction_input	 = sc16is7xx_gpio_direction_input;
1333
+		s->gpio.get		 = sc16is7xx_gpio_get;
1334
+		s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1335
+		s->gpio.set		 = sc16is7xx_gpio_set;
1336
+		s->gpio.base		 = -1;
1337
+		s->gpio.ngpio		 = devtype->nr_gpio;
1338
+		s->gpio.can_sleep	 = 1;
1339
+		ret = gpiochip_add_data(&s->gpio, s);
1340
+		if (ret)
1341
+			goto out_thread;
1342
+	}
1343
+#endif
1344
+
13301345 	/*
13311346 	 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
13321347 	 * If that succeeds, we can allow sharing the interrupt as well.
....@@ -1346,18 +1361,19 @@
13461361 	if (!ret)
13471362 		return 0;
13481363 
1349
-out_ports:
1350
-	for (i--; i >= 0; i--) {
1351
-		uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1352
-		clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1353
-	}
1354
-
13551364 #ifdef CONFIG_GPIOLIB
13561365 	if (devtype->nr_gpio)
13571366 		gpiochip_remove(&s->gpio);
13581367 
13591368 out_thread:
13601369 #endif
1370
+
1371
+out_ports:
1372
+	for (i--; i >= 0; i--) {
1373
+		uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1374
+		clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1375
+	}
1376
+
13611377 	kthread_stop(s->kworker_task);
13621378 
13631379 out_clk: