update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/soc/rockchip/rockchip_debug.c
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@@ -59,6 +59,10 @@
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 #include <linux/irq.h>
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 #include <linux/delay.h>
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+#if IS_ENABLED(CONFIG_ROCKCHIP_MINIDUMP)
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+#include <soc/rockchip/rk_minidump.h>
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+#endif
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+
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 #include "fiq_debugger/fiq_debugger_priv.h"
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 #include "rockchip_debug.h"
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@@ -85,6 +89,22 @@
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 extern struct atomic_notifier_head hardlock_notifier_list;
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 extern struct atomic_notifier_head rcu_stall_notifier_list;
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+static inline void rockchip_debug_serror_enable(void)
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+{
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+#ifdef CONFIG_ARM64
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+	/* enable SError */
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+	asm volatile("msr	daifclr, #0x4");
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+#endif
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+}
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+
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+static inline void rockchip_debug_serror_disable(void)
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+{
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+#ifdef CONFIG_ARM64
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+	/* disable SError */
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+	asm volatile("msr	daifset, #0x4");
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+#endif
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+}
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+
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 #if IS_ENABLED(CONFIG_FIQ_DEBUGGER)
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 static int rockchip_debug_dump_edpcsr(struct fiq_debugger_output *output)
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 {
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@@ -96,10 +116,7 @@
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 	void __iomem *base;
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 	u32 pu = 0, online = 0;
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-#ifdef CONFIG_ARM64
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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-#endif
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+	rockchip_debug_serror_disable();
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 	while (rockchip_cpu_debug[i]) {
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 		online = cpu_online(i);
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@@ -154,11 +171,7 @@
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 		printed = 0;
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 	}
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-#ifdef CONFIG_ARM64
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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-#endif
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-
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+	rockchip_debug_serror_enable();
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 	return NOTIFY_OK;
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 }
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@@ -173,8 +186,7 @@
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 	void __iomem *base;
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 	u32 pu = 0, online = 0;
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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+	rockchip_debug_serror_disable();
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 	while (rockchip_cs_pmu[i]) {
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 		online = cpu_online(i);
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@@ -233,8 +245,7 @@
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 		prev_pc = NULL;
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 		printed = 0;
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 	}
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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+	rockchip_debug_serror_enable();
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 	return NOTIFY_OK;
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 }
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 #else
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@@ -243,7 +254,6 @@
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 	return 0;
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 }
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 #endif
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-
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 int rockchip_debug_dump_pcsr(struct fiq_debugger_output *output)
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 {
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@@ -267,10 +277,7 @@
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 	void __iomem *base;
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 	u32 pu = 0;
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-#ifdef CONFIG_ARM64
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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-#endif
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+	rockchip_debug_serror_disable();
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 	/*
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 	 * The panic handler will try to shut down the other CPUs.
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@@ -324,11 +331,6 @@
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 		printed = 0;
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 	}
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-#ifdef CONFIG_ARM64
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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-#endif
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-
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 	return NOTIFY_OK;
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 }
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@@ -344,8 +346,7 @@
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 	void __iomem *base;
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 	u32 pu = 0;
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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+	rockchip_debug_serror_disable();
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 	/*
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 	 * The panic handler will try to shut down the other CPUs.
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@@ -403,8 +404,7 @@
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 		prev_pc = NULL;
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 		printed = 0;
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 	}
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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+
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 	return NOTIFY_OK;
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 }
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 #else
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@@ -508,8 +508,73 @@
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 	rockchip_panic_notify_dump_irqs();
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 	return NOTIFY_OK;
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 }
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+
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+static int rockchip_hardlock_notify(struct notifier_block *nb,
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+				    unsigned long event, void *p)
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+{
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+	u64 pmpcsr;
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+	int el;
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+	u32 pu = 0;
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+	void *pc = NULL;
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+	void __iomem *base;
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+	unsigned long edpcsr;
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+	unsigned long cpu = event;
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+
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+	rockchip_debug_serror_disable();
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+
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+	pu = (u32)readl(rockchip_cpu_debug[cpu] + EDPRSR) & EDPRSR_PU;
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+	if (pu != EDPRSR_PU) {
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+		pr_err("CPU%ld power down\n", cpu);
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+		return NOTIFY_OK;
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+	}
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+
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+	if (edpcsr_present) {
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+		base = rockchip_cpu_debug[cpu];
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+		/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
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+		writel(EDLAR_UNLOCK, base + EDLAR);
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+		if (sizeof(edpcsr) == 8)
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+			edpcsr = ((u64)readl(base + EDPCSR_LO)) |
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+				 ((u64)readl(base + EDPCSR_HI) << 32);
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+		else
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+			edpcsr = (u32)readl(base + EDPCSR_LO);
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+
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+		/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
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+		pc = (void *)(edpcsr & ~1);
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+	} else {
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+		base = rockchip_cs_pmu[cpu];
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+		pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
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+			 ((u64)readl(base + PMPCSR_HI) << 32);
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+		el = (pmpcsr >> 61) & 0x3;
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+		if (el == 2)
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+			pmpcsr |= 0xff00000000000000;
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+		else
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+			pmpcsr &= 0x0fffffffffffffff;
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+		/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
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+		pc = (void *)(pmpcsr & ~1);
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+	}
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+
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+	rockchip_debug_serror_enable();
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+
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+#if IS_ENABLED(CONFIG_ROCKCHIP_MINIDUMP)
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+	rk_minidump_hardlock_notify(nb, event, pc);
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+#endif
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+
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+#if !IS_ENABLED(CONFIG_BOOTPARAM_HARDLOCKUP_PANIC)
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+	rockchip_panic_notify(nb, event, p);
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+#endif
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+	return NOTIFY_OK;
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+}
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+
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 static struct notifier_block rockchip_panic_nb = {
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 	.notifier_call = rockchip_panic_notify,
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+};
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+
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+static struct notifier_block rockchip_rcu_stall_nb = {
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+	.notifier_call = rockchip_panic_notify,
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+};
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+
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+static struct notifier_block rockchip_hardlock_nb = {
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+	.notifier_call = rockchip_hardlock_notify,
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 };
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 static const struct of_device_id rockchip_debug_dt_match[] __initconst = {
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@@ -527,7 +592,6 @@
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 	},
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 	{ /* sentinel */ },
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 };
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-
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 static int __init rockchip_debug_init(void)
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 {
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@@ -575,10 +639,10 @@
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 	if (IS_ENABLED(CONFIG_NO_GKI)) {
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 		if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
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 			atomic_notifier_chain_register(&hardlock_notifier_list,
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-						       &rockchip_panic_nb);
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+						       &rockchip_hardlock_nb);
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 		atomic_notifier_chain_register(&rcu_stall_notifier_list,
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-					       &rockchip_panic_nb);
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+					       &rockchip_rcu_stall_nb);
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 	}
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 	return 0;
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@@ -594,10 +658,10 @@
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 	if (IS_ENABLED(CONFIG_NO_GKI)) {
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 		if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
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 			atomic_notifier_chain_unregister(&hardlock_notifier_list,
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-							 &rockchip_panic_nb);
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+							 &rockchip_hardlock_nb);
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 		atomic_notifier_chain_unregister(&rcu_stall_notifier_list,
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-						 &rockchip_panic_nb);
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+						 &rockchip_rcu_stall_nb);
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 	}
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 	while (rockchip_cpu_debug[i])