update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/soc/fsl/qe/ucc.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * arch/powerpc/sysdev/qe_lib/ucc.c
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  *
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@@ -7,11 +8,6 @@
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  *
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  * Authors: 	Shlomi Gridish <gridish@freescale.com>
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  * 		Li Yang <leoli@freescale.com>
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/kernel.h>
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 #include <linux/errno.h>
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@@ -19,7 +15,6 @@
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 #include <linux/spinlock.h>
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 #include <linux/export.h>
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-#include <asm/irq.h>
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 #include <asm/io.h>
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 #include <soc/fsl/qe/immap_qe.h>
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 #include <soc/fsl/qe/qe.h>
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@@ -39,8 +34,8 @@
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 		return -EINVAL;
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 	spin_lock_irqsave(&cmxgcr_lock, flags);
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-	clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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-		ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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+	qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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+			   ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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 	spin_unlock_irqrestore(&cmxgcr_lock, flags);
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 	return 0;
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@@ -84,8 +79,8 @@
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 		return -EINVAL;
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 	}
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-	clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
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-		UCC_GUEMR_SET_RESERVED3 | speed);
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+	qe_clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
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+			UCC_GUEMR_SET_RESERVED3 | speed);
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 	return 0;
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 }
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@@ -113,9 +108,9 @@
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 	get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
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 	if (set)
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-		setbits32(cmxucr, mask << shift);
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+		qe_setbits_be32(cmxucr, mask << shift);
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 	else
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-		clrbits32(cmxucr, mask << shift);
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+		qe_clrbits_be32(cmxucr, mask << shift);
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 	return 0;
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 }
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@@ -211,8 +206,8 @@
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 	if (mode == COMM_DIR_RX)
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 		shift += 4;
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-	clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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-		clock_bits << shift);
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+	qe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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+			   clock_bits << shift);
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 	return 0;
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 }
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@@ -524,11 +519,11 @@
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 	int clock_bits;
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 	u32 shift;
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 	struct qe_mux __iomem *qe_mux_reg;
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-	 __be32 __iomem *cmxs1cr;
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+	__be32 __iomem *cmxs1cr;
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 	qe_mux_reg = &qe_immr->qmx;
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525
 
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-	if (tdm_num > 7 || tdm_num < 0)
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+	if (tdm_num > 7)
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 		return -EINVAL;
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 	/* The communications direction must be RX or TX */
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@@ -544,8 +539,8 @@
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 	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :
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 				  &qe_mux_reg->cmxsi1cr_h;
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-	qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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-			clock_bits << shift);
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+	qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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+			   clock_bits << shift);
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 	return 0;
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 }
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@@ -637,7 +632,7 @@
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 {
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 	int source;
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 	u32 shift;
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-	struct qe_mux *qe_mux_reg;
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+	struct qe_mux __iomem *qe_mux_reg;
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 	qe_mux_reg = &qe_immr->qmx;
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@@ -654,9 +649,9 @@
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 	shift = ucc_get_tdm_sync_shift(mode, tdm_num);
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-	qe_clrsetbits32(&qe_mux_reg->cmxsi1syr,
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-			QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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-			source << shift);
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+	qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,
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+			   QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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+			   source << shift);
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 	return 0;
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 }