update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/scsi/qla4xxx/ql4_83xx.c
..
..
@@ -1,8 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * QLogic iSCSI HBA Driver
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  * Copyright (c)   2003-2013 QLogic Corporation
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- *
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- * See LICENSE.qla4xxx for copyright and licensing details.
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  */
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 #include <linux/ratelimit.h>
..
..
@@ -1406,16 +1405,16 @@
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 static void qla4_83xx_dump_pause_control_regs(struct scsi_qla_host *ha)
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 {
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 	u32 val = 0, val1 = 0;
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-	int i, status = QLA_SUCCESS;
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+	int i;
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-	status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val);
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+	qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val);
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 	DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val));
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 	/* Port 0 Rx Buffer Pause Threshold Registers. */
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 		"Port 0 Rx Buffer Pause Threshold Registers[TC7..TC0]:"));
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 	for (i = 0; i < 8; i++) {
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-		status = qla4_83xx_rd_reg_indirect(ha,
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+		qla4_83xx_rd_reg_indirect(ha,
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 				QLA83XX_PORT0_RXB_PAUSE_THRS + (i * 0x4), &val);
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 		DEBUG2(pr_info("0x%x ", val));
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 	}
..
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@@ -1426,7 +1425,7 @@
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 		"Port 1 Rx Buffer Pause Threshold Registers[TC7..TC0]:"));
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 	for (i = 0; i < 8; i++) {
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-		status = qla4_83xx_rd_reg_indirect(ha,
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+		qla4_83xx_rd_reg_indirect(ha,
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 				QLA83XX_PORT1_RXB_PAUSE_THRS + (i * 0x4), &val);
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 		DEBUG2(pr_info("0x%x  ", val));
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 	}
..
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@@ -1437,7 +1436,7 @@
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 		"Port 0 RxB Traffic Class Max Cell Registers[3..0]:"));
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 	for (i = 0; i < 4; i++) {
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-		status = qla4_83xx_rd_reg_indirect(ha,
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+		qla4_83xx_rd_reg_indirect(ha,
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 			       QLA83XX_PORT0_RXB_TC_MAX_CELL + (i * 0x4), &val);
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 		DEBUG2(pr_info("0x%x  ", val));
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 	}
..
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@@ -1448,7 +1447,7 @@
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 		"Port 1 RxB Traffic Class Max Cell Registers[3..0]:"));
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 	for (i = 0; i < 4; i++) {
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-		status = qla4_83xx_rd_reg_indirect(ha,
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+		qla4_83xx_rd_reg_indirect(ha,
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 			       QLA83XX_PORT1_RXB_TC_MAX_CELL + (i * 0x4), &val);
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 		DEBUG2(pr_info("0x%x  ", val));
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 	}
..
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@@ -1459,15 +1458,11 @@
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 			  "Port 0 RxB Rx Traffic Class Stats [TC7..TC0]"));
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 	for (i = 7; i >= 0; i--) {
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-		status = qla4_83xx_rd_reg_indirect(ha,
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-						   QLA83XX_PORT0_RXB_TC_STATS,
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-						   &val);
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+		qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val);
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 		val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
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 		qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS,
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 					  (val | (i << 29)));
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-		status = qla4_83xx_rd_reg_indirect(ha,
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-						   QLA83XX_PORT0_RXB_TC_STATS,
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-						   &val);
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+		qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val);
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 		DEBUG2(pr_info("0x%x  ", val));
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 	}
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..
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@@ -1477,24 +1472,18 @@
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 			  "Port 1 RxB Rx Traffic Class Stats [TC7..TC0]"));
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 	for (i = 7; i >= 0; i--) {
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-		status = qla4_83xx_rd_reg_indirect(ha,
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-						   QLA83XX_PORT1_RXB_TC_STATS,
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-						   &val);
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+		qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val);
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 		val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
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 		qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS,
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 					  (val | (i << 29)));
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-		status = qla4_83xx_rd_reg_indirect(ha,
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-						   QLA83XX_PORT1_RXB_TC_STATS,
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-						   &val);
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+		qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val);
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 		DEBUG2(pr_info("0x%x  ", val));
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 	}
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 	DEBUG2(pr_info("\n"));
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-	status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS,
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-					   &val);
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-	status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS,
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-					   &val1);
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+	qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS, &val);
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+	qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS, &val1);
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 	DEBUG2(ql4_printk(KERN_INFO, ha,
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 			  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",