~hc/RK356X_SDK_RELEASE.git

..	..	@@ -20,10 +20,10 @@
20	20	#include <linux/platform_device.h>
21	21	#include <linux/io.h>
22	22	#include <linux/bitops.h>
23		-#include <linux/gpio.h>
	23	+#include <linux/gpio/driver.h>
24	24	#include <linux/of_address.h>
25		-#include <linux/of_irq.h>
26	25	#include <linux/of_device.h>
	26	+#include <linux/of_irq.h>
27	27	#include <linux/pinctrl/machine.h>
28	28	#include <linux/pinctrl/pinconf.h>
29	29	#include <linux/pinctrl/pinctrl.h>
..	..	@@ -40,7 +40,7 @@
40	40	#include "pinconf.h"
41	41	#include "pinctrl-rockchip.h"
42	42
43		-/**
	43	+/*
44	44	* Generate a bitmask for setting a value (v) with a write mask bit in hiword
45	45	* register 31:16 area.
46	46	*/
..	..	@@ -117,6 +117,25 @@
117	117	{ .drv_type = type2, .offset = -1 }, \
118	118	{ .drv_type = type3, .offset = -1 }, \
119	119	}, \
	120	+ }
	121	+
	122	+#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
	123	+ iom2, iom3, pull0, pull1, \
	124	+ pull2, pull3) \
	125	+ { \
	126	+ .bank_num = id, \
	127	+ .nr_pins = pins, \
	128	+ .name = label, \
	129	+ .iomux = { \
	130	+ { .type = iom0, .offset = -1 }, \
	131	+ { .type = iom1, .offset = -1 }, \
	132	+ { .type = iom2, .offset = -1 }, \
	133	+ { .type = iom3, .offset = -1 }, \
	134	+ }, \
	135	+ .pull_type[0] = pull0, \
	136	+ .pull_type[1] = pull1, \
	137	+ .pull_type[2] = pull2, \
	138	+ .pull_type[3] = pull3, \
120	139	}
121	140
122	141	#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
..	..	@@ -204,7 +223,7 @@
204	223	.route_location = FLAG, \
205	224	}
206	225
207		-#define PX30S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
	226	+#define S_PIN_BANK_FLAGS(ID, PIN, LABEL, MTYPE, DTYPE) \
208	227	PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(ID, PIN, LABEL, \
209	228	MTYPE, MTYPE, MTYPE, MTYPE, \
210	229	DTYPE, DTYPE, DTYPE, DTYPE, \
..	..	@@ -218,6 +237,12 @@
218	237
219	238	#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
220	239	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
	240	+
	241	+#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
	242	+ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
	243	+
	244	+static struct pinctrl_dev *g_pctldev;
	245	+static DEFINE_MUTEX(iomux_lock);
221	246
222	247	static struct regmap_config rockchip_regmap_config = {
223	248	.reg_bits = 32,
..	..	@@ -309,6 +334,7 @@
309	334	{
310	335	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
311	336	const struct rockchip_pin_group *grp;
	337	+ struct device *dev = info->dev;
312	338	struct pinctrl_map *new_map;
313	339	struct device_node *parent;
314	340	int map_num = 1;
..	..	@@ -320,8 +346,7 @@
320	346	*/
321	347	grp = pinctrl_name_to_group(info, np->name);
322	348	if (!grp) {
323		- dev_err(info->dev, "unable to find group for node %pOFn\n",
324		- np);
	349	+ dev_err(dev, "unable to find group for node %pOFn\n", np);
325	350	return -EINVAL;
326	351	}
327	352
..	..	@@ -355,7 +380,7 @@
355	380	new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
356	381	}
357	382
358		- dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
	383	+ dev_dbg(dev, "maps: function %s group %s num %d\n",
359	384	(map)->data.mux.function, (map)->data.mux.group, map_num);
360	385
361	386	return 0;
..	..	@@ -510,159 +535,110 @@
510	535
511	536	static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
512	537	{
	538	+ /* gpio1b6_sel */
513	539	.num = 1,
514	540	.pin = 14,
515	541	.reg = 0x28,
516	542	.bit = 12,
517	543	.mask = 0xf
518	544	}, {
	545	+ /* gpio1b7_sel */
519	546	.num = 1,
520	547	.pin = 15,
521	548	.reg = 0x2c,
522	549	.bit = 0,
523	550	.mask = 0x3
524	551	}, {
	552	+ /* gpio1c2_sel */
525	553	.num = 1,
526	554	.pin = 18,
527	555	.reg = 0x30,
528	556	.bit = 4,
529	557	.mask = 0xf
530	558	}, {
	559	+ /* gpio1c3_sel */
531	560	.num = 1,
532	561	.pin = 19,
533	562	.reg = 0x30,
534	563	.bit = 8,
535	564	.mask = 0xf
536	565	}, {
	566	+ /* gpio1c4_sel */
537	567	.num = 1,
538	568	.pin = 20,
539	569	.reg = 0x30,
540	570	.bit = 12,
541	571	.mask = 0xf
542	572	}, {
	573	+ /* gpio1c5_sel */
543	574	.num = 1,
544	575	.pin = 21,
545	576	.reg = 0x34,
546	577	.bit = 0,
547	578	.mask = 0xf
548	579	}, {
	580	+ /* gpio1c6_sel */
549	581	.num = 1,
550	582	.pin = 22,
551	583	.reg = 0x34,
552	584	.bit = 4,
553	585	.mask = 0xf
554	586	}, {
	587	+ /* gpio1c7_sel */
555	588	.num = 1,
556	589	.pin = 23,
557	590	.reg = 0x34,
558	591	.bit = 8,
559	592	.mask = 0xf
560	593	}, {
561		- .num = 3,
562		- .pin = 12,
563		- .reg = 0x68,
564		- .bit = 8,
565		- .mask = 0xf
566		- }, {
567		- .num = 3,
568		- .pin = 13,
569		- .reg = 0x68,
570		- .bit = 12,
571		- .mask = 0xf
572		- },
573		-};
574		-
575		-static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
576		- {
577		- .num = 1,
578		- .pin = 14,
579		- .reg = 0x28,
580		- .bit = 12,
581		- .mask = 0xf
582		- }, {
583		- .num = 1,
584		- .pin = 15,
585		- .reg = 0x2c,
586		- .bit = 0,
587		- .mask = 0x3
588		- }, {
589		- .num = 1,
590		- .pin = 18,
591		- .reg = 0x30,
592		- .bit = 4,
593		- .mask = 0xf
594		- }, {
595		- .num = 1,
596		- .pin = 19,
597		- .reg = 0x30,
598		- .bit = 8,
599		- .mask = 0xf
600		- }, {
601		- .num = 1,
602		- .pin = 20,
603		- .reg = 0x30,
604		- .bit = 12,
605		- .mask = 0xf
606		- }, {
607		- .num = 1,
608		- .pin = 21,
609		- .reg = 0x34,
610		- .bit = 0,
611		- .mask = 0xf
612		- }, {
613		- .num = 1,
614		- .pin = 22,
615		- .reg = 0x34,
616		- .bit = 4,
617		- .mask = 0xf
618		- }, {
619		- .num = 1,
620		- .pin = 23,
621		- .reg = 0x34,
622		- .bit = 8,
623		- .mask = 0xf
624		- }, {
625		- .num = 3,
626		- .pin = 12,
627		- .reg = 0x68,
628		- .bit = 8,
629		- .mask = 0xf
630		- }, {
631		- .num = 3,
632		- .pin = 13,
633		- .reg = 0x68,
634		- .bit = 12,
635		- .mask = 0xf
636		- }, {
	594	+ /* gpio2a2_sel_plus */
637	595	.num = 2,
638	596	.pin = 2,
639	597	.reg = 0x608,
640	598	.bit = 0,
641	599	.mask = 0x7
642	600	}, {
	601	+ /* gpio2a3_sel_plus */
643	602	.num = 2,
644	603	.pin = 3,
645	604	.reg = 0x608,
646	605	.bit = 4,
647	606	.mask = 0x7
648	607	}, {
	608	+ /* gpio2c0_sel_plus */
649	609	.num = 2,
650	610	.pin = 16,
651	611	.reg = 0x610,
652	612	.bit = 8,
653	613	.mask = 0x7
654	614	}, {
	615	+ /* gpio3b2_sel_plus */
655	616	.num = 3,
656	617	.pin = 10,
657	618	.reg = 0x610,
658	619	.bit = 0,
659	620	.mask = 0x7
660	621	}, {
	622	+ /* gpio3b3_sel_plus */
661	623	.num = 3,
662	624	.pin = 11,
663	625	.reg = 0x610,
664	626	.bit = 4,
665	627	.mask = 0x7
	628	+ }, {
	629	+ /* gpio3b4_sel */
	630	+ .num = 3,
	631	+ .pin = 12,
	632	+ .reg = 0x68,
	633	+ .bit = 8,
	634	+ .mask = 0xf
	635	+ }, {
	636	+ /* gpio3b5_sel */
	637	+ .num = 3,
	638	+ .pin = 13,
	639	+ .reg = 0x68,
	640	+ .bit = 12,
	641	+ .mask = 0xf
666	642	},
667	643	};
668	644
..	..	@@ -725,16 +701,23 @@
725	701	};
726	702
727	703	static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
	704	+ RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
728	705	RK_MUXROUTE_GRF(3, RK_PD1, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_RX_M0 */
729	706	RK_MUXROUTE_GRF(3, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_TX_M0 */
	707	+ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
730	708	RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_RX_M1 */
731	709	RK_MUXROUTE_GRF(3, RK_PA4, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_TX_M1 */
732	710
	711	+ RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
733	712	RK_MUXROUTE_GRF(1, RK_PA1, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_SCLK_M0 */
	713	+ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
734	714	RK_MUXROUTE_GRF(1, RK_PD6, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_SCLK_M1 */
	715	+ RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
735	716	RK_MUXROUTE_GRF(2, RK_PD1, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_SCLK_M2 */
736	717
	718	+ RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
737	719	RK_MUXROUTE_GRF(1, RK_PC6, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_SCLK_M0 */
	720	+ RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
738	721	RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_SCLK_M1 */
739	722
740	723	RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
..	..	@@ -916,22 +899,6 @@
916	899	RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) \| BIT(0)), /* rtc_clk */
917	900	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3)), /* uart2_rxm0 */
918	901	RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3) \| BIT(2)), /* uart2_rxm1 */
919		- RK_MUXROUTE_SAME(0, RK_PC7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
920		- RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) \| BIT(4)), /* i2c3_sdam1 */
921		- RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
922		- RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
923		- RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) \| BIT(3)), /* i2s-8ch-1-sclktxm1 */
924		- RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) \| BIT(3)), /* i2s-8ch-1-sclkrxm1 */
925		- RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) \| BIT(16 + 13)), /* pdm-clkm0 */
926		- RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) \| BIT(16 + 13) \| BIT(12)), /* pdm-clkm1 */
927		- RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) \| BIT(16 + 13) \| BIT(13)), /* pdm-clkm2 */
928		- RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) \| BIT(2)), /* pdm-clkm-m2 */
929		-};
930		-
931		-static struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
932		- RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) \| BIT(0)), /* rtc_clk */
933		- RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3)), /* uart2_rxm0 */
934		- RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) \| BIT(16 + 3) \| BIT(2)), /* uart2_rxm1 */
935	902	RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) \| BIT(16 + 9)), /* i2c3_sdam0 */
936	903	RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) \| BIT(16 + 9) \| BIT(8)), /* i2c3_sdam1 */
937	904	RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) \| BIT(16 + 9) \| BIT(9)), /* i2c3_sdam2 */
..	..	@@ -965,7 +932,9 @@
965	932	RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
966	933	RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) \| BIT(3)), /* pdm_sdi0m1 */
967	934	RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) \| BIT(16 + 5) \| BIT(5)), /* spi_rxdm2 */
	935	+ RK_MUXROUTE_SAME(1, RK_PC6, 1, 0x50, BIT(16 + 6)), /* i2s2_sclkm0 */
968	936	RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
	937	+ RK_MUXROUTE_SAME(3, RK_PA0, 6, 0x50, BIT(16 + 6) \| BIT(6)), /* i2s2_sclkm1 */
969	938	RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) \| BIT(6)), /* i2s2_sdim1 */
970	939	RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) \| BIT(7)), /* card_iom1 */
971	940	RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) \| BIT(8)), /* tsp_d5m1 */
..	..	@@ -1054,25 +1023,25 @@
1054	1023	RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1055	1024	RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1056	1025	RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1057		- RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1058		- RK_MUXROUTE_GRF(1, RK_PA3, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux sclk tx M0 */
1059		- RK_MUXROUTE_GRF(1, RK_PA4, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux sclk rx M0 */
1060		- RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1061		- RK_MUXROUTE_GRF(3, RK_PC7, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux sclk tx M1 */
1062		- RK_MUXROUTE_GRF(4, RK_PA6, 5, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux sclk rx M1 */
1063		- RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1064		- RK_MUXROUTE_GRF(2, RK_PD1, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux sclk tx M2 */
1065		- RK_MUXROUTE_GRF(3, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux sclk rx M2 */
1066		- RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1067		- RK_MUXROUTE_GRF(2, RK_PC2, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux sclk tx M0 */
1068		- RK_MUXROUTE_GRF(2, RK_PB7, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux sclk rx M0 */
1069		- RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1070		- RK_MUXROUTE_GRF(4, RK_PB7, 4, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S1 IO mux sclk tx M1 */
1071		- RK_MUXROUTE_GRF(4, RK_PC1, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S1 IO mux sclk rx M1 */
1072		- RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1073		- RK_MUXROUTE_GRF(3, RK_PA3, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux sclk M0 */
1074		- RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1075		- RK_MUXROUTE_GRF(4, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux sclk M1 */
	1026	+ RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 MCLK mux M0 */
	1027	+ RK_MUXROUTE_GRF(1, RK_PA4, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 SCLKRX mux M0 */
	1028	+ RK_MUXROUTE_GRF(1, RK_PA3, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 SCLKTX mux M0 */
	1029	+ RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 MCLK mux M1 */
	1030	+ RK_MUXROUTE_GRF(4, RK_PA6, 5, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 SCLKRX mux M1 */
	1031	+ RK_MUXROUTE_GRF(3, RK_PC7, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 SCLKTX mux M1 */
	1032	+ RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 MCLK mux M2 */
	1033	+ RK_MUXROUTE_GRF(3, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 SCLKRX mux M2 */
	1034	+ RK_MUXROUTE_GRF(2, RK_PD1, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 SCLKTX mux M2 */
	1035	+ RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 MCLK mux M0 */
	1036	+ RK_MUXROUTE_GRF(2, RK_PB7, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 SCLKRX mux M0 */
	1037	+ RK_MUXROUTE_GRF(2, RK_PC2, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 SCLKTX mux M0 */
	1038	+ RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 MCLK mux M1 */
	1039	+ RK_MUXROUTE_GRF(4, RK_PC1, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 SCLKRX mux M1 */
	1040	+ RK_MUXROUTE_GRF(4, RK_PB7, 4, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 SCLKTX mux M1 */
	1041	+ RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 MCLK mux M0 */
	1042	+ RK_MUXROUTE_GRF(3, RK_PA3, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 SCLK mux M0 */
	1043	+ RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 MCLK mux M1 */
	1044	+ RK_MUXROUTE_GRF(4, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 SCLK mux M1 */
1076	1045	RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1077	1046	RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1078	1047	RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
..	..	@@ -1117,6 +1086,7 @@
1117	1086	static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1118	1087	{
1119	1088	struct rockchip_pinctrl *info = bank->drvdata;
	1089	+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
1120	1090	int iomux_num = (pin / 8);
1121	1091	struct regmap *regmap;
1122	1092	unsigned int val;
..	..	@@ -1162,6 +1132,27 @@
1162	1132	if (bank->recalced_mask & BIT(pin))
1163	1133	rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1164	1134
	1135	+ if (ctrl->type == RK3588) {
	1136	+ if (bank->bank_num == 0) {
	1137	+ if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
	1138	+ u32 reg0 = 0;
	1139	+
	1140	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1141	+ ret = regmap_read(regmap, reg0, &val);
	1142	+ if (ret)
	1143	+ return ret;
	1144	+
	1145	+ if (((val >> bit) & mask) != 8)
	1146	+ return ((val >> bit) & mask);
	1147	+
	1148	+ reg = reg + 0x8000; /* BUS_IOC_BASE */
	1149	+ regmap = info->regmap_base;
	1150	+ }
	1151	+ } else if (bank->bank_num > 0) {
	1152	+ reg += 0x8000; /* BUS_IOC_BASE */
	1153	+ }
	1154	+ }
	1155	+
1165	1156	ret = regmap_read(regmap, reg, &val);
1166	1157	if (ret)
1167	1158	return ret;
..	..	@@ -1173,20 +1164,20 @@
1173	1164	int pin, int mux)
1174	1165	{
1175	1166	struct rockchip_pinctrl *info = bank->drvdata;
	1167	+ struct device *dev = info->dev;
1176	1168	int iomux_num = (pin / 8);
1177	1169
1178	1170	if (iomux_num > 3)
1179	1171	return -EINVAL;
1180	1172
1181	1173	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1182		- dev_err(info->dev, "pin %d is unrouted\n", pin);
	1174	+ dev_err(dev, "pin %d is unrouted\n", pin);
1183	1175	return -EINVAL;
1184	1176	}
1185	1177
1186	1178	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1187	1179	if (mux != RK_FUNC_GPIO) {
1188		- dev_err(info->dev,
1189		- "pin %d only supports a gpio mux\n", pin);
	1180	+ dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1190	1181	return -ENOTSUPP;
1191	1182	}
1192	1183	}
..	..	@@ -1210,6 +1201,8 @@
1210	1201	static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1211	1202	{
1212	1203	struct rockchip_pinctrl *info = bank->drvdata;
	1204	+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
	1205	+ struct device *dev = info->dev;
1213	1206	int iomux_num = (pin / 8);
1214	1207	struct regmap *regmap;
1215	1208	int reg, ret, mask, mux_type;
..	..	@@ -1223,8 +1216,7 @@
1223	1216	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1224	1217	return 0;
1225	1218
1226		- dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1227		- bank->bank_num, pin, mux);
	1219	+ dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1228	1220
1229	1221	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1230	1222	regmap = info->regmap_pmu;
..	..	@@ -1253,6 +1245,64 @@
1253	1245
1254	1246	if (bank->recalced_mask & BIT(pin))
1255	1247	rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
	1248	+
	1249	+ /* rk3562 force jtag m1 */
	1250	+ if (ctrl->type == RK3562) {
	1251	+ if (bank->bank_num == 1) {
	1252	+ if ((pin == RK_PB5) \|\| (pin == RK_PB6)) {
	1253	+ if (mux == 1) {
	1254	+ regmap_update_bits(regmap, 0x504, 0x10001, 0x10001);
	1255	+ } else {
	1256	+ regmap_update_bits(regmap, 0x504, 0x10001, 0x10000);
	1257	+ }
	1258	+ }
	1259	+ }
	1260	+ }
	1261	+
	1262	+ if (ctrl->type == RK3588) {
	1263	+ if (bank->bank_num == 0) {
	1264	+ if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
	1265	+ if (mux < 8) {
	1266	+ u32 reg0 = 0;
	1267	+
	1268	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1269	+ data = (mask << (bit + 16));
	1270	+ rmask = data \| (data >> 16);
	1271	+ data \|= (mux & mask) << bit;
	1272	+ ret = regmap_update_bits(regmap, reg0, rmask, data);
	1273	+
	1274	+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
	1275	+ data = (mask << (bit + 16));
	1276	+ rmask = data \| (data >> 16);
	1277	+ regmap = info->regmap_base;
	1278	+ ret \|= regmap_update_bits(regmap, reg0, rmask, data);
	1279	+ } else {
	1280	+ u32 reg0 = 0;
	1281	+
	1282	+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
	1283	+ data = (mask << (bit + 16));
	1284	+ rmask = data \| (data >> 16);
	1285	+ data \|= 8 << bit;
	1286	+ ret = regmap_update_bits(regmap, reg0, rmask, data);
	1287	+
	1288	+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
	1289	+ data = (mask << (bit + 16));
	1290	+ rmask = data \| (data >> 16);
	1291	+ data \|= (mux & mask) << bit;
	1292	+ regmap = info->regmap_base;
	1293	+ ret \|= regmap_update_bits(regmap, reg0, rmask, data);
	1294	+ }
	1295	+ } else {
	1296	+ data = (mask << (bit + 16));
	1297	+ rmask = data \| (data >> 16);
	1298	+ data \|= (mux & mask) << bit;
	1299	+ ret = regmap_update_bits(regmap, reg, rmask, data);
	1300	+ }
	1301	+ return ret;
	1302	+ } else if (bank->bank_num > 0) {
	1303	+ reg += 0x8000; /* BUS_IOC_BASE */
	1304	+ }
	1305	+ }
1256	1306
1257	1307	if (mux > mask)
1258	1308	return -EINVAL;
..	..	@@ -1302,9 +1352,9 @@
1302	1352	#define PX30_PULL_PINS_PER_REG 8
1303	1353	#define PX30_PULL_BANK_STRIDE 16
1304	1354
1305		-static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1306		- int pin_num, struct regmap **regmap,
1307		- int reg, u8 bit)
	1355	+static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1356	+ int pin_num, struct regmap **regmap,
	1357	+ int reg, u8 bit)
1308	1358	{
1309	1359	struct rockchip_pinctrl *info = bank->drvdata;
1310	1360
..	..	@@ -1324,6 +1374,8 @@
1324	1374	reg += ((pin_num / PX30_PULL_PINS_PER_REG) 4);
1325	1375	*bit = (pin_num % PX30_PULL_PINS_PER_REG);
1326	1376	bit = PX30_PULL_BITS_PER_PIN;
	1377	+
	1378	+ return 0;
1327	1379	}
1328	1380
1329	1381	#define PX30_DRV_PMU_OFFSET 0x20
..	..	@@ -1332,9 +1384,9 @@
1332	1384	#define PX30_DRV_PINS_PER_REG 8
1333	1385	#define PX30_DRV_BANK_STRIDE 16
1334	1386
1335		-static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1336		- int pin_num, struct regmap **regmap,
1337		- int reg, u8 bit)
	1387	+static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1388	+ int pin_num, struct regmap **regmap,
	1389	+ int reg, u8 bit)
1338	1390	{
1339	1391	struct rockchip_pinctrl *info = bank->drvdata;
1340	1392
..	..	@@ -1354,6 +1406,8 @@
1354	1406	reg += ((pin_num / PX30_DRV_PINS_PER_REG) 4);
1355	1407	*bit = (pin_num % PX30_DRV_PINS_PER_REG);
1356	1408	bit = PX30_DRV_BITS_PER_PIN;
	1409	+
	1410	+ return 0;
1357	1411	}
1358	1412
1359	1413	#define PX30_SCHMITT_PMU_OFFSET 0x38
..	..	@@ -1387,15 +1441,175 @@
1387	1441	return 0;
1388	1442	}
1389	1443
	1444	+#define RV1106_DRV_BITS_PER_PIN 8
	1445	+#define RV1106_DRV_PINS_PER_REG 2
	1446	+#define RV1106_DRV_GPIO0_OFFSET 0x10
	1447	+#define RV1106_DRV_GPIO1_OFFSET 0x80
	1448	+#define RV1106_DRV_GPIO2_OFFSET 0x100C0
	1449	+#define RV1106_DRV_GPIO3_OFFSET 0x20100
	1450	+#define RV1106_DRV_GPIO4_OFFSET 0x30020
	1451	+
	1452	+static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1453	+ int pin_num, struct regmap **regmap,
	1454	+ int reg, u8 bit)
	1455	+{
	1456	+ struct rockchip_pinctrl *info = bank->drvdata;
	1457	+
	1458	+ /* GPIO0_IOC is located in PMU */
	1459	+ switch (bank->bank_num) {
	1460	+ case 0:
	1461	+ *regmap = info->regmap_pmu;
	1462	+ *reg = RV1106_DRV_GPIO0_OFFSET;
	1463	+ break;
	1464	+
	1465	+ case 1:
	1466	+ *regmap = info->regmap_base;
	1467	+ *reg = RV1106_DRV_GPIO1_OFFSET;
	1468	+ break;
	1469	+
	1470	+ case 2:
	1471	+ *regmap = info->regmap_base;
	1472	+ *reg = RV1106_DRV_GPIO2_OFFSET;
	1473	+ break;
	1474	+
	1475	+ case 3:
	1476	+ *regmap = info->regmap_base;
	1477	+ *reg = RV1106_DRV_GPIO3_OFFSET;
	1478	+ break;
	1479	+
	1480	+ case 4:
	1481	+ *regmap = info->regmap_base;
	1482	+ *reg = RV1106_DRV_GPIO4_OFFSET;
	1483	+ break;
	1484	+
	1485	+ default:
	1486	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1487	+ break;
	1488	+ }
	1489	+
	1490	+ reg += ((pin_num / RV1106_DRV_PINS_PER_REG) 4);
	1491	+ *bit = pin_num % RV1106_DRV_PINS_PER_REG;
	1492	+ bit = RV1106_DRV_BITS_PER_PIN;
	1493	+
	1494	+ return 0;
	1495	+}
	1496	+
	1497	+#define RV1106_PULL_BITS_PER_PIN 2
	1498	+#define RV1106_PULL_PINS_PER_REG 8
	1499	+#define RV1106_PULL_GPIO0_OFFSET 0x38
	1500	+#define RV1106_PULL_GPIO1_OFFSET 0x1C0
	1501	+#define RV1106_PULL_GPIO2_OFFSET 0x101D0
	1502	+#define RV1106_PULL_GPIO3_OFFSET 0x201E0
	1503	+#define RV1106_PULL_GPIO4_OFFSET 0x30070
	1504	+
	1505	+static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1506	+ int pin_num, struct regmap **regmap,
	1507	+ int reg, u8 bit)
	1508	+{
	1509	+ struct rockchip_pinctrl *info = bank->drvdata;
	1510	+
	1511	+ /* GPIO0_IOC is located in PMU */
	1512	+ switch (bank->bank_num) {
	1513	+ case 0:
	1514	+ *regmap = info->regmap_pmu;
	1515	+ *reg = RV1106_PULL_GPIO0_OFFSET;
	1516	+ break;
	1517	+
	1518	+ case 1:
	1519	+ *regmap = info->regmap_base;
	1520	+ *reg = RV1106_PULL_GPIO1_OFFSET;
	1521	+ break;
	1522	+
	1523	+ case 2:
	1524	+ *regmap = info->regmap_base;
	1525	+ *reg = RV1106_PULL_GPIO2_OFFSET;
	1526	+ break;
	1527	+
	1528	+ case 3:
	1529	+ *regmap = info->regmap_base;
	1530	+ *reg = RV1106_PULL_GPIO3_OFFSET;
	1531	+ break;
	1532	+
	1533	+ case 4:
	1534	+ *regmap = info->regmap_base;
	1535	+ *reg = RV1106_PULL_GPIO4_OFFSET;
	1536	+ break;
	1537	+
	1538	+ default:
	1539	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1540	+ break;
	1541	+ }
	1542	+
	1543	+ reg += ((pin_num / RV1106_PULL_PINS_PER_REG) 4);
	1544	+ *bit = pin_num % RV1106_PULL_PINS_PER_REG;
	1545	+ bit = RV1106_PULL_BITS_PER_PIN;
	1546	+
	1547	+ return 0;
	1548	+}
	1549	+
	1550	+#define RV1106_SMT_BITS_PER_PIN 1
	1551	+#define RV1106_SMT_PINS_PER_REG 8
	1552	+#define RV1106_SMT_GPIO0_OFFSET 0x40
	1553	+#define RV1106_SMT_GPIO1_OFFSET 0x280
	1554	+#define RV1106_SMT_GPIO2_OFFSET 0x10290
	1555	+#define RV1106_SMT_GPIO3_OFFSET 0x202A0
	1556	+#define RV1106_SMT_GPIO4_OFFSET 0x300A0
	1557	+
	1558	+static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1559	+ int pin_num,
	1560	+ struct regmap **regmap,
	1561	+ int reg, u8 bit)
	1562	+{
	1563	+ struct rockchip_pinctrl *info = bank->drvdata;
	1564	+
	1565	+ /* GPIO0_IOC is located in PMU */
	1566	+ switch (bank->bank_num) {
	1567	+ case 0:
	1568	+ *regmap = info->regmap_pmu;
	1569	+ *reg = RV1106_SMT_GPIO0_OFFSET;
	1570	+ break;
	1571	+
	1572	+ case 1:
	1573	+ *regmap = info->regmap_base;
	1574	+ *reg = RV1106_SMT_GPIO1_OFFSET;
	1575	+ break;
	1576	+
	1577	+ case 2:
	1578	+ *regmap = info->regmap_base;
	1579	+ *reg = RV1106_SMT_GPIO2_OFFSET;
	1580	+ break;
	1581	+
	1582	+ case 3:
	1583	+ *regmap = info->regmap_base;
	1584	+ *reg = RV1106_SMT_GPIO3_OFFSET;
	1585	+ break;
	1586	+
	1587	+ case 4:
	1588	+ *regmap = info->regmap_base;
	1589	+ *reg = RV1106_SMT_GPIO4_OFFSET;
	1590	+ break;
	1591	+
	1592	+ default:
	1593	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	1594	+ break;
	1595	+ }
	1596	+
	1597	+ reg += ((pin_num / RV1106_SMT_PINS_PER_REG) 4);
	1598	+ *bit = pin_num % RV1106_SMT_PINS_PER_REG;
	1599	+ bit = RV1106_SMT_BITS_PER_PIN;
	1600	+
	1601	+ return 0;
	1602	+}
	1603	+
1390	1604	#define RV1108_PULL_PMU_OFFSET 0x10
1391	1605	#define RV1108_PULL_OFFSET 0x110
1392	1606	#define RV1108_PULL_PINS_PER_REG 8
1393	1607	#define RV1108_PULL_BITS_PER_PIN 2
1394	1608	#define RV1108_PULL_BANK_STRIDE 16
1395	1609
1396		-static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1397		- int pin_num, struct regmap **regmap,
1398		- int reg, u8 bit)
	1610	+static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1611	+ int pin_num, struct regmap **regmap,
	1612	+ int reg, u8 bit)
1399	1613	{
1400	1614	struct rockchip_pinctrl *info = bank->drvdata;
1401	1615
..	..	@@ -1414,6 +1628,8 @@
1414	1628	reg += ((pin_num / RV1108_PULL_PINS_PER_REG) 4);
1415	1629	*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1416	1630	bit = RV1108_PULL_BITS_PER_PIN;
	1631	+
	1632	+ return 0;
1417	1633	}
1418	1634
1419	1635	#define RV1108_DRV_PMU_OFFSET 0x20
..	..	@@ -1422,9 +1638,9 @@
1422	1638	#define RV1108_DRV_PINS_PER_REG 8
1423	1639	#define RV1108_DRV_BANK_STRIDE 16
1424	1640
1425		-static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1426		- int pin_num, struct regmap **regmap,
1427		- int reg, u8 bit)
	1641	+static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1642	+ int pin_num, struct regmap **regmap,
	1643	+ int reg, u8 bit)
1428	1644	{
1429	1645	struct rockchip_pinctrl *info = bank->drvdata;
1430	1646
..	..	@@ -1444,6 +1660,8 @@
1444	1660	reg += ((pin_num / RV1108_DRV_PINS_PER_REG) 4);
1445	1661	*bit = pin_num % RV1108_DRV_PINS_PER_REG;
1446	1662	bit = RV1108_DRV_BITS_PER_PIN;
	1663	+
	1664	+ return 0;
1447	1665	}
1448	1666
1449	1667	#define RV1108_SCHMITT_PMU_OFFSET 0x30
..	..	@@ -1483,9 +1701,9 @@
1483	1701	#define RV1126_PULL_BANK_STRIDE 16
1484	1702	#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1485	1703
1486		-static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1487		- int pin_num, struct regmap **regmap,
1488		- int reg, u8 bit)
	1704	+static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1705	+ int pin_num, struct regmap **regmap,
	1706	+ int reg, u8 bit)
1489	1707	{
1490	1708	struct rockchip_pinctrl *info = bank->drvdata;
1491	1709
..	..	@@ -1497,7 +1715,7 @@
1497	1715	reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) 4);
1498	1716	*bit = pin_num % RV1126_PULL_PINS_PER_REG;
1499	1717	bit = RV1126_PULL_BITS_PER_PIN;
1500		- return;
	1718	+ return 0;
1501	1719	}
1502	1720	*regmap = info->regmap_pmu;
1503	1721	*reg = RV1126_PULL_PMU_OFFSET;
..	..	@@ -1510,6 +1728,8 @@
1510	1728	reg += ((pin_num / RV1126_PULL_PINS_PER_REG) 4);
1511	1729	*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1512	1730	bit = RV1126_PULL_BITS_PER_PIN;
	1731	+
	1732	+ return 0;
1513	1733	}
1514	1734
1515	1735	#define RV1126_DRV_PMU_OFFSET 0x20
..	..	@@ -1518,9 +1738,9 @@
1518	1738	#define RV1126_DRV_PINS_PER_REG 4
1519	1739	#define RV1126_DRV_BANK_STRIDE 32
1520	1740
1521		-static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1522		- int pin_num, struct regmap **regmap,
1523		- int reg, u8 bit)
	1741	+static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1742	+ int pin_num, struct regmap **regmap,
	1743	+ int reg, u8 bit)
1524	1744	{
1525	1745	struct rockchip_pinctrl *info = bank->drvdata;
1526	1746
..	..	@@ -1533,7 +1753,7 @@
1533	1753	*reg -= 0x4;
1534	1754	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1535	1755	bit = RV1126_DRV_BITS_PER_PIN;
1536		- return;
	1756	+ return 0;
1537	1757	}
1538	1758	*regmap = info->regmap_pmu;
1539	1759	*reg = RV1126_DRV_PMU_OFFSET;
..	..	@@ -1546,6 +1766,8 @@
1546	1766	reg += ((pin_num / RV1126_DRV_PINS_PER_REG) 4);
1547	1767	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1548	1768	bit = RV1126_DRV_BITS_PER_PIN;
	1769	+
	1770	+ return 0;
1549	1771	}
1550	1772
1551	1773	#define RV1126_SCHMITT_PMU_OFFSET 0x60
..	..	@@ -1585,15 +1807,35 @@
1585	1807	return 0;
1586	1808	}
1587	1809
	1810	+#define RK3308_SCHMITT_PINS_PER_REG 8
	1811	+#define RK3308_SCHMITT_BANK_STRIDE 16
	1812	+#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
	1813	+
	1814	+static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1815	+ int pin_num, struct regmap **regmap,
	1816	+ int reg, u8 bit)
	1817	+{
	1818	+ struct rockchip_pinctrl *info = bank->drvdata;
	1819	+
	1820	+ *regmap = info->regmap_base;
	1821	+ *reg = RK3308_SCHMITT_GRF_OFFSET;
	1822	+
	1823	+ reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
	1824	+ reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
	1825	+ *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
	1826	+
	1827	+ return 0;
	1828	+}
	1829	+
1588	1830	#define RK1808_PULL_PMU_OFFSET 0x10
1589	1831	#define RK1808_PULL_GRF_OFFSET 0x80
1590	1832	#define RK1808_PULL_PINS_PER_REG 8
1591	1833	#define RK1808_PULL_BITS_PER_PIN 2
1592	1834	#define RK1808_PULL_BANK_STRIDE 16
1593	1835
1594		-static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1595		- int pin_num, struct regmap **regmap,
1596		- int reg, u8 bit)
	1836	+static int rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1837	+ int pin_num, struct regmap **regmap,
	1838	+ int reg, u8 bit)
1597	1839	{
1598	1840	struct rockchip_pinctrl *info = bank->drvdata;
1599	1841
..	..	@@ -1609,6 +1851,8 @@
1609	1851	reg += ((pin_num / RK1808_PULL_PINS_PER_REG) 4);
1610	1852	*bit = (pin_num % RK1808_PULL_PINS_PER_REG);
1611	1853	bit = RK1808_PULL_BITS_PER_PIN;
	1854	+
	1855	+ return 0;
1612	1856	}
1613	1857
1614	1858	#define RK1808_DRV_PMU_OFFSET 0x20
..	..	@@ -1617,10 +1861,10 @@
1617	1861	#define RK1808_DRV_PINS_PER_REG 8
1618	1862	#define RK1808_DRV_BANK_STRIDE 16
1619	1863
1620		-static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1621		- int pin_num,
1622		- struct regmap **regmap,
1623		- int reg, u8 bit)
	1864	+static int rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1865	+ int pin_num,
	1866	+ struct regmap **regmap,
	1867	+ int reg, u8 bit)
1624	1868	{
1625	1869	struct rockchip_pinctrl *info = bank->drvdata;
1626	1870
..	..	@@ -1636,6 +1880,8 @@
1636	1880	reg += ((pin_num / RK1808_DRV_PINS_PER_REG) 4);
1637	1881	*bit = pin_num % RK1808_DRV_PINS_PER_REG;
1638	1882	bit = RK1808_DRV_BITS_PER_PIN;
	1883	+
	1884	+ return 0;
1639	1885	}
1640	1886
1641	1887	#define RK1808_SR_PMU_OFFSET 0x0030
..	..	@@ -1694,9 +1940,9 @@
1694	1940	#define RK2928_PULL_PINS_PER_REG 16
1695	1941	#define RK2928_PULL_BANK_STRIDE 8
1696	1942
1697		-static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1698		- int pin_num, struct regmap **regmap,
1699		- int reg, u8 bit)
	1943	+static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1944	+ int pin_num, struct regmap **regmap,
	1945	+ int reg, u8 bit)
1700	1946	{
1701	1947	struct rockchip_pinctrl *info = bank->drvdata;
1702	1948
..	..	@@ -1706,13 +1952,15 @@
1706	1952	reg += (pin_num / RK2928_PULL_PINS_PER_REG) 4;
1707	1953
1708	1954	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
	1955	+
	1956	+ return 0;
1709	1957	};
1710	1958
1711	1959	#define RK3128_PULL_OFFSET 0x118
1712	1960
1713		-static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1714		- int pin_num, struct regmap **regmap,
1715		- int reg, u8 bit)
	1961	+static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1962	+ int pin_num, struct regmap **regmap,
	1963	+ int reg, u8 bit)
1716	1964	{
1717	1965	struct rockchip_pinctrl *info = bank->drvdata;
1718	1966
..	..	@@ -1722,6 +1970,8 @@
1722	1970	reg += ((pin_num / RK2928_PULL_PINS_PER_REG) 4);
1723	1971
1724	1972	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
	1973	+
	1974	+ return 0;
1725	1975	}
1726	1976
1727	1977	#define RK3188_PULL_OFFSET 0x164
..	..	@@ -1730,9 +1980,9 @@
1730	1980	#define RK3188_PULL_BANK_STRIDE 16
1731	1981	#define RK3188_PULL_PMU_OFFSET 0x64
1732	1982
1733		-static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1734		- int pin_num, struct regmap **regmap,
1735		- int reg, u8 bit)
	1983	+static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1984	+ int pin_num, struct regmap **regmap,
	1985	+ int reg, u8 bit)
1736	1986	{
1737	1987	struct rockchip_pinctrl *info = bank->drvdata;
1738	1988
..	..	@@ -1762,12 +2012,14 @@
1762	2012	*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1763	2013	bit = RK3188_PULL_BITS_PER_PIN;
1764	2014	}
	2015	+
	2016	+ return 0;
1765	2017	}
1766	2018
1767	2019	#define RK3288_PULL_OFFSET 0x140
1768		-static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1769		- int pin_num, struct regmap **regmap,
1770		- int reg, u8 bit)
	2020	+static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2021	+ int pin_num, struct regmap **regmap,
	2022	+ int reg, u8 bit)
1771	2023	{
1772	2024	struct rockchip_pinctrl *info = bank->drvdata;
1773	2025
..	..	@@ -1791,6 +2043,8 @@
1791	2043	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1792	2044	bit = RK3188_PULL_BITS_PER_PIN;
1793	2045	}
	2046	+
	2047	+ return 0;
1794	2048	}
1795	2049
1796	2050	#define RK3288_DRV_PMU_OFFSET 0x70
..	..	@@ -1799,9 +2053,9 @@
1799	2053	#define RK3288_DRV_PINS_PER_REG 8
1800	2054	#define RK3288_DRV_BANK_STRIDE 16
1801	2055
1802		-static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1803		- int pin_num, struct regmap **regmap,
1804		- int reg, u8 bit)
	2056	+static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2057	+ int pin_num, struct regmap **regmap,
	2058	+ int reg, u8 bit)
1805	2059	{
1806	2060	struct rockchip_pinctrl *info = bank->drvdata;
1807	2061
..	..	@@ -1825,13 +2079,15 @@
1825	2079	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1826	2080	bit = RK3288_DRV_BITS_PER_PIN;
1827	2081	}
	2082	+
	2083	+ return 0;
1828	2084	}
1829	2085
1830	2086	#define RK3228_PULL_OFFSET 0x100
1831	2087
1832		-static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1833		- int pin_num, struct regmap **regmap,
1834		- int reg, u8 bit)
	2088	+static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2089	+ int pin_num, struct regmap **regmap,
	2090	+ int reg, u8 bit)
1835	2091	{
1836	2092	struct rockchip_pinctrl *info = bank->drvdata;
1837	2093
..	..	@@ -1842,13 +2098,15 @@
1842	2098
1843	2099	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1844	2100	bit = RK3188_PULL_BITS_PER_PIN;
	2101	+
	2102	+ return 0;
1845	2103	}
1846	2104
1847	2105	#define RK3228_DRV_GRF_OFFSET 0x200
1848	2106
1849		-static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1850		- int pin_num, struct regmap **regmap,
1851		- int reg, u8 bit)
	2107	+static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2108	+ int pin_num, struct regmap **regmap,
	2109	+ int reg, u8 bit)
1852	2110	{
1853	2111	struct rockchip_pinctrl *info = bank->drvdata;
1854	2112
..	..	@@ -1859,13 +2117,15 @@
1859	2117
1860	2118	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1861	2119	bit = RK3288_DRV_BITS_PER_PIN;
	2120	+
	2121	+ return 0;
1862	2122	}
1863	2123
1864	2124	#define RK3308_PULL_OFFSET 0xa0
1865	2125
1866		-static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1867		- int pin_num, struct regmap **regmap,
1868		- int reg, u8 bit)
	2126	+static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2127	+ int pin_num, struct regmap **regmap,
	2128	+ int reg, u8 bit)
1869	2129	{
1870	2130	struct rockchip_pinctrl *info = bank->drvdata;
1871	2131
..	..	@@ -1876,13 +2136,15 @@
1876	2136
1877	2137	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1878	2138	bit = RK3188_PULL_BITS_PER_PIN;
	2139	+
	2140	+ return 0;
1879	2141	}
1880	2142
1881	2143	#define RK3308_DRV_GRF_OFFSET 0x100
1882	2144
1883		-static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1884		- int pin_num, struct regmap **regmap,
1885		- int reg, u8 bit)
	2145	+static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2146	+ int pin_num, struct regmap **regmap,
	2147	+ int reg, u8 bit)
1886	2148	{
1887	2149	struct rockchip_pinctrl *info = bank->drvdata;
1888	2150
..	..	@@ -1893,14 +2155,39 @@
1893	2155
1894	2156	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1895	2157	bit = RK3288_DRV_BITS_PER_PIN;
	2158	+
	2159	+ return 0;
	2160	+}
	2161	+
	2162	+#define RK3308_SLEW_RATE_GRF_OFFSET 0x150
	2163	+#define RK3308_SLEW_RATE_BANK_STRIDE 16
	2164	+#define RK3308_SLEW_RATE_PINS_PER_GRF_REG 8
	2165	+
	2166	+static int rk3308_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
	2167	+ int pin_num,
	2168	+ struct regmap **regmap,
	2169	+ int reg, u8 bit)
	2170	+{
	2171	+ struct rockchip_pinctrl *info = bank->drvdata;
	2172	+ int pins_per_reg;
	2173	+
	2174	+ *regmap = info->regmap_base;
	2175	+ *reg = RK3308_SLEW_RATE_GRF_OFFSET;
	2176	+ reg += (bank->bank_num) RK3308_SLEW_RATE_BANK_STRIDE;
	2177	+ pins_per_reg = RK3308_SLEW_RATE_PINS_PER_GRF_REG;
	2178	+
	2179	+ reg += ((pin_num / pins_per_reg) 4);
	2180	+ *bit = pin_num % pins_per_reg;
	2181	+
	2182	+ return 0;
1896	2183	}
1897	2184
1898	2185	#define RK3368_PULL_GRF_OFFSET 0x100
1899	2186	#define RK3368_PULL_PMU_OFFSET 0x10
1900	2187
1901		-static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1902		- int pin_num, struct regmap **regmap,
1903		- int reg, u8 bit)
	2188	+static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2189	+ int pin_num, struct regmap **regmap,
	2190	+ int reg, u8 bit)
1904	2191	{
1905	2192	struct rockchip_pinctrl *info = bank->drvdata;
1906	2193
..	..	@@ -1924,14 +2211,16 @@
1924	2211	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1925	2212	bit = RK3188_PULL_BITS_PER_PIN;
1926	2213	}
	2214	+
	2215	+ return 0;
1927	2216	}
1928	2217
1929	2218	#define RK3368_DRV_PMU_OFFSET 0x20
1930	2219	#define RK3368_DRV_GRF_OFFSET 0x200
1931	2220
1932		-static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1933		- int pin_num, struct regmap **regmap,
1934		- int reg, u8 bit)
	2221	+static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2222	+ int pin_num, struct regmap **regmap,
	2223	+ int reg, u8 bit)
1935	2224	{
1936	2225	struct rockchip_pinctrl *info = bank->drvdata;
1937	2226
..	..	@@ -1955,15 +2244,17 @@
1955	2244	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1956	2245	bit = RK3288_DRV_BITS_PER_PIN;
1957	2246	}
	2247	+
	2248	+ return 0;
1958	2249	}
1959	2250
1960	2251	#define RK3399_PULL_GRF_OFFSET 0xe040
1961	2252	#define RK3399_PULL_PMU_OFFSET 0x40
1962	2253	#define RK3399_DRV_3BITS_PER_PIN 3
1963	2254
1964		-static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1965		- int pin_num, struct regmap **regmap,
1966		- int reg, u8 bit)
	2255	+static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2256	+ int pin_num, struct regmap **regmap,
	2257	+ int reg, u8 bit)
1967	2258	{
1968	2259	struct rockchip_pinctrl *info = bank->drvdata;
1969	2260
..	..	@@ -1989,11 +2280,13 @@
1989	2280	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1990	2281	bit = RK3188_PULL_BITS_PER_PIN;
1991	2282	}
	2283	+
	2284	+ return 0;
1992	2285	}
1993	2286
1994		-static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1995		- int pin_num, struct regmap **regmap,
1996		- int reg, u8 bit)
	2287	+static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2288	+ int pin_num, struct regmap **regmap,
	2289	+ int reg, u8 bit)
1997	2290	{
1998	2291	struct rockchip_pinctrl *info = bank->drvdata;
1999	2292	int drv_num = (pin_num / 8);
..	..	@@ -2010,6 +2303,8 @@
2010	2303	bit = (pin_num % 8) 3;
2011	2304	else
2012	2305	bit = (pin_num % 8) 2;
	2306	+
	2307	+ return 0;
2013	2308	}
2014	2309
2015	2310	#define RK3528_DRV_BITS_PER_PIN 8
..	..	@@ -2020,9 +2315,9 @@
2020	2315	#define RK3528_DRV_GPIO3_OFFSET 0x20190
2021	2316	#define RK3528_DRV_GPIO4_OFFSET 0x101C0
2022	2317
2023		-static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2024		- int pin_num, struct regmap **regmap,
2025		- int reg, u8 bit)
	2318	+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2319	+ int pin_num, struct regmap **regmap,
	2320	+ int reg, u8 bit)
2026	2321	{
2027	2322	struct rockchip_pinctrl *info = bank->drvdata;
2028	2323
..	..	@@ -2056,6 +2351,8 @@
2056	2351	reg += ((pin_num / RK3528_DRV_PINS_PER_REG) 4);
2057	2352	*bit = pin_num % RK3528_DRV_PINS_PER_REG;
2058	2353	bit = RK3528_DRV_BITS_PER_PIN;
	2354	+
	2355	+ return 0;
2059	2356	}
2060	2357
2061	2358	#define RK3528_PULL_BITS_PER_PIN 2
..	..	@@ -2066,9 +2363,9 @@
2066	2363	#define RK3528_PULL_GPIO3_OFFSET 0x20230
2067	2364	#define RK3528_PULL_GPIO4_OFFSET 0x10240
2068	2365
2069		-static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2070		- int pin_num, struct regmap **regmap,
2071		- int reg, u8 bit)
	2366	+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2367	+ int pin_num, struct regmap **regmap,
	2368	+ int reg, u8 bit)
2072	2369	{
2073	2370	struct rockchip_pinctrl *info = bank->drvdata;
2074	2371
..	..	@@ -2102,6 +2399,8 @@
2102	2399	reg += ((pin_num / RK3528_PULL_PINS_PER_REG) 4);
2103	2400	*bit = pin_num % RK3528_PULL_PINS_PER_REG;
2104	2401	bit = RK3528_PULL_BITS_PER_PIN;
	2402	+
	2403	+ return 0;
2105	2404	}
2106	2405
2107	2406	#define RK3528_SMT_BITS_PER_PIN 1
..	..	@@ -2152,6 +2451,151 @@
2152	2451	return 0;
2153	2452	}
2154	2453
	2454	+#define RK3562_DRV_BITS_PER_PIN 8
	2455	+#define RK3562_DRV_PINS_PER_REG 2
	2456	+#define RK3562_DRV_GPIO0_OFFSET 0x20070
	2457	+#define RK3562_DRV_GPIO1_OFFSET 0x200
	2458	+#define RK3562_DRV_GPIO2_OFFSET 0x240
	2459	+#define RK3562_DRV_GPIO3_OFFSET 0x10280
	2460	+#define RK3562_DRV_GPIO4_OFFSET 0x102C0
	2461	+
	2462	+static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2463	+ int pin_num, struct regmap **regmap,
	2464	+ int reg, u8 bit)
	2465	+{
	2466	+ struct rockchip_pinctrl *info = bank->drvdata;
	2467	+
	2468	+ *regmap = info->regmap_base;
	2469	+ switch (bank->bank_num) {
	2470	+ case 0:
	2471	+ *reg = RK3562_DRV_GPIO0_OFFSET;
	2472	+ break;
	2473	+
	2474	+ case 1:
	2475	+ *reg = RK3562_DRV_GPIO1_OFFSET;
	2476	+ break;
	2477	+
	2478	+ case 2:
	2479	+ *reg = RK3562_DRV_GPIO2_OFFSET;
	2480	+ break;
	2481	+
	2482	+ case 3:
	2483	+ *reg = RK3562_DRV_GPIO3_OFFSET;
	2484	+ break;
	2485	+
	2486	+ case 4:
	2487	+ *reg = RK3562_DRV_GPIO4_OFFSET;
	2488	+ break;
	2489	+
	2490	+ default:
	2491	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2492	+ break;
	2493	+ }
	2494	+
	2495	+ reg += ((pin_num / RK3562_DRV_PINS_PER_REG) 4);
	2496	+ *bit = pin_num % RK3562_DRV_PINS_PER_REG;
	2497	+ bit = RK3562_DRV_BITS_PER_PIN;
	2498	+
	2499	+ return 0;
	2500	+}
	2501	+
	2502	+#define RK3562_PULL_BITS_PER_PIN 2
	2503	+#define RK3562_PULL_PINS_PER_REG 8
	2504	+#define RK3562_PULL_GPIO0_OFFSET 0x20020
	2505	+#define RK3562_PULL_GPIO1_OFFSET 0x80
	2506	+#define RK3562_PULL_GPIO2_OFFSET 0x90
	2507	+#define RK3562_PULL_GPIO3_OFFSET 0x100A0
	2508	+#define RK3562_PULL_GPIO4_OFFSET 0x100B0
	2509	+
	2510	+static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2511	+ int pin_num, struct regmap **regmap,
	2512	+ int reg, u8 bit)
	2513	+{
	2514	+ struct rockchip_pinctrl *info = bank->drvdata;
	2515	+
	2516	+ *regmap = info->regmap_base;
	2517	+ switch (bank->bank_num) {
	2518	+ case 0:
	2519	+ *reg = RK3562_PULL_GPIO0_OFFSET;
	2520	+ break;
	2521	+
	2522	+ case 1:
	2523	+ *reg = RK3562_PULL_GPIO1_OFFSET;
	2524	+ break;
	2525	+
	2526	+ case 2:
	2527	+ *reg = RK3562_PULL_GPIO2_OFFSET;
	2528	+ break;
	2529	+
	2530	+ case 3:
	2531	+ *reg = RK3562_PULL_GPIO3_OFFSET;
	2532	+ break;
	2533	+
	2534	+ case 4:
	2535	+ *reg = RK3562_PULL_GPIO4_OFFSET;
	2536	+ break;
	2537	+
	2538	+ default:
	2539	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2540	+ break;
	2541	+ }
	2542	+
	2543	+ reg += ((pin_num / RK3562_PULL_PINS_PER_REG) 4);
	2544	+ *bit = pin_num % RK3562_PULL_PINS_PER_REG;
	2545	+ bit = RK3562_PULL_BITS_PER_PIN;
	2546	+
	2547	+ return 0;
	2548	+}
	2549	+
	2550	+#define RK3562_SMT_BITS_PER_PIN 2
	2551	+#define RK3562_SMT_PINS_PER_REG 8
	2552	+#define RK3562_SMT_GPIO0_OFFSET 0x20030
	2553	+#define RK3562_SMT_GPIO1_OFFSET 0xC0
	2554	+#define RK3562_SMT_GPIO2_OFFSET 0xD0
	2555	+#define RK3562_SMT_GPIO3_OFFSET 0x100E0
	2556	+#define RK3562_SMT_GPIO4_OFFSET 0x100F0
	2557	+
	2558	+static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2559	+ int pin_num,
	2560	+ struct regmap **regmap,
	2561	+ int reg, u8 bit)
	2562	+{
	2563	+ struct rockchip_pinctrl *info = bank->drvdata;
	2564	+
	2565	+ *regmap = info->regmap_base;
	2566	+ switch (bank->bank_num) {
	2567	+ case 0:
	2568	+ *reg = RK3562_SMT_GPIO0_OFFSET;
	2569	+ break;
	2570	+
	2571	+ case 1:
	2572	+ *reg = RK3562_SMT_GPIO1_OFFSET;
	2573	+ break;
	2574	+
	2575	+ case 2:
	2576	+ *reg = RK3562_SMT_GPIO2_OFFSET;
	2577	+ break;
	2578	+
	2579	+ case 3:
	2580	+ *reg = RK3562_SMT_GPIO3_OFFSET;
	2581	+ break;
	2582	+
	2583	+ case 4:
	2584	+ *reg = RK3562_SMT_GPIO4_OFFSET;
	2585	+ break;
	2586	+
	2587	+ default:
	2588	+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
	2589	+ break;
	2590	+ }
	2591	+
	2592	+ reg += ((pin_num / RK3562_SMT_PINS_PER_REG) 4);
	2593	+ *bit = pin_num % RK3562_SMT_PINS_PER_REG;
	2594	+ bit = RK3562_SMT_BITS_PER_PIN;
	2595	+
	2596	+ return 0;
	2597	+}
	2598	+
2155	2599	#define RK3568_SR_PMU_OFFSET 0x60
2156	2600	#define RK3568_SR_GRF_OFFSET 0x0180
2157	2601	#define RK3568_SR_BANK_STRIDE 0x10
..	..	@@ -2186,9 +2630,9 @@
2186	2630	#define RK3568_PULL_PINS_PER_REG 8
2187	2631	#define RK3568_PULL_BANK_STRIDE 0x10
2188	2632
2189		-static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2190		- int pin_num, struct regmap **regmap,
2191		- int reg, u8 bit)
	2633	+static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2634	+ int pin_num, struct regmap **regmap,
	2635	+ int reg, u8 bit)
2192	2636	{
2193	2637	struct rockchip_pinctrl *info = bank->drvdata;
2194	2638
..	..	@@ -2209,6 +2653,8 @@
2209	2653	*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2210	2654	bit = RK3568_PULL_BITS_PER_PIN;
2211	2655	}
	2656	+
	2657	+ return 0;
2212	2658	}
2213	2659
2214	2660	#define RK3568_DRV_PMU_OFFSET 0x70
..	..	@@ -2217,9 +2663,9 @@
2217	2663	#define RK3568_DRV_PINS_PER_REG 2
2218	2664	#define RK3568_DRV_BANK_STRIDE 0x40
2219	2665
2220		-static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2221		- int pin_num, struct regmap **regmap,
2222		- int reg, u8 bit)
	2666	+static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2667	+ int pin_num, struct regmap **regmap,
	2668	+ int reg, u8 bit)
2223	2669	{
2224	2670	struct rockchip_pinctrl *info = bank->drvdata;
2225	2671
..	..	@@ -2246,6 +2692,197 @@
2246	2692	((bank->bank_num == 2 \|\| bank->bank_num == 3 \|\| bank->bank_num == 4) &&
2247	2693	(pin_num == 7 \|\| pin_num == 15 \|\| pin_num == 23 \|\| pin_num == 31)))
2248	2694	*bit -= RK3568_DRV_BITS_PER_PIN;
	2695	+
	2696	+ return 0;
	2697	+}
	2698	+
	2699	+#define RK3588_PMU1_IOC_REG (0x0000)
	2700	+#define RK3588_PMU2_IOC_REG (0x4000)
	2701	+#define RK3588_BUS_IOC_REG (0x8000)
	2702	+#define RK3588_VCCIO1_4_IOC_REG (0x9000)
	2703	+#define RK3588_VCCIO3_5_IOC_REG (0xA000)
	2704	+#define RK3588_VCCIO2_IOC_REG (0xB000)
	2705	+#define RK3588_VCCIO6_IOC_REG (0xC000)
	2706	+#define RK3588_EMMC_IOC_REG (0xD000)
	2707	+
	2708	+static const u32 rk3588_ds_regs[][2] = {
	2709	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
	2710	+ {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
	2711	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
	2712	+ {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
	2713	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
	2714	+ {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
	2715	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
	2716	+ {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
	2717	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
	2718	+ {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
	2719	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
	2720	+ {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
	2721	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
	2722	+ {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
	2723	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
	2724	+ {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
	2725	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
	2726	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
	2727	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
	2728	+ {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
	2729	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
	2730	+ {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
	2731	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
	2732	+ {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
	2733	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
	2734	+ {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
	2735	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
	2736	+ {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
	2737	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
	2738	+ {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
	2739	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
	2740	+ {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
	2741	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
	2742	+ {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
	2743	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
	2744	+ {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
	2745	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
	2746	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
	2747	+ {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
	2748	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
	2749	+};
	2750	+
	2751	+static const u32 rk3588_p_regs[][2] = {
	2752	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
	2753	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
	2754	+ {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
	2755	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
	2756	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
	2757	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
	2758	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
	2759	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
	2760	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
	2761	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
	2762	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120},
	2763	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
	2764	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
	2765	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
	2766	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
	2767	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
	2768	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
	2769	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
	2770	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
	2771	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
	2772	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
	2773	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
	2774	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
	2775	+};
	2776	+
	2777	+static const u32 rk3588_smt_regs[][2] = {
	2778	+ {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
	2779	+ {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
	2780	+ {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
	2781	+ {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
	2782	+ {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
	2783	+ {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
	2784	+ {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
	2785	+ {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
	2786	+ {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
	2787	+ {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
	2788	+ {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220},
	2789	+ {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
	2790	+ {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
	2791	+ {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
	2792	+ {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
	2793	+ {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
	2794	+ {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
	2795	+ {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
	2796	+ {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
	2797	+ {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
	2798	+ {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
	2799	+ {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
	2800	+ {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
	2801	+};
	2802	+
	2803	+#define RK3588_PULL_BITS_PER_PIN 2
	2804	+#define RK3588_PULL_PINS_PER_REG 8
	2805	+
	2806	+static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	2807	+ int pin_num, struct regmap **regmap,
	2808	+ int reg, u8 bit)
	2809	+{
	2810	+ struct rockchip_pinctrl *info = bank->drvdata;
	2811	+ u8 bank_num = bank->bank_num;
	2812	+ u32 pin = bank_num * 32 + pin_num;
	2813	+ int i;
	2814	+
	2815	+ for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
	2816	+ if (pin >= rk3588_p_regs[i][0]) {
	2817	+ *reg = rk3588_p_regs[i][1];
	2818	+ break;
	2819	+ }
	2820	+ BUG_ON(i == 0);
	2821	+ }
	2822	+
	2823	+ *regmap = info->regmap_base;
	2824	+ reg += ((pin - rk3588_p_regs[i][0]) / RK3588_PULL_PINS_PER_REG) 4;
	2825	+ *bit = pin_num % RK3588_PULL_PINS_PER_REG;
	2826	+ bit = RK3588_PULL_BITS_PER_PIN;
	2827	+
	2828	+ return 0;
	2829	+}
	2830	+
	2831	+#define RK3588_DRV_BITS_PER_PIN 4
	2832	+#define RK3588_DRV_PINS_PER_REG 4
	2833	+
	2834	+static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	2835	+ int pin_num, struct regmap **regmap,
	2836	+ int reg, u8 bit)
	2837	+{
	2838	+ struct rockchip_pinctrl *info = bank->drvdata;
	2839	+ u8 bank_num = bank->bank_num;
	2840	+ u32 pin = bank_num * 32 + pin_num;
	2841	+ int i;
	2842	+
	2843	+ for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
	2844	+ if (pin >= rk3588_ds_regs[i][0]) {
	2845	+ *reg = rk3588_ds_regs[i][1];
	2846	+ break;
	2847	+ }
	2848	+ BUG_ON(i == 0);
	2849	+ }
	2850	+
	2851	+ *regmap = info->regmap_base;
	2852	+ reg += ((pin - rk3588_ds_regs[i][0]) / RK3588_DRV_PINS_PER_REG) 4;
	2853	+ *bit = pin_num % RK3588_DRV_PINS_PER_REG;
	2854	+ bit = RK3588_DRV_BITS_PER_PIN;
	2855	+
	2856	+ return 0;
	2857	+}
	2858	+
	2859	+#define RK3588_SMT_BITS_PER_PIN 1
	2860	+#define RK3588_SMT_PINS_PER_REG 8
	2861	+
	2862	+static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	2863	+ int pin_num,
	2864	+ struct regmap **regmap,
	2865	+ int reg, u8 bit)
	2866	+{
	2867	+ struct rockchip_pinctrl *info = bank->drvdata;
	2868	+ u8 bank_num = bank->bank_num;
	2869	+ u32 pin = bank_num * 32 + pin_num;
	2870	+ int i;
	2871	+
	2872	+ for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
	2873	+ if (pin >= rk3588_smt_regs[i][0]) {
	2874	+ *reg = rk3588_smt_regs[i][1];
	2875	+ break;
	2876	+ }
	2877	+ BUG_ON(i == 0);
	2878	+ }
	2879	+
	2880	+ *regmap = info->regmap_base;
	2881	+ reg += ((pin - rk3588_smt_regs[i][0]) / RK3588_SMT_PINS_PER_REG) 4;
	2882	+ *bit = pin_num % RK3588_SMT_PINS_PER_REG;
	2883	+ bit = RK3588_SMT_BITS_PER_PIN;
	2884	+
	2885	+ return 0;
2249	2886	}
2250	2887
2251	2888	static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
..	..	@@ -2262,13 +2899,16 @@
2262	2899	{
2263	2900	struct rockchip_pinctrl *info = bank->drvdata;
2264	2901	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	2902	+ struct device *dev = info->dev;
2265	2903	struct regmap *regmap;
2266	2904	int reg, ret;
2267	2905	u32 data, temp, rmask_bits;
2268	2906	u8 bit;
2269	2907	int drv_type = bank->drv[pin_num / 8].drv_type;
2270	2908
2271		- ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2909	+ ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	2910	+ if (ret)
	2911	+ return ret;
2272	2912
2273	2913	switch (drv_type) {
2274	2914	case DRV_TYPE_IO_1V8_3V0_AUTO:
..	..	@@ -2307,7 +2947,7 @@
2307	2947	bit -= 16;
2308	2948	break;
2309	2949	default:
2310		- dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
	2950	+ dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2311	2951	bit, drv_type);
2312	2952	return -EINVAL;
2313	2953	}
..	..	@@ -2320,8 +2960,7 @@
2320	2960	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2321	2961	break;
2322	2962	default:
2323		- dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2324		- drv_type);
	2963	+ dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2325	2964	return -EINVAL;
2326	2965	}
2327	2966
..	..	@@ -2354,21 +2993,28 @@
2354	2993	{
2355	2994	struct rockchip_pinctrl *info = bank->drvdata;
2356	2995	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	2996	+ struct device *dev = info->dev;
2357	2997	struct regmap *regmap;
2358	2998	int reg, ret, i, err;
2359	2999	u32 data, rmask, rmask_bits, temp;
2360	3000	u8 bit;
2361	3001	int drv_type = bank->drv[pin_num / 8].drv_type;
2362	3002
2363		- dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
	3003	+ dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2364	3004	bank->bank_num, pin_num, strength);
2365	3005
2366		- ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2367		- if (ctrl->type == RV1126) {
	3006	+ ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3007	+ if (ret)
	3008	+ return ret;
	3009	+
	3010	+ if (ctrl->type == RV1126 \|\| ctrl->type == RK3588) {
2368	3011	rmask_bits = RV1126_DRV_BITS_PER_PIN;
2369	3012	ret = strength;
2370	3013	goto config;
2371		- } else if (ctrl->type == RK3568 \|\| ctrl->type == RK3528) {
	3014	+ } else if (ctrl->type == RV1106 \|\|
	3015	+ ctrl->type == RK3528 \|\|
	3016	+ ctrl->type == RK3562 \|\|
	3017	+ ctrl->type == RK3568) {
2372	3018	rmask_bits = RK3568_DRV_BITS_PER_PIN;
2373	3019	ret = (1 << (strength + 1)) - 1;
2374	3020	goto config;
..	..	@@ -2386,8 +3032,7 @@
2386	3032	}
2387	3033
2388	3034	if (ret < 0) {
2389		- dev_err(info->dev, "unsupported driver strength %d\n",
2390		- strength);
	3035	+ dev_err(dev, "unsupported driver strength %d\n", strength);
2391	3036	return ret;
2392	3037	}
2393	3038
..	..	@@ -2426,7 +3071,7 @@
2426	3071	bit -= 16;
2427	3072	break;
2428	3073	default:
2429		- dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
	3074	+ dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2430	3075	bit, drv_type);
2431	3076	return -EINVAL;
2432	3077	}
..	..	@@ -2438,8 +3083,7 @@
2438	3083	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2439	3084	break;
2440	3085	default:
2441		- dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2442		- drv_type);
	3086	+ dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2443	3087	return -EINVAL;
2444	3088	}
2445	3089
..	..	@@ -2508,6 +3152,7 @@
2508	3152	{
2509	3153	struct rockchip_pinctrl *info = bank->drvdata;
2510	3154	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3155	+ struct device *dev = info->dev;
2511	3156	struct regmap *regmap;
2512	3157	int reg, ret, pull_type;
2513	3158	u8 bit;
..	..	@@ -2517,7 +3162,9 @@
2517	3162	if (ctrl->type == RK3066B)
2518	3163	return PIN_CONFIG_BIAS_DISABLE;
2519	3164
2520		- ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3165	+ ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3166	+ if (ret)
	3167	+ return ret;
2521	3168
2522	3169	ret = regmap_read(regmap, reg, &data);
2523	3170	if (ret)
..	..	@@ -2530,6 +3177,7 @@
2530	3177	? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2531	3178	: PIN_CONFIG_BIAS_DISABLE;
2532	3179	case PX30:
	3180	+ case RV1106:
2533	3181	case RV1108:
2534	3182	case RV1126:
2535	3183	case RK1808:
..	..	@@ -2539,14 +3187,24 @@
2539	3187	case RK3368:
2540	3188	case RK3399:
2541	3189	case RK3528:
	3190	+ case RK3562:
2542	3191	case RK3568:
	3192	+ case RK3588:
2543	3193	pull_type = bank->pull_type[pin_num / 8];
2544	3194	data >>= bit;
2545	3195	data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
	3196	+ /*
	3197	+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
	3198	+ * where that pull up value becomes 3.
	3199	+ */
	3200	+ if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
	3201	+ if (data == 3)
	3202	+ data = 1;
	3203	+ }
2546	3204
2547	3205	return rockchip_pull_list[pull_type][data];
2548	3206	default:
2549		- dev_err(info->dev, "unsupported pinctrl type\n");
	3207	+ dev_err(dev, "unsupported pinctrl type\n");
2550	3208	return -EINVAL;
2551	3209	};
2552	3210	}
..	..	@@ -2556,19 +3214,21 @@
2556	3214	{
2557	3215	struct rockchip_pinctrl *info = bank->drvdata;
2558	3216	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3217	+ struct device *dev = info->dev;
2559	3218	struct regmap *regmap;
2560	3219	int reg, ret, i, pull_type;
2561	3220	u8 bit;
2562	3221	u32 data, rmask;
2563	3222
2564		- dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2565		- bank->bank_num, pin_num, pull);
	3223	+ dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2566	3224
2567	3225	/* rk3066b does support any pulls */
2568	3226	if (ctrl->type == RK3066B)
2569	3227	return pull ? -EINVAL : 0;
2570	3228
2571		- ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3229	+ ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
	3230	+ if (ret)
	3231	+ return ret;
2572	3232
2573	3233	switch (ctrl->type) {
2574	3234	case RK2928:
..	..	@@ -2579,6 +3239,7 @@
2579	3239	ret = regmap_write(regmap, reg, data);
2580	3240	break;
2581	3241	case PX30:
	3242	+ case RV1106:
2582	3243	case RV1108:
2583	3244	case RV1126:
2584	3245	case RK1808:
..	..	@@ -2588,7 +3249,9 @@
2588	3249	case RK3368:
2589	3250	case RK3399:
2590	3251	case RK3528:
	3252	+ case RK3562:
2591	3253	case RK3568:
	3254	+ case RK3588:
2592	3255	pull_type = bank->pull_type[pin_num / 8];
2593	3256	ret = -EINVAL;
2594	3257	for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
..	..	@@ -2599,7 +3262,7 @@
2599	3262	}
2600	3263	}
2601	3264	/*
2602		- * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
	3265	+ * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2603	3266	* where that pull up value becomes 3.
2604	3267	*/
2605	3268	if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
..	..	@@ -2608,8 +3271,7 @@
2608	3271	}
2609	3272
2610	3273	if (ret < 0) {
2611		- dev_err(info->dev, "unsupported pull setting %d\n",
2612		- pull);
	3274	+ dev_err(dev, "unsupported pull setting %d\n", pull);
2613	3275	return ret;
2614	3276	}
2615	3277
..	..	@@ -2621,32 +3283,11 @@
2621	3283	ret = regmap_update_bits(regmap, reg, rmask, data);
2622	3284	break;
2623	3285	default:
2624		- dev_err(info->dev, "unsupported pinctrl type\n");
	3286	+ dev_err(dev, "unsupported pinctrl type\n");
2625	3287	return -EINVAL;
2626	3288	}
2627	3289
2628	3290	return ret;
2629		-}
2630		-
2631		-#define RK3308_SCHMITT_PINS_PER_REG 8
2632		-#define RK3308_SCHMITT_BANK_STRIDE 16
2633		-#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
2634		-
2635		-static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2636		- int pin_num,
2637		- struct regmap **regmap,
2638		- int reg, u8 bit)
2639		-{
2640		- struct rockchip_pinctrl *info = bank->drvdata;
2641		-
2642		- *regmap = info->regmap_base;
2643		- *reg = RK3308_SCHMITT_GRF_OFFSET;
2644		-
2645		- reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
2646		- reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
2647		- *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
2648		-
2649		- return 0;
2650	3291	}
2651	3292
2652	3293	#define RK3328_SCHMITT_BITS_PER_PIN 1
..	..	@@ -2719,6 +3360,7 @@
2719	3360
2720	3361	data >>= bit;
2721	3362	switch (ctrl->type) {
	3363	+ case RK3562:
2722	3364	case RK3568:
2723	3365	return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2724	3366	default:
..	..	@@ -2733,12 +3375,13 @@
2733	3375	{
2734	3376	struct rockchip_pinctrl *info = bank->drvdata;
2735	3377	struct rockchip_pin_ctrl *ctrl = info->ctrl;
	3378	+ struct device *dev = info->dev;
2736	3379	struct regmap *regmap;
2737	3380	int reg, ret;
2738	3381	u8 bit;
2739	3382	u32 data, rmask;
2740	3383
2741		- dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
	3384	+ dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2742	3385	bank->bank_num, pin_num, enable);
2743	3386
2744	3387	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
..	..	@@ -2747,6 +3390,7 @@
2747	3390
2748	3391	/* enable the write to the equivalent lower bits */
2749	3392	switch (ctrl->type) {
	3393	+ case RK3562:
2750	3394	case RK3568:
2751	3395	data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2752	3396	rmask = data \| (data >> 16);
..	..	@@ -2881,10 +3525,11 @@
2881	3525	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2882	3526	const unsigned int *pins = info->groups[group].pins;
2883	3527	const struct rockchip_pin_config *data = info->groups[group].data;
	3528	+ struct device *dev = info->dev;
2884	3529	struct rockchip_pin_bank *bank;
2885	3530	int cnt, ret = 0;
2886	3531
2887		- dev_dbg(info->dev, "enable function %s group %s\n",
	3532	+ dev_dbg(dev, "enable function %s group %s\n",
2888	3533	info->functions[selector].name, info->groups[group].name);
2889	3534
2890	3535	/*
..	..	@@ -2932,6 +3577,7 @@
2932	3577	case RK3066B:
2933	3578	return pull ? false : true;
2934	3579	case PX30:
	3580	+ case RV1106:
2935	3581	case RV1108:
2936	3582	case RV1126:
2937	3583	case RK1808:
..	..	@@ -2941,11 +3587,31 @@
2941	3587	case RK3368:
2942	3588	case RK3399:
2943	3589	case RK3528:
	3590	+ case RK3562:
2944	3591	case RK3568:
	3592	+ case RK3588:
2945	3593	return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2946	3594	}
2947	3595
2948	3596	return false;
	3597	+}
	3598	+
	3599	+static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
	3600	+ unsigned int pin, u32 param, u32 arg)
	3601	+{
	3602	+ struct rockchip_pin_deferred *cfg;
	3603	+
	3604	+ cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
	3605	+ if (!cfg)
	3606	+ return -ENOMEM;
	3607	+
	3608	+ cfg->pin = pin;
	3609	+ cfg->param = param;
	3610	+ cfg->arg = arg;
	3611	+
	3612	+ list_add_tail(&cfg->head, &bank->deferred_pins);
	3613	+
	3614	+ return 0;
2949	3615	}
2950	3616
2951	3617	/* set the pin config settings for a specified pin */
..	..	@@ -2963,6 +3629,25 @@
2963	3629	for (i = 0; i < num_configs; i++) {
2964	3630	param = pinconf_to_config_param(configs[i]);
2965	3631	arg = pinconf_to_config_argument(configs[i]);
	3632	+
	3633	+ if (param == PIN_CONFIG_OUTPUT \|\| param == PIN_CONFIG_INPUT_ENABLE) {
	3634	+ /*
	3635	+ * Check for gpio driver not being probed yet.
	3636	+ * The lock makes sure that either gpio-probe has completed
	3637	+ * or the gpio driver hasn't probed yet.
	3638	+ */
	3639	+ mutex_lock(&bank->deferred_lock);
	3640	+ if (!gpio \|\| !gpio->direction_output) {
	3641	+ rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
	3642	+ arg);
	3643	+ mutex_unlock(&bank->deferred_lock);
	3644	+ if (rc)
	3645	+ return rc;
	3646	+
	3647	+ break;
	3648	+ }
	3649	+ mutex_unlock(&bank->deferred_lock);
	3650	+ }
2966	3651
2967	3652	switch (param) {
2968	3653	case PIN_CONFIG_BIAS_DISABLE:
..	..	@@ -2989,10 +3674,8 @@
2989	3674	case PIN_CONFIG_OUTPUT:
2990	3675	rc = rockchip_set_mux(bank, pin - bank->pin_base,
2991	3676	RK_FUNC_GPIO);
2992		- if (rc != RK_FUNC_GPIO) {
2993		- dev_err(info->dev, "pin-%d fail to mux to gpio, %d\n", pin, rc);
	3677	+ if (rc != RK_FUNC_GPIO)
2994	3678	return -EINVAL;
2995		- }
2996	3679
2997	3680	rc = gpio->direction_output(gpio, pin - bank->pin_base,
2998	3681	arg);
..	..	@@ -3077,13 +3760,13 @@
3077	3760	break;
3078	3761	case PIN_CONFIG_OUTPUT:
3079	3762	rc = rockchip_get_mux(bank, pin - bank->pin_base);
3080		- if (rc != 0)
	3763	+ if (rc != RK_FUNC_GPIO)
3081	3764	return -EINVAL;
3082	3765
3083		- /* 0 for output, 1 for input */
3084		- rc = gpio->get_direction(gpio, pin - bank->pin_base);
3085		- if (rc)
3086		- return -EINVAL;
	3766	+ if (!gpio \|\| !gpio->get) {
	3767	+ arg = 0;
	3768	+ break;
	3769	+ }
3087	3770
3088	3771	rc = gpio->get(gpio, pin - bank->pin_base);
3089	3772	if (rc < 0)
..	..	@@ -3143,24 +3826,13 @@
3143	3826	{},
3144	3827	};
3145	3828
3146		-static bool is_function_node(const struct device_node *np)
3147		-{
3148		- if (of_match_node(rockchip_bank_match, np))
3149		- return false;
3150		-
3151		- if (!strncmp(np->name, "pcfg", 4))
3152		- return false;
3153		-
3154		- return true;
3155		-}
3156		-
3157	3829	static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
3158	3830	struct device_node *np)
3159	3831	{
3160	3832	struct device_node *child;
3161	3833
3162	3834	for_each_child_of_node(np, child) {
3163		- if (!is_function_node(child))
	3835	+ if (of_match_node(rockchip_bank_match, child))
3164	3836	continue;
3165	3837
3166	3838	info->nfunctions++;
..	..	@@ -3173,6 +3845,7 @@
3173	3845	struct rockchip_pinctrl *info,
3174	3846	u32 index)
3175	3847	{
	3848	+ struct device *dev = info->dev;
3176	3849	struct rockchip_pin_bank *bank;
3177	3850	int size;
3178	3851	const __be32 *list;
..	..	@@ -3180,7 +3853,7 @@
3180	3853	int i, j;
3181	3854	int ret;
3182	3855
3183		- dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
	3856	+ dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3184	3857
3185	3858	/* Initialise group */
3186	3859	grp->name = np->name;
..	..	@@ -3192,19 +3865,13 @@
3192	3865	list = of_get_property(np, "rockchip,pins", &size);
3193	3866	/* we do not check return since it's safe node passed down */
3194	3867	size /= sizeof(*list);
3195		- if (!size \|\| size % 4) {
3196		- dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
3197		- return -EINVAL;
3198		- }
	3868	+ if (!size \|\| size % 4)
	3869	+ return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
3199	3870
3200	3871	grp->npins = size / 4;
3201	3872
3202		- grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
3203		- GFP_KERNEL);
3204		- grp->data = devm_kcalloc(info->dev,
3205		- grp->npins,
3206		- sizeof(struct rockchip_pin_config),
3207		- GFP_KERNEL);
	3873	+ grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
	3874	+ grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3208	3875	if (!grp->pins \|\| !grp->data)
3209	3876	return -ENOMEM;
3210	3877
..	..	@@ -3227,6 +3894,7 @@
3227	3894	np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
3228	3895	ret = pinconf_generic_parse_dt_config(np_config, NULL,
3229	3896	&grp->data[j].configs, &grp->data[j].nconfigs);
	3897	+ of_node_put(np_config);
3230	3898	if (ret)
3231	3899	return ret;
3232	3900	}
..	..	@@ -3238,6 +3906,7 @@
3238	3906	struct rockchip_pinctrl *info,
3239	3907	u32 index)
3240	3908	{
	3909	+ struct device *dev = info->dev;
3241	3910	struct device_node *child;
3242	3911	struct rockchip_pmx_func *func;
3243	3912	struct rockchip_pin_group *grp;
..	..	@@ -3245,7 +3914,7 @@
3245	3914	static u32 grp_index;
3246	3915	u32 i = 0;
3247	3916
3248		- dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
	3917	+ dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3249	3918
3250	3919	func = &info->functions[index];
3251	3920
..	..	@@ -3255,8 +3924,7 @@
3255	3924	if (func->ngroups <= 0)
3256	3925	return 0;
3257	3926
3258		- func->groups = devm_kcalloc(info->dev,
3259		- func->ngroups, sizeof(char *), GFP_KERNEL);
	3927	+ func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3260	3928	if (!func->groups)
3261	3929	return -ENOMEM;
3262	3930
..	..	@@ -3284,32 +3952,26 @@
3284	3952
3285	3953	rockchip_pinctrl_child_count(info, np);
3286	3954
3287		- dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
3288		- dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
	3955	+ dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
	3956	+ dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3289	3957
3290		- info->functions = devm_kcalloc(dev,
3291		- info->nfunctions,
3292		- sizeof(struct rockchip_pmx_func),
3293		- GFP_KERNEL);
	3958	+ info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3294	3959	if (!info->functions)
3295	3960	return -ENOMEM;
3296	3961
3297		- info->groups = devm_kcalloc(dev,
3298		- info->ngroups,
3299		- sizeof(struct rockchip_pin_group),
3300		- GFP_KERNEL);
	3962	+ info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3301	3963	if (!info->groups)
3302	3964	return -ENOMEM;
3303	3965
3304	3966	i = 0;
3305	3967
3306	3968	for_each_child_of_node(np, child) {
3307		- if (!is_function_node(child))
	3969	+ if (of_match_node(rockchip_bank_match, child))
3308	3970	continue;
3309	3971
3310	3972	ret = rockchip_pinctrl_parse_functions(child, info, i++);
3311	3973	if (ret) {
3312		- dev_err(&pdev->dev, "failed to parse function\n");
	3974	+ dev_err(dev, "failed to parse function\n");
3313	3975	of_node_put(child);
3314	3976	return ret;
3315	3977	}
..	..	@@ -3324,6 +3986,7 @@
3324	3986	struct pinctrl_desc *ctrldesc = &info->pctl;
3325	3987	struct pinctrl_pin_desc pindesc, pdesc;
3326	3988	struct rockchip_pin_bank *pin_bank;
	3989	+ struct device *dev = &pdev->dev;
3327	3990	int pin, bank, ret;
3328	3991	int k;
3329	3992
..	..	@@ -3333,9 +3996,7 @@
3333	3996	ctrldesc->pmxops = &rockchip_pmx_ops;
3334	3997	ctrldesc->confops = &rockchip_pinconf_ops;
3335	3998
3336		- pindesc = devm_kcalloc(&pdev->dev,
3337		- info->ctrl->nr_pins, sizeof(*pindesc),
3338		- GFP_KERNEL);
	3999	+ pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3339	4000	if (!pindesc)
3340	4001	return -ENOMEM;
3341	4002
..	..	@@ -3351,41 +4012,24 @@
3351	4012	pin_bank->name, pin);
3352	4013	pdesc++;
3353	4014	}
	4015	+
	4016	+ INIT_LIST_HEAD(&pin_bank->deferred_pins);
	4017	+ mutex_init(&pin_bank->deferred_lock);
3354	4018	}
3355	4019
3356	4020	ret = rockchip_pinctrl_parse_dt(pdev, info);
3357	4021	if (ret)
3358	4022	return ret;
3359	4023
3360		- info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3361		- if (IS_ERR(info->pctl_dev)) {
3362		- dev_err(&pdev->dev, "could not register pinctrl driver\n");
3363		- return PTR_ERR(info->pctl_dev);
3364		- }
	4024	+ info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
	4025	+ if (IS_ERR(info->pctl_dev))
	4026	+ return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3365	4027
3366	4028	return 0;
3367	4029	}
3368	4030
3369	4031	static const struct of_device_id rockchip_pinctrl_dt_match[];
3370		-
3371		-/* Ctrl data specially handle */
3372		-static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl)
3373		-{
3374		- /*
3375		- * Special for rk3308b, where we need to replace the recalced
3376		- * and routed arrays.
3377		- */
3378		- if (soc_is_rk3308b()) {
3379		- ctrl->iomux_recalced = rk3308b_mux_recalced_data;
3380		- ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data);
3381		- ctrl->iomux_routes = rk3308b_mux_route_data;
3382		- ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data);
3383		-
3384		- }
3385		-
3386		- return 0;
3387		-}
3388		-
	4032	+static struct rockchip_pin_bank rk3308bs_pin_banks[];
3389	4033	static struct rockchip_pin_bank px30s_pin_banks[];
3390	4034
3391	4035	/* retrieve the soc specific data */
..	..	@@ -3393,22 +4037,19 @@
3393	4037	struct rockchip_pinctrl *d,
3394	4038	struct platform_device *pdev)
3395	4039	{
	4040	+ struct device *dev = &pdev->dev;
	4041	+ struct device_node *node = dev->of_node;
3396	4042	const struct of_device_id *match;
3397		- struct device_node *node = pdev->dev.of_node;
3398	4043	struct rockchip_pin_ctrl *ctrl;
3399	4044	struct rockchip_pin_bank *bank;
3400	4045	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3401	4046
3402	4047	match = of_match_node(rockchip_pinctrl_dt_match, node);
3403	4048	ctrl = (struct rockchip_pin_ctrl *)match->data;
	4049	+ if (IS_ENABLED(CONFIG_CPU_RK3308) && soc_is_rk3308bs())
	4050	+ ctrl->pin_banks = rk3308bs_pin_banks;
3404	4051	if (IS_ENABLED(CONFIG_CPU_PX30) && soc_is_px30s())
3405	4052	ctrl->pin_banks = px30s_pin_banks;
3406		-
3407		- /* Ctrl data re-initialize for some Socs */
3408		- if (ctrl->ctrl_data_re_init) {
3409		- if (ctrl->ctrl_data_re_init(ctrl))
3410		- return NULL;
3411		- }
3412	4053
3413	4054	grf_offs = ctrl->grf_mux_offset;
3414	4055	pmu_offs = ctrl->pmu_mux_offset;
..	..	@@ -3455,7 +4096,7 @@
3455	4096	drv_pmu_offs : drv_grf_offs;
3456	4097	}
3457	4098
3458		- dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
	4099	+ dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3459	4100	i, j, iom->offset, drv->offset);
3460	4101
3461	4102	/*
..	..	@@ -3562,60 +4203,56 @@
3562	4203
3563	4204	/* SoC data specially handle */
3564	4205
3565		-/* rk3308b SoC data initialize */
3566		-#define RK3308B_GRF_SOC_CON13 0x608
3567		-#define RK3308B_GRF_SOC_CON15 0x610
	4206	+/* rk3308 SoC data initialize */
	4207	+#define RK3308_GRF_SOC_CON13 0x608
	4208	+#define RK3308_GRF_SOC_CON15 0x610
3568	4209
3569		-/* RK3308B_GRF_SOC_CON13 */
3570		-#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) \| BIT(10))
3571		-#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
3572		-#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
	4210	+/* RK3308_GRF_SOC_CON13 */
	4211	+#define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) \| BIT(10))
	4212	+#define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
	4213	+#define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
3573	4214
3574		-/* RK3308B_GRF_SOC_CON15 */
3575		-#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) \| BIT(11))
3576		-#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
3577		-#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
	4215	+/* RK3308_GRF_SOC_CON15 */
	4216	+#define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) \| BIT(11))
	4217	+#define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) \| BIT(7))
	4218	+#define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) \| BIT(3))
3578	4219
3579		-static int rk3308b_soc_data_init(struct rockchip_pinctrl *info)
	4220	+static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
3580	4221	{
3581	4222	int ret;
3582	4223
3583	4224	/*
3584	4225	* Enable the special ctrl of selected sources.
3585	4226	*/
3586		- if (soc_is_rk3308b()) {
3587		- ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13,
3588		- RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL \|
3589		- RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL \|
3590		- RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL);
3591		- if (ret)
3592		- return ret;
3593	4227
3594		- ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15,
3595		- RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL \|
3596		- RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL \|
3597		- RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL);
3598		- if (ret)
3599		- return ret;
3600		- }
	4228	+ ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
	4229	+ RK3308_GRF_I2C3_IOFUNC_SRC_CTRL \|
	4230	+ RK3308_GRF_GPIO2A3_SEL_SRC_CTRL \|
	4231	+ RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
	4232	+ if (ret)
	4233	+ return ret;
3601	4234
3602		- return 0;
	4235	+ ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
	4236	+ RK3308_GRF_GPIO2C0_SEL_SRC_CTRL \|
	4237	+ RK3308_GRF_GPIO3B3_SEL_SRC_CTRL \|
	4238	+ RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
	4239	+
	4240	+ return ret;
	4241	+
3603	4242	}
3604	4243
3605	4244	static int rockchip_pinctrl_probe(struct platform_device *pdev)
3606	4245	{
3607	4246	struct rockchip_pinctrl *info;
3608	4247	struct device *dev = &pdev->dev;
	4248	+ struct device_node np = dev->of_node, node;
3609	4249	struct rockchip_pin_ctrl *ctrl;
3610		- struct device_node np = pdev->dev.of_node, node;
3611	4250	struct resource *res;
3612	4251	void __iomem *base;
3613	4252	int ret;
3614	4253
3615		- if (!dev->of_node) {
3616		- dev_err(dev, "device tree node not found\n");
3617		- return -ENODEV;
3618		- }
	4254	+ if (!dev->of_node)
	4255	+ return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
3619	4256
3620	4257	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3621	4258	if (!info)
..	..	@@ -3624,44 +4261,39 @@
3624	4261	info->dev = dev;
3625	4262
3626	4263	ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3627		- if (!ctrl) {
3628		- dev_err(dev, "driver data not available\n");
3629		- return -EINVAL;
3630		- }
	4264	+ if (!ctrl)
	4265	+ return dev_err_probe(dev, -EINVAL, "driver data not available\n");
3631	4266	info->ctrl = ctrl;
3632	4267
3633	4268	node = of_parse_phandle(np, "rockchip,grf", 0);
3634	4269	if (node) {
3635	4270	info->regmap_base = syscon_node_to_regmap(node);
	4271	+ of_node_put(node);
3636	4272	if (IS_ERR(info->regmap_base))
3637	4273	return PTR_ERR(info->regmap_base);
3638	4274	} else {
3639		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3640		- base = devm_ioremap_resource(&pdev->dev, res);
	4275	+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
3641	4276	if (IS_ERR(base))
3642	4277	return PTR_ERR(base);
3643	4278
3644	4279	rockchip_regmap_config.max_register = resource_size(res) - 4;
3645	4280	rockchip_regmap_config.name = "rockchip,pinctrl";
3646		- info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3647		- &rockchip_regmap_config);
	4281	+ info->regmap_base =
	4282	+ devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3648	4283
3649	4284	/* to check for the old dt-bindings */
3650	4285	info->reg_size = resource_size(res);
3651	4286
3652	4287	/* Honor the old binding, with pull registers as 2nd resource */
3653	4288	if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3654		- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3655		- base = devm_ioremap_resource(&pdev->dev, res);
	4289	+ base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
3656	4290	if (IS_ERR(base))
3657	4291	return PTR_ERR(base);
3658	4292
3659		- rockchip_regmap_config.max_register =
3660		- resource_size(res) - 4;
	4293	+ rockchip_regmap_config.max_register = resource_size(res) - 4;
3661	4294	rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3662		- info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3663		- base,
3664		- &rockchip_regmap_config);
	4295	+ info->regmap_pull =
	4296	+ devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3665	4297	}
3666	4298	}
3667	4299
..	..	@@ -3669,13 +4301,13 @@
3669	4301	node = of_parse_phandle(np, "rockchip,pmu", 0);
3670	4302	if (node) {
3671	4303	info->regmap_pmu = syscon_node_to_regmap(node);
	4304	+ of_node_put(node);
3672	4305	if (IS_ERR(info->regmap_pmu))
3673	4306	return PTR_ERR(info->regmap_pmu);
3674	4307	}
3675	4308
3676		- /* Special handle for some Socs */
3677		- if (ctrl->soc_data_init) {
3678		- ret = ctrl->soc_data_init(info);
	4309	+ if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) {
	4310	+ ret = rk3308_soc_data_init(info);
3679	4311	if (ret)
3680	4312	return ret;
3681	4313	}
..	..	@@ -3685,16 +4317,49 @@
3685	4317	return ret;
3686	4318
3687	4319	platform_set_drvdata(pdev, info);
	4320	+ g_pctldev = info->pctl_dev;
3688	4321
3689		- ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
3690		- if (ret) {
3691		- dev_err(&pdev->dev, "failed to register gpio device\n");
3692		- return ret;
3693		- }
	4322	+ ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
	4323	+ if (ret)
	4324	+ return dev_err_probe(dev, ret, "failed to register gpio device\n");
	4325	+
3694	4326	dev_info(dev, "probed %s\n", dev_name(dev));
3695	4327
3696	4328	return 0;
3697	4329	}
	4330	+
	4331	+static int rockchip_pinctrl_remove(struct platform_device *pdev)
	4332	+{
	4333	+ struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
	4334	+ struct rockchip_pin_bank *bank;
	4335	+ struct rockchip_pin_deferred *cfg;
	4336	+ int i;
	4337	+
	4338	+ g_pctldev = NULL;
	4339	+ of_platform_depopulate(&pdev->dev);
	4340	+
	4341	+ for (i = 0; i < info->ctrl->nr_banks; i++) {
	4342	+ bank = &info->ctrl->pin_banks[i];
	4343	+
	4344	+ mutex_lock(&bank->deferred_lock);
	4345	+ while (!list_empty(&bank->deferred_pins)) {
	4346	+ cfg = list_first_entry(&bank->deferred_pins,
	4347	+ struct rockchip_pin_deferred, head);
	4348	+ list_del(&cfg->head);
	4349	+ kfree(cfg);
	4350	+ }
	4351	+ mutex_unlock(&bank->deferred_lock);
	4352	+ }
	4353	+
	4354	+ return 0;
	4355	+}
	4356	+
	4357	+static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
	4358	+ S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
	4359	+ S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4360	+ S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4361	+ S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
	4362	+};
3698	4363
3699	4364	static struct rockchip_pin_bank px30_pin_banks[] = {
3700	4365	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
..	..	@@ -3719,13 +4384,6 @@
3719	4384	),
3720	4385	};
3721	4386
3722		-static struct rockchip_pin_bank px30s_pin_banks[] __maybe_unused = {
3723		- PX30S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, DRV_TYPE_IO_SMIC),
3724		- PX30S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3725		- PX30S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3726		- PX30S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, DRV_TYPE_IO_SMIC),
3727		-};
3728		-
3729	4387	static struct rockchip_pin_ctrl px30_pin_ctrl __maybe_unused = {
3730	4388	.pin_banks = px30_pin_banks,
3731	4389	.nr_banks = ARRAY_SIZE(px30_pin_banks),
..	..	@@ -3739,6 +4397,48 @@
3739	4397	.drv_calc_reg = px30_calc_drv_reg_and_bit,
3740	4398	.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3741	4399	.slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
	4400	+};
	4401	+
	4402	+static struct rockchip_pin_bank rv1106_pin_banks[] = {
	4403	+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
	4404	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4405	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4406	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU,
	4407	+ IOMUX_WIDTH_4BIT \| IOMUX_SOURCE_PMU),
	4408	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4409	+ IOMUX_WIDTH_4BIT,
	4410	+ IOMUX_WIDTH_4BIT,
	4411	+ IOMUX_WIDTH_4BIT,
	4412	+ IOMUX_WIDTH_4BIT,
	4413	+ 0, 0x08, 0x10, 0x18),
	4414	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4415	+ IOMUX_WIDTH_4BIT,
	4416	+ IOMUX_WIDTH_4BIT,
	4417	+ IOMUX_WIDTH_4BIT,
	4418	+ IOMUX_WIDTH_4BIT,
	4419	+ 0x10020, 0x10028, 0, 0),
	4420	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4421	+ IOMUX_WIDTH_4BIT,
	4422	+ IOMUX_WIDTH_4BIT,
	4423	+ IOMUX_WIDTH_4BIT,
	4424	+ IOMUX_WIDTH_4BIT,
	4425	+ 0x20040, 0x20048, 0x20050, 0x20058),
	4426	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4",
	4427	+ IOMUX_WIDTH_4BIT,
	4428	+ IOMUX_WIDTH_4BIT,
	4429	+ IOMUX_WIDTH_4BIT,
	4430	+ 0,
	4431	+ 0x30000, 0x30008, 0x30010, 0),
	4432	+};
	4433	+
	4434	+static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
	4435	+ .pin_banks = rv1106_pin_banks,
	4436	+ .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
	4437	+ .label = "RV1106-GPIO",
	4438	+ .type = RV1106,
	4439	+ .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
	4440	+ .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
	4441	+ .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
3742	4442	};
3743	4443
3744	4444	static struct rockchip_pin_bank rv1108_pin_banks[] = {
..	..	@@ -4011,6 +4711,14 @@
4011	4711	.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4012	4712	};
4013	4713
	4714	+static struct rockchip_pin_bank rk3308bs_pin_banks[] __maybe_unused = {
	4715	+ S_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4716	+ S_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4717	+ S_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4718	+ S_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4719	+ S_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, DRV_TYPE_IO_SMIC),
	4720	+};
	4721	+
4014	4722	static struct rockchip_pin_bank rk3308_pin_banks[] = {
4015	4723	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4016	4724	IOMUX_WIDTH_2BIT,
..	..	@@ -4044,11 +4752,10 @@
4044	4752	.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4045	4753	.iomux_routes = rk3308_mux_route_data,
4046	4754	.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4047		- .ctrl_data_re_init = rk3308b_ctrl_data_re_init,
4048		- .soc_data_init = rk3308b_soc_data_init,
4049	4755	.pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4050	4756	.drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4051	4757	.schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
	4758	+ .slew_rate_calc_reg = rk3308_calc_slew_rate_reg_and_bit,
4052	4759	};
4053	4760
4054	4761	static struct rockchip_pin_bank rk3328_pin_banks[] = {
..	..	@@ -4213,6 +4920,49 @@
4213	4920	.schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
4214	4921	};
4215	4922
	4923	+static struct rockchip_pin_bank rk3562_pin_banks[] = {
	4924	+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
	4925	+ IOMUX_WIDTH_4BIT,
	4926	+ IOMUX_WIDTH_4BIT,
	4927	+ IOMUX_WIDTH_4BIT,
	4928	+ IOMUX_WIDTH_4BIT,
	4929	+ 0x20000, 0x20008, 0x20010, 0x20018),
	4930	+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
	4931	+ IOMUX_WIDTH_4BIT,
	4932	+ IOMUX_WIDTH_4BIT,
	4933	+ IOMUX_WIDTH_4BIT,
	4934	+ IOMUX_WIDTH_4BIT,
	4935	+ 0, 0x08, 0x10, 0x18),
	4936	+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
	4937	+ IOMUX_WIDTH_4BIT,
	4938	+ IOMUX_WIDTH_4BIT,
	4939	+ IOMUX_WIDTH_4BIT,
	4940	+ IOMUX_WIDTH_4BIT,
	4941	+ 0x20, 0, 0, 0),
	4942	+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
	4943	+ IOMUX_WIDTH_4BIT,
	4944	+ IOMUX_WIDTH_4BIT,
	4945	+ IOMUX_WIDTH_4BIT,
	4946	+ IOMUX_WIDTH_4BIT,
	4947	+ 0x10040, 0x10048, 0x10050, 0x10058),
	4948	+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
	4949	+ IOMUX_WIDTH_4BIT,
	4950	+ IOMUX_WIDTH_4BIT,
	4951	+ 0,
	4952	+ 0,
	4953	+ 0x10060, 0x10068, 0, 0),
	4954	+};
	4955	+
	4956	+static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
	4957	+ .pin_banks = rk3562_pin_banks,
	4958	+ .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
	4959	+ .label = "RK3562-GPIO",
	4960	+ .type = RK3562,
	4961	+ .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
	4962	+ .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
	4963	+ .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
	4964	+};
	4965	+
4216	4966	static struct rockchip_pin_bank rk3568_pin_banks[] = {
4217	4967	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU \| IOMUX_WIDTH_4BIT,
4218	4968	IOMUX_SOURCE_PMU \| IOMUX_WIDTH_4BIT,
..	..	@@ -4253,12 +5003,39 @@
4253	5003	.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4254	5004	};
4255	5005
	5006	+static struct rockchip_pin_bank rk3588_pin_banks[] = {
	5007	+ RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
	5008	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5009	+ RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
	5010	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5011	+ RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
	5012	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5013	+ RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
	5014	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5015	+ RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
	5016	+ IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
	5017	+};
	5018	+
	5019	+static struct rockchip_pin_ctrl rk3588_pin_ctrl __maybe_unused = {
	5020	+ .pin_banks = rk3588_pin_banks,
	5021	+ .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
	5022	+ .label = "RK3588-GPIO",
	5023	+ .type = RK3588,
	5024	+ .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
	5025	+ .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
	5026	+ .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
	5027	+};
	5028	+
4256	5029	static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4257	5030	#ifdef CONFIG_CPU_PX30
4258	5031	{ .compatible = "rockchip,px30-pinctrl",
4259	5032	.data = &px30_pin_ctrl },
4260	5033	#endif
4261		-#ifdef CONFIG_CPU_RV110X
	5034	+#ifdef CONFIG_CPU_RV1106
	5035	+ { .compatible = "rockchip,rv1106-pinctrl",
	5036	+ .data = &rv1106_pin_ctrl },
	5037	+#endif
	5038	+#ifdef CONFIG_CPU_RV1108
4262	5039	{ .compatible = "rockchip,rv1108-pinctrl",
4263	5040	.data = &rv1108_pin_ctrl },
4264	5041	#endif
..	..	@@ -4320,15 +5097,24 @@
4320	5097	{ .compatible = "rockchip,rk3528-pinctrl",
4321	5098	.data = &rk3528_pin_ctrl },
4322	5099	#endif
	5100	+#ifdef CONFIG_CPU_RK3562
	5101	+ { .compatible = "rockchip,rk3562-pinctrl",
	5102	+ .data = &rk3562_pin_ctrl },
	5103	+#endif
4323	5104	#ifdef CONFIG_CPU_RK3568
4324	5105	{ .compatible = "rockchip,rk3568-pinctrl",
4325	5106	.data = &rk3568_pin_ctrl },
	5107	+#endif
	5108	+#ifdef CONFIG_CPU_RK3588
	5109	+ { .compatible = "rockchip,rk3588-pinctrl",
	5110	+ .data = &rk3588_pin_ctrl },
4326	5111	#endif
4327	5112	{},
4328	5113	};
4329	5114
4330	5115	static struct platform_driver rockchip_pinctrl_driver = {
4331	5116	.probe = rockchip_pinctrl_probe,
	5117	+ .remove = rockchip_pinctrl_remove,
4332	5118	.driver = {
4333	5119	.name = "rockchip-pinctrl",
4334	5120	.pm = &rockchip_pinctrl_dev_pm_ops,
..	..	@@ -4348,6 +5134,103 @@
4348	5134	}
4349	5135	module_exit(rockchip_pinctrl_drv_unregister);
4350	5136
	5137	+/**
	5138	+ * rk_iomux_set - set the rockchip iomux by pin number.
	5139	+ *
	5140	+ * @bank: the gpio bank index, from 0 to the max bank num.
	5141	+ * @pin: the gpio pin index, from 0 to 31.
	5142	+ * @mux: the pointer to store mux value.
	5143	+ *
	5144	+ * Return 0 if set success, else return error code.
	5145	+ */
	5146	+int rk_iomux_set(int bank, int pin, int mux)
	5147	+{
	5148	+ struct pinctrl_dev *pctldev = g_pctldev;
	5149	+ struct rockchip_pinctrl *info;
	5150	+ struct rockchip_pin_bank *gpio;
	5151	+ struct rockchip_pin_group *grp = NULL;
	5152	+ struct rockchip_pin_config *cfg = NULL;
	5153	+ int i, j, ret;
	5154	+
	5155	+ if (!g_pctldev)
	5156	+ return -ENODEV;
	5157	+
	5158	+ info = pinctrl_dev_get_drvdata(pctldev);
	5159	+ if (bank >= info->ctrl->nr_banks)
	5160	+ return -EINVAL;
	5161	+
	5162	+ if (pin > 31 \|\| pin < 0)
	5163	+ return -EINVAL;
	5164	+
	5165	+ gpio = &info->ctrl->pin_banks[bank];
	5166	+
	5167	+ mutex_lock(&iomux_lock);
	5168	+ for (i = 0; i < info->ngroups; i++) {
	5169	+ grp = &info->groups[i];
	5170	+ for (j = 0; j < grp->npins; i++) {
	5171	+ if (grp->pins[i] == (gpio->pin_base + pin)) {
	5172	+ cfg = grp->data;
	5173	+ break;
	5174	+ }
	5175	+ }
	5176	+ }
	5177	+
	5178	+ ret = rockchip_set_mux(gpio, pin, mux);
	5179	+ if (ret) {
	5180	+ dev_err(info->dev, "mux GPIO%d-%d %d fail\n", bank, pin, mux);
	5181	+ goto out;
	5182	+ }
	5183	+
	5184	+ if (cfg && (cfg->func != mux))
	5185	+ cfg->func = mux;
	5186	+
	5187	+out:
	5188	+ mutex_unlock(&iomux_lock);
	5189	+
	5190	+ return ret;
	5191	+}
	5192	+EXPORT_SYMBOL_GPL(rk_iomux_set);
	5193	+
	5194	+/**
	5195	+ * rk_iomux_get - get the rockchip iomux by pin number.
	5196	+ *
	5197	+ * @bank: the gpio bank index, from 0 to the max bank num.
	5198	+ * @pin: the gpio pin index, from 0 to 31.
	5199	+ * @mux: the pointer to store mux value.
	5200	+ *
	5201	+ * Return 0 if get success, else return error code.
	5202	+ */
	5203	+int rk_iomux_get(int bank, int pin, int *mux)
	5204	+{
	5205	+ struct pinctrl_dev *pctldev = g_pctldev;
	5206	+ struct rockchip_pinctrl *info;
	5207	+ struct rockchip_pin_bank *gpio;
	5208	+ int ret;
	5209	+
	5210	+ if (!g_pctldev)
	5211	+ return -ENODEV;
	5212	+ if (!mux)
	5213	+ return -EINVAL;
	5214	+
	5215	+ info = pinctrl_dev_get_drvdata(pctldev);
	5216	+ if (bank >= info->ctrl->nr_banks)
	5217	+ return -EINVAL;
	5218	+
	5219	+ if (pin > 31 \|\| pin < 0)
	5220	+ return -EINVAL;
	5221	+
	5222	+ gpio = &info->ctrl->pin_banks[bank];
	5223	+
	5224	+ mutex_lock(&iomux_lock);
	5225	+ ret = rockchip_get_mux(gpio, pin);
	5226	+ mutex_unlock(&iomux_lock);
	5227	+
	5228	+ *mux = ret;
	5229	+
	5230	+ return (ret >= 0) ? 0 : ret;
	5231	+}
	5232	+EXPORT_SYMBOL_GPL(rk_iomux_get);
	5233	+
4351	5234	MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4352	5235	MODULE_LICENSE("GPL");
4353	5236	MODULE_ALIAS("platform:pinctrl-rockchip");