forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/pinctrl/intel/pinctrl-intel.h
....@@ -10,7 +10,15 @@
1010 #ifndef PINCTRL_INTEL_H
1111 #define PINCTRL_INTEL_H
1212 
13
-struct pinctrl_pin_desc;
13
+#include <linux/bits.h>
14
+#include <linux/compiler_types.h>
15
+#include <linux/gpio/driver.h>
16
+#include <linux/irq.h>
17
+#include <linux/kernel.h>
18
+#include <linux/pm.h>
19
+#include <linux/pinctrl/pinctrl.h>
20
+#include <linux/spinlock_types.h>
21
+
1422 struct platform_device;
1523 struct device;
1624 
....@@ -25,10 +33,10 @@
2533  */
2634 struct intel_pingroup {
2735 	const char *name;
28
-	const unsigned *pins;
36
+	const unsigned int *pins;
2937 	size_t npins;
3038 	unsigned short mode;
31
-	const unsigned *modes;
39
+	const unsigned int *modes;
3240 };
3341 
3442 /**
....@@ -48,19 +56,31 @@
4856  * @reg_num: GPI_IS register number
4957  * @base: Starting pin of this group
5058  * @size: Size of this group (maximum is 32).
51
- * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
52
- *	       and %-1 if no GPIO mapping should be created)
59
+ * @gpio_base: Starting GPIO base of this group
5360  * @padown_num: PAD_OWN register number (assigned by the core driver)
5461  *
5562  * If pad groups of a community are not the same size, use this structure
5663  * to specify them.
5764  */
5865 struct intel_padgroup {
59
-	unsigned reg_num;
60
-	unsigned base;
61
-	unsigned size;
66
+	unsigned int reg_num;
67
+	unsigned int base;
68
+	unsigned int size;
6269 	int gpio_base;
63
-	unsigned padown_num;
70
+	unsigned int padown_num;
71
+};
72
+
73
+/**
74
+ * enum - Special treatment for GPIO base in pad group
75
+ *
76
+ * @INTEL_GPIO_BASE_ZERO:	force GPIO base to be 0
77
+ * @INTEL_GPIO_BASE_NOMAP:	no GPIO mapping should be created
78
+ * @INTEL_GPIO_BASE_MATCH:	matches with starting pin number
79
+ */
80
+enum {
81
+	INTEL_GPIO_BASE_ZERO	= -2,
82
+	INTEL_GPIO_BASE_NOMAP	= -1,
83
+	INTEL_GPIO_BASE_MATCH	= 0,
6484 };
6585 
6686 /**
....@@ -73,42 +93,48 @@
7393  * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
7494  *                  is assumed that the host owns the pin (rather than
7595  *                  ACPI).
76
- * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
77
- *             default (%0x100).
96
+ * @is_offset: Register offset of GPI_IS from @regs.
7897  * @ie_offset: Register offset of GPI_IE from @regs.
98
+ * @features: Additional features supported by the hardware
7999  * @pin_base: Starting pin of pins in this community
100
+ * @npins: Number of pins in this community
80101  * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
81
- *            HOSTSW_OWN,  GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
102
+ *            HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
82103  * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
83104  *			 minimum. Use %0 if the number of registers can be
84105  *			 determined by the size of the group.
85
- * @npins: Number of pins in this community
86
- * @features: Additional features supported by the hardware
87106  * @gpps: Pad groups if the controller has variable size pad groups
88107  * @ngpps: Number of pad groups in this community
108
+ * @pad_map: Optional non-linear mapping of the pads
109
+ * @nirqs: Optional total number of IRQs this community can generate
110
+ * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
89111  * @regs: Community specific common registers (reserved for core driver)
90112  * @pad_regs: Community specific pad registers (reserved for core driver)
91113  *
92
- * Most Intel GPIO host controllers this driver supports each pad group is
93
- * of equal size (except the last one). In that case the driver can just
114
+ * In some of Intel GPIO host controllers this driver supports each pad group
115
+ * is of equal size (except the last one). In that case the driver can just
94116  * fill in @gpp_size field and let the core driver to handle the rest. If
95117  * the controller has pad groups of variable size the client driver can
96118  * pass custom @gpps and @ngpps instead.
97119  */
98120 struct intel_community {
99
-	unsigned barno;
100
-	unsigned padown_offset;
101
-	unsigned padcfglock_offset;
102
-	unsigned hostown_offset;
103
-	unsigned is_offset;
104
-	unsigned ie_offset;
105
-	unsigned pin_base;
106
-	unsigned gpp_size;
107
-	unsigned gpp_num_padown_regs;
121
+	unsigned int barno;
122
+	unsigned int padown_offset;
123
+	unsigned int padcfglock_offset;
124
+	unsigned int hostown_offset;
125
+	unsigned int is_offset;
126
+	unsigned int ie_offset;
127
+	unsigned int features;
128
+	unsigned int pin_base;
108129 	size_t npins;
109
-	unsigned features;
130
+	unsigned int gpp_size;
131
+	unsigned int gpp_num_padown_regs;
110132 	const struct intel_padgroup *gpps;
111133 	size_t ngpps;
134
+	const unsigned int *pad_map;
135
+	unsigned short nirqs;
136
+	unsigned short acpi_space_id;
137
+
112138 	/* Reserved for the core driver */
113139 	void __iomem *regs;
114140 	void __iomem *pad_regs;
....@@ -171,11 +197,61 @@
171197 	size_t ncommunities;
172198 };
173199 
174
-int intel_pinctrl_probe(struct platform_device *pdev,
175
-			const struct intel_pinctrl_soc_data *soc_data);
200
+const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
201
+
202
+struct intel_pad_context;
203
+struct intel_community_context;
204
+
205
+/**
206
+ * struct intel_pinctrl_context - context to be saved during suspend-resume
207
+ * @pads: Opaque context per pad (driver dependent)
208
+ * @communities: Opaque context per community (driver dependent)
209
+ */
210
+struct intel_pinctrl_context {
211
+	struct intel_pad_context *pads;
212
+	struct intel_community_context *communities;
213
+};
214
+
215
+/**
216
+ * struct intel_pinctrl - Intel pinctrl private structure
217
+ * @dev: Pointer to the device structure
218
+ * @lock: Lock to serialize register access
219
+ * @pctldesc: Pin controller description
220
+ * @pctldev: Pointer to the pin controller device
221
+ * @chip: GPIO chip in this pin controller
222
+ * @irqchip: IRQ chip in this pin controller
223
+ * @soc: SoC/PCH specific pin configuration data
224
+ * @communities: All communities in this pin controller
225
+ * @ncommunities: Number of communities in this pin controller
226
+ * @context: Configuration saved over system sleep
227
+ * @irq: pinctrl/GPIO chip irq number
228
+ */
229
+struct intel_pinctrl {
230
+	struct device *dev;
231
+	raw_spinlock_t lock;
232
+	struct pinctrl_desc pctldesc;
233
+	struct pinctrl_dev *pctldev;
234
+	struct gpio_chip chip;
235
+	struct irq_chip irqchip;
236
+	const struct intel_pinctrl_soc_data *soc;
237
+	struct intel_community *communities;
238
+	size_t ncommunities;
239
+	struct intel_pinctrl_context context;
240
+	int irq;
241
+};
242
+
243
+int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
244
+int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
245
+
176246 #ifdef CONFIG_PM_SLEEP
177
-int intel_pinctrl_suspend(struct device *dev);
178
-int intel_pinctrl_resume(struct device *dev);
247
+int intel_pinctrl_suspend_noirq(struct device *dev);
248
+int intel_pinctrl_resume_noirq(struct device *dev);
179249 #endif
180250 
251
+#define INTEL_PINCTRL_PM_OPS(_name)					\
252
+const struct dev_pm_ops _name = {					\
253
+	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq,	\
254
+				      intel_pinctrl_resume_noirq)	\
255
+}
256
+
181257 #endif /* PINCTRL_INTEL_H */