update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
..
..
@@ -745,10 +745,12 @@
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 		do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
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 	}
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-	inno->pixclock = vco;
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-	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
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+	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
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-	return vco;
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+	dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
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+		__func__, inno->pixclock, vco);
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+
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+	return inno->pixclock;
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 }
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 static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
..
..
@@ -790,8 +792,8 @@
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 			 RK3328_PRE_PLL_POWER_DOWN);
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 	/* Configure pre-pll */
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-	inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK,
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-			 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
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+	inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
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+			 RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
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 	inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
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 	val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
..
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@@ -1021,9 +1023,10 @@
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 	inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
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 	if (cfg->postdiv == 1) {
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-		inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
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 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
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 			   RK3328_POST_PLL_PRE_DIV(cfg->prediv));
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+		inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
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+			   RK3328_POST_PLL_POWER_DOWN);
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 	} else {
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 		v = (cfg->postdiv / 2) - 1;
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 		v &= RK3328_POST_PLL_POST_DIV_MASK;
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@@ -1031,7 +1034,8 @@
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 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
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 			   RK3328_POST_PLL_PRE_DIV(cfg->prediv));
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 		inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
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-			   RK3328_POST_PLL_REFCLK_SEL_TMDS);
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+			   RK3328_POST_PLL_REFCLK_SEL_TMDS |
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+			   RK3328_POST_PLL_POWER_DOWN);
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 	}
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 	for (v = 0; v < 14; v++)