update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
..
..
@@ -68,29 +68,61 @@
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 /**
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  * struct qcom_snps_hsphy - snps hs phy attributes
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  *
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+ * @dev: device structure
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+ *
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  * @phy: generic phy
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  * @base: iomapped memory space for snps hs phy
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  *
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- * @cfg_ahb_clk: AHB2PHY interface clock
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- * @ref_clk: phy reference clock
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- * @iface_clk: phy interface clock
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+ * @num_clks: number of clocks
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+ * @clks: array of clocks
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  * @phy_reset: phy reset control
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  * @vregs: regulator supplies bulk data
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  * @phy_initialized: if PHY has been initialized correctly
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  * @mode: contains the current mode the PHY is in
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+ * @update_seq_cfg: tuning parameters for phy init
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  */
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 struct qcom_snps_hsphy {
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+	struct device *dev;
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+
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 	struct phy *phy;
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 	void __iomem *base;
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-	struct clk *cfg_ahb_clk;
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-	struct clk *ref_clk;
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+	int num_clks;
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+	struct clk_bulk_data *clks;
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 	struct reset_control *phy_reset;
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 	struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
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 	bool phy_initialized;
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 	enum phy_mode mode;
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 };
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+
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+static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy)
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+{
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+	struct device *dev = hsphy->dev;
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+
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+	hsphy->num_clks = 2;
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+	hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL);
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+	if (!hsphy->clks)
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+		return -ENOMEM;
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+
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+	/*
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+	 * TODO: Currently no device tree instantiation of the PHY is using the clock.
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+	 * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get().
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+	 */
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+	hsphy->clks[0].id = "cfg_ahb";
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+	hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb");
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+	if (IS_ERR(hsphy->clks[0].clk))
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+		return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk),
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+				     "failed to get cfg_ahb clk\n");
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+
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+	hsphy->clks[1].id = "ref";
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+	hsphy->clks[1].clk = devm_clk_get(dev, "ref");
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+	if (IS_ERR(hsphy->clks[1].clk))
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+		return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk),
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+				     "failed to get ref clk\n");
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+
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+	return 0;
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+}
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 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
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 						u32 mask, u32 val)
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@@ -122,21 +154,12 @@
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 					   0, USB2_AUTO_RESUME);
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 	}
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-	clk_disable_unprepare(hsphy->cfg_ahb_clk);
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 	return 0;
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 }
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 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
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 {
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-	int ret;
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-
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 	dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
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-
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-	ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
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-	if (ret) {
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-		dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");
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-		return ret;
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-	}
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 	return 0;
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 }
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@@ -148,8 +171,7 @@
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 	if (!hsphy->phy_initialized)
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 		return 0;
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-	qcom_snps_hsphy_suspend(hsphy);
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-	return 0;
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+	return qcom_snps_hsphy_suspend(hsphy);
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 }
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 static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
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@@ -159,8 +181,7 @@
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 	if (!hsphy->phy_initialized)
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 		return 0;
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-	qcom_snps_hsphy_resume(hsphy);
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-	return 0;
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+	return qcom_snps_hsphy_resume(hsphy);
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 }
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 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
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@@ -183,16 +204,16 @@
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 	if (ret)
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 		return ret;
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-	ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
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+	ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks);
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 	if (ret) {
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-		dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
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+		dev_err(&phy->dev, "failed to enable clocks, %d\n", ret);
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 		goto poweroff_phy;
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 	}
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 	ret = reset_control_assert(hsphy->phy_reset);
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 	if (ret) {
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 		dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
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-		goto disable_ahb_clk;
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+		goto disable_clks;
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 	}
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 	usleep_range(100, 150);
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@@ -200,7 +221,7 @@
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 	ret = reset_control_deassert(hsphy->phy_reset);
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 	if (ret) {
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 		dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
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-		goto disable_ahb_clk;
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+		goto disable_clks;
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 	}
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 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
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@@ -246,8 +267,8 @@
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 	return 0;
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-disable_ahb_clk:
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-	clk_disable_unprepare(hsphy->cfg_ahb_clk);
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+disable_clks:
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+	clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);
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 poweroff_phy:
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 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
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@@ -259,7 +280,7 @@
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 	struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
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 	reset_control_assert(hsphy->phy_reset);
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-	clk_disable_unprepare(hsphy->cfg_ahb_clk);
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+	clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);
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 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
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 	hsphy->phy_initialized = false;
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..
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@@ -299,17 +320,15 @@
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 	if (!hsphy)
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 		return -ENOMEM;
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+	hsphy->dev = dev;
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+
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 	hsphy->base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(hsphy->base))
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 		return PTR_ERR(hsphy->base);
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-	hsphy->ref_clk = devm_clk_get(dev, "ref");
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-	if (IS_ERR(hsphy->ref_clk)) {
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-		ret = PTR_ERR(hsphy->ref_clk);
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-		if (ret != -EPROBE_DEFER)
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-			dev_err(dev, "failed to get ref clk, %d\n", ret);
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-		return ret;
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-	}
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+	ret = qcom_snps_hsphy_clk_init(hsphy);
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+	if (ret)
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+		return dev_err_probe(dev, ret, "failed to initialize clocks\n");
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 	hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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 	if (IS_ERR(hsphy->phy_reset)) {
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@@ -322,12 +341,9 @@
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 		hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
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 	ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
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-	if (ret) {
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-		if (ret != -EPROBE_DEFER)
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-			dev_err(dev, "failed to get regulator supplies: %d\n",
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-				ret);
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-		return ret;
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-	}
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+	if (ret)
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+		return dev_err_probe(dev, ret,
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+				     "failed to get regulator supplies\n");
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 	pm_runtime_set_active(dev);
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 	pm_runtime_enable(dev);