.. | .. |
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1210 | 1210 | val |= BIT(4); |
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1211 | 1211 | writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); |
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1212 | 1212 | |
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1213 | | - if (IS_ENABLED(CONFIG_PCI_MSI)) { |
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1214 | | - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); |
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1215 | | - val |= BIT(31); |
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1216 | | - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); |
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1217 | | - } |
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| 1213 | + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); |
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| 1214 | + val |= BIT(31); |
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| 1215 | + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); |
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1218 | 1216 | |
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1219 | 1217 | return 0; |
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1220 | 1218 | err_disable_clocks: |
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