forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
....@@ -94,11 +94,13 @@
9494 #define PCIE_ELBI_LOCAL_BASE		0x200e00
9595 
9696 #define PCIE_ELBI_APP_ELBI_INT_GEN0		0x0
97
-#define PCIE_ELBI_APP_ELBI_INT_GEN0_SIGIO	BIT(0)
97
+#define PCIE_ELBI_APP_ELBI_INT_GEN0_IRQ_USER	BIT(0)
9898 
9999 #define PCIE_ELBI_APP_ELBI_INT_GEN1		0x4
100100 
101101 #define PCIE_ELBI_LOCAL_ENABLE_OFF	0x8
102
+
103
+#define PCIE_ELBI_USER_DATA_OFF	0x10
102104 
103105 #define PCIE_DIRECT_SPEED_CHANGE	BIT(17)
104106 
....@@ -131,12 +133,14 @@
131133 	u32				ib_target_size[PCIE_BAR_MAX_NUM];
132134 	void				*ib_target_base[PCIE_BAR_MAX_NUM];
133135 	struct dma_trx_obj		*dma_obj;
134
-	struct fasync_struct		*async;
135136 	phys_addr_t			dbi_base_physical;
136137 	struct pcie_ep_obj_info		*obj_info;
137138 	enum pcie_ep_mmap_resource	cur_mmap_res;
138139 	struct workqueue_struct		*hot_rst_wq;
139140 	struct work_struct		hot_rst_work;
141
+	struct mutex			file_mutex;
142
+	DECLARE_BITMAP(virtual_id_irq_bitmap, RKEP_EP_VIRTUAL_ID_MAX);
143
+	wait_queue_head_t wq_head;
140144 };
141145 
142146 struct rockchip_pcie_misc_dev {
....@@ -528,18 +532,18 @@
528532 
529533 	/* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref, BAR4 1MB 32bits */
530534 	bar = BAR_0;
531
-	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
535
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x40);
532536 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0);
533537 	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
534538 
535539 	bar = BAR_2;
536
-	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
540
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x400);
537541 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
538542 	rockchip_pcie_ep_set_bar_flag(rockchip, bar,
539543 				      PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
540544 
541545 	bar = BAR_4;
542
-	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
546
+	dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x10);
543547 	dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
544548 	rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
545549 
....@@ -642,6 +646,49 @@
642646 	rockchip_pcie_writel_apb(rockchip, BIT(interrupt_num), PCIE_CLIENT_MSI_GEN_CON);
643647 }
644648 
649
+static int rockchip_pcie_raise_irq_user(struct rockchip_pcie *rockchip, u32 index)
650
+{
651
+	if (index >= RKEP_EP_VIRTUAL_ID_MAX) {
652
+		dev_err(rockchip->pci.dev, "raise irq_user, virtual id %d out of range\n", index);
653
+
654
+		return -EINVAL;
655
+	}
656
+
657
+	mutex_lock(&rockchip->file_mutex);
658
+	rockchip->obj_info->irq_type_rc = OBJ_IRQ_USER;
659
+	rockchip->obj_info->irq_user_data_rc = index;
660
+	rockchip_pcie_raise_msi_irq(rockchip, PCIe_CLIENT_MSI_OBJ_IRQ);
661
+	mutex_unlock(&rockchip->file_mutex);
662
+
663
+	return 0;
664
+}
665
+
666
+static int rockchip_pcie_poll_irq_user(struct rockchip_pcie *rockchip, struct pcie_ep_obj_poll_virtual_id_cfg *cfg)
667
+{
668
+	u32 index = cfg->virtual_id;
669
+
670
+	if (index >= RKEP_EP_VIRTUAL_ID_MAX) {
671
+		dev_err(rockchip->pci.dev, "poll irq_user, virtual id %d out of range\n", index);
672
+
673
+		return -EINVAL;
674
+	}
675
+
676
+	cfg->poll_status = NSIGPOLL;
677
+	if (cfg->sync)
678
+		wait_event_interruptible(rockchip->wq_head,
679
+					 test_bit(index, rockchip->virtual_id_irq_bitmap));
680
+	else
681
+		wait_event_interruptible_timeout(rockchip->wq_head,
682
+						 test_bit(index, rockchip->virtual_id_irq_bitmap),
683
+						 cfg->timeout_ms);
684
+	if (test_and_clear_bit(index, rockchip->virtual_id_irq_bitmap))
685
+		cfg->poll_status = POLL_IN;
686
+
687
+	dev_dbg(rockchip->pci.dev, "poll virtual id %d, ret=%d\n", index, cfg->poll_status);
688
+
689
+	return 0;
690
+}
691
+
645692 static irqreturn_t rockchip_pcie_sys_irq_handler(int irq, void *arg)
646693 {
647694 	struct rockchip_pcie *rockchip = arg;
....@@ -651,14 +698,19 @@
651698 	union int_status wr_status, rd_status;
652699 	union int_clear clears;
653700 	u32 reg, mask;
654
-	bool sigio = false;
655701 
656702 	/* ELBI helper, only check the valid bits, and discard the rest interrupts */
657703 	elbi_reg = dw_pcie_readl_dbi(pci, PCIE_ELBI_LOCAL_BASE + PCIE_ELBI_APP_ELBI_INT_GEN0);
658
-	if (elbi_reg & PCIE_ELBI_APP_ELBI_INT_GEN0_SIGIO) {
659
-		sigio = true;
660
-		rockchip->obj_info->irq_type_ep = OBJ_IRQ_ELBI;
704
+	if (elbi_reg & PCIE_ELBI_APP_ELBI_INT_GEN0_IRQ_USER) {
661705 		rockchip_pcie_elbi_clear(rockchip);
706
+
707
+		if (rockchip->obj_info->irq_type_ep == OBJ_IRQ_USER) {
708
+			reg = rockchip->obj_info->irq_user_data_ep;
709
+			if (reg < RKEP_EP_VIRTUAL_ID_MAX) {
710
+				set_bit(reg, rockchip->virtual_id_irq_bitmap);
711
+				wake_up_interruptible(&rockchip->wq_head);
712
+			}
713
+		}
662714 		goto out;
663715 	}
664716 
....@@ -711,15 +763,9 @@
711763 		rockchip->obj_info->irq_type_ep = OBJ_IRQ_DMA;
712764 		rockchip->obj_info->dma_status_ep.wr |= wr_status.asdword;
713765 		rockchip->obj_info->dma_status_ep.rd |= rd_status.asdword;
714
-		sigio = true;
715766 	}
716767 
717768 out:
718
-	if (sigio) {
719
-		dev_dbg(rockchip->pci.dev, "SIGIO\n");
720
-		kill_fasync(&rockchip->async, SIGIO, POLL_IN);
721
-	}
722
-
723769 	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
724770 	if (reg & BIT(2))
725771 		queue_work(rockchip->hot_rst_wq, &rockchip->hot_rst_work);
....@@ -944,13 +990,6 @@
944990 	.link_up = rockchip_pcie_link_up,
945991 };
946992 
947
-static int pcie_ep_fasync(int fd, struct file *file, int mode)
948
-{
949
-	struct rockchip_pcie *rockchip = (struct rockchip_pcie *)file->private_data;
950
-
951
-	return fasync_helper(fd, file, mode, &rockchip->async);
952
-}
953
-
954993 static int pcie_ep_open(struct inode *inode, struct file *file)
955994 {
956995 	struct miscdevice *miscdev = file->private_data;
....@@ -962,35 +1001,16 @@
9621001 	return 0;
9631002 }
9641003 
965
-static int pcie_ep_release(struct inode *inode, struct file *file)
966
-{
967
-	return pcie_ep_fasync(-1, file, 0);
968
-}
969
-
9701004 static long pcie_ep_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
9711005 {
9721006 	struct rockchip_pcie *rockchip = (struct rockchip_pcie *)file->private_data;
973
-	struct pcie_ep_user_data msg;
9741007 	struct pcie_ep_dma_cache_cfg cfg;
9751008 	void __user *uarg = (void __user *)arg;
976
-	int i, ret;
1009
+	struct pcie_ep_obj_poll_virtual_id_cfg poll_cfg;
9771010 	enum pcie_ep_mmap_resource mmap_res;
1011
+	int ret, index;
9781012 
9791013 	switch (cmd) {
980
-	case PCIE_DMA_GET_ELBI_DATA:
981
-		for (i = 4; i <= 6; i++)
982
-			msg.elbi_app_user[i - 4] = dw_pcie_readl_dbi(&rockchip->pci,
983
-								     PCIE_ELBI_LOCAL_BASE + i * 4);
984
-		for (i = 8; i <= 15; i++)
985
-			msg.elbi_app_user[i - 5] = dw_pcie_readl_dbi(&rockchip->pci,
986
-								     PCIE_ELBI_LOCAL_BASE + i * 4);
987
-
988
-		ret = copy_to_user(uarg, &msg, sizeof(msg));
989
-		if (ret) {
990
-			dev_err(rockchip->pci.dev, "failed to get elbi data\n");
991
-			return -EFAULT;
992
-		}
993
-		break;
9941014 	case PCIE_DMA_CACHE_INVALIDE:
9951015 		ret = copy_from_user(&cfg, uarg, sizeof(cfg));
9961016 		if (ret) {
....@@ -1013,18 +1033,8 @@
10131033 		dw_pcie_writel_dbi(&rockchip->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_MASK,
10141034 				   0xffffffff);
10151035 		break;
1016
-	case PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER:
1017
-		rockchip->obj_info->irq_type_rc = OBJ_IRQ_USER;
1036
+	case PCIE_EP_RAISE_MSI:
10181037 		rockchip_pcie_raise_msi_irq(rockchip, PCIe_CLIENT_MSI_OBJ_IRQ);
1019
-		break;
1020
-	case PCIE_EP_GET_USER_INFO:
1021
-		msg.bar0_phys_addr = rockchip->ib_target_address[0];
1022
-
1023
-		ret = copy_to_user(uarg, &msg, sizeof(msg));
1024
-		if (ret) {
1025
-			dev_err(rockchip->pci.dev, "failed to get elbi data\n");
1026
-			return -EFAULT;
1027
-		}
10281038 		break;
10291039 	case PCIE_EP_SET_MMAP_RESOURCE:
10301040 		ret = copy_from_user(&mmap_res, uarg, sizeof(mmap_res));
....@@ -1039,6 +1049,34 @@
10391049 		}
10401050 
10411051 		rockchip->cur_mmap_res = mmap_res;
1052
+		break;
1053
+	case PCIE_EP_RAISE_IRQ_USER:
1054
+		ret = copy_from_user(&index, uarg, sizeof(index));
1055
+		if (ret) {
1056
+			dev_err(rockchip->pci.dev,
1057
+				"failed to get raise irq data copy from userspace\n");
1058
+			return -EFAULT;
1059
+		}
1060
+
1061
+		ret = rockchip_pcie_raise_irq_user(rockchip, index);
1062
+		if (ret < 0)
1063
+			return -EFAULT;
1064
+		break;
1065
+	case PCIE_EP_POLL_IRQ_USER:
1066
+		ret = copy_from_user(&poll_cfg, uarg, sizeof(poll_cfg));
1067
+		if (ret) {
1068
+			dev_err(rockchip->pci.dev,
1069
+				"failed to get poll irq data copy from userspace\n");
1070
+
1071
+			return -EFAULT;
1072
+		}
1073
+
1074
+		ret = rockchip_pcie_poll_irq_user(rockchip, &poll_cfg);
1075
+		if (ret < 0)
1076
+			return -EFAULT;
1077
+
1078
+		if (copy_to_user(uarg, &poll_cfg, sizeof(poll_cfg)))
1079
+			return -EFAULT;
10421080 		break;
10431081 	default:
10441082 		break;
....@@ -1100,9 +1138,7 @@
11001138 static const struct file_operations pcie_ep_ops = {
11011139 	.owner = THIS_MODULE,
11021140 	.open = pcie_ep_open,
1103
-	.release = pcie_ep_release,
11041141 	.unlocked_ioctl = pcie_ep_ioctl,
1105
-	.fasync = pcie_ep_fasync,
11061142 	.mmap = pcie_ep_mmap,
11071143 };
11081144 
....@@ -1265,12 +1301,14 @@
12651301 		rockchip->dma_obj->config_dma_func = rockchip_pcie_config_dma_dwc;
12661302 		rockchip->dma_obj->get_dma_status = rockchip_pcie_get_dma_status;
12671303 	}
1304
+	mutex_init(&rockchip->file_mutex);
12681305 
12691306 	/* Enable client ELBI interrupt */
12701307 	rockchip_pcie_writel_apb(rockchip, 0x80000000, PCIE_CLIENT_INTR_MASK);
12711308 	/* Enable ELBI interrupt */
12721309 	rockchip_pcie_local_elbi_enable(rockchip);
12731310 
1311
+	init_waitqueue_head(&rockchip->wq_head);
12741312 	ret = rockchip_pcie_request_sys_irq(rockchip, pdev);
12751313 	if (ret)
12761314 		goto deinit_phy;