forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/pci/controller/dwc/pci-dra7xx.c
....@@ -2,7 +2,7 @@
22 /*
33  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
44  *
5
- * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
5
+ * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
66  *
77  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
88  */
....@@ -73,8 +73,6 @@
7373 #define	LINK_UP						BIT(16)
7474 #define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF
7575 
76
-#define EXP_CAP_ID_OFFSET				0x70
77
-
7876 #define	PCIECTRL_TI_CONF_INTX_ASSERT			0x0124
7977 #define	PCIECTRL_TI_CONF_INTX_DEASSERT			0x0128
8078 
....@@ -82,18 +80,22 @@
8280 #define MSI_REQ_GRANT					BIT(0)
8381 #define MSI_VECTOR_SHIFT				7
8482 
83
+#define PCIE_1LANE_2LANE_SELECTION			BIT(13)
84
+#define PCIE_B1C0_MODE_SEL				BIT(2)
85
+#define PCIE_B0_B1_TSYNCEN				BIT(0)
86
+
8587 struct dra7xx_pcie {
8688 	struct dw_pcie		*pci;
8789 	void __iomem		*base;		/* DT ti_conf */
8890 	int			phy_count;	/* DT phy-names count */
8991 	struct phy		**phy;
90
-	int			link_gen;
9192 	struct irq_domain	*irq_domain;
9293 	enum dw_pcie_device_mode mode;
9394 };
9495 
9596 struct dra7xx_pcie_of_data {
9697 	enum dw_pcie_device_mode mode;
98
+	u32 b1co_mode_sel_mask;
9799 };
98100 
99101 #define to_dra7xx_pcie(x)	dev_get_drvdata((x)->dev)
....@@ -137,31 +139,10 @@
137139 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
138140 	struct device *dev = pci->dev;
139141 	u32 reg;
140
-	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
141142 
142143 	if (dw_pcie_link_up(pci)) {
143144 		dev_err(dev, "link is already up\n");
144145 		return 0;
145
-	}
146
-
147
-	if (dra7xx->link_gen == 1) {
148
-		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
149
-			     4, &reg);
150
-		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
151
-			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
152
-			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
153
-			dw_pcie_write(pci->dbi_base + exp_cap_off +
154
-				      PCI_EXP_LNKCAP, 4, reg);
155
-		}
156
-
157
-		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
158
-			     2, &reg);
159
-		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
160
-			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
161
-			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
162
-			dw_pcie_write(pci->dbi_base + exp_cap_off +
163
-				      PCI_EXP_LNKCTL2, 2, reg);
164
-		}
165146 	}
166147 
167148 	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
....@@ -210,10 +191,6 @@
210191 	return 0;
211192 }
212193 
213
-static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
214
-	.host_init = dra7xx_pcie_host_init,
215
-};
216
-
217194 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
218195 				irq_hw_number_t hwirq)
219196 {
....@@ -228,42 +205,77 @@
228205 	.xlate = pci_irqd_intx_xlate,
229206 };
230207 
231
-static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
208
+static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
232209 {
233210 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
234
-	struct device *dev = pci->dev;
235
-	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
236
-	struct device_node *node = dev->of_node;
237
-	struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
211
+	unsigned long val;
212
+	int pos, irq;
238213 
239
-	if (!pcie_intc_node) {
240
-		dev_err(dev, "No PCIe Intc node found\n");
241
-		return -ENODEV;
214
+	val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
215
+				   (index * MSI_REG_CTRL_BLOCK_SIZE));
216
+	if (!val)
217
+		return 0;
218
+
219
+	pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 0);
220
+	while (pos != MAX_MSI_IRQS_PER_CTRL) {
221
+		irq = irq_find_mapping(pp->irq_domain,
222
+				       (index * MAX_MSI_IRQS_PER_CTRL) + pos);
223
+		generic_handle_irq(irq);
224
+		pos++;
225
+		pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
242226 	}
243227 
244
-	dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
245
-						   &intx_domain_ops, pp);
246
-	if (!dra7xx->irq_domain) {
247
-		dev_err(dev, "Failed to get a INTx IRQ domain\n");
248
-		return -ENODEV;
249
-	}
250
-
251
-	return 0;
228
+	return 1;
252229 }
253230 
254
-static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
231
+static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
255232 {
256
-	struct dra7xx_pcie *dra7xx = arg;
257
-	struct dw_pcie *pci = dra7xx->pci;
258
-	struct pcie_port *pp = &pci->pp;
233
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
234
+	int ret, i, count, num_ctrls;
235
+
236
+	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
237
+
238
+	/**
239
+	 * Need to make sure all MSI status bits read 0 before exiting.
240
+	 * Else, new MSI IRQs are not registered by the wrapper. Have an
241
+	 * upperbound for the loop and exit the IRQ in case of IRQ flood
242
+	 * to avoid locking up system in interrupt context.
243
+	 */
244
+	count = 0;
245
+	do {
246
+		ret = 0;
247
+
248
+		for (i = 0; i < num_ctrls; i++)
249
+			ret |= dra7xx_pcie_handle_msi(pp, i);
250
+		count++;
251
+	} while (ret && count <= 1000);
252
+
253
+	if (count > 1000)
254
+		dev_warn_ratelimited(pci->dev,
255
+				     "Too many MSI IRQs to handle\n");
256
+}
257
+
258
+static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
259
+{
260
+	struct irq_chip *chip = irq_desc_get_chip(desc);
261
+	struct dra7xx_pcie *dra7xx;
262
+	struct dw_pcie *pci;
263
+	struct pcie_port *pp;
259264 	unsigned long reg;
260265 	u32 virq, bit;
261266 
267
+	chained_irq_enter(chip, desc);
268
+
269
+	pp = irq_desc_get_handler_data(desc);
270
+	pci = to_dw_pcie_from_pp(pp);
271
+	dra7xx = to_dra7xx_pcie(pci);
272
+
262273 	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
274
+	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
263275 
264276 	switch (reg) {
265277 	case MSI:
266
-		dw_handle_msi_irq(pp);
278
+		dra7xx_pcie_handle_msi_irq(pp);
267279 		break;
268280 	case INTA:
269281 	case INTB:
....@@ -277,9 +289,7 @@
277289 		break;
278290 	}
279291 
280
-	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
281
-
282
-	return IRQ_HANDLED;
292
+	chained_irq_exit(chip, desc);
283293 }
284294 
285295 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
....@@ -341,13 +351,168 @@
341351 	return IRQ_HANDLED;
342352 }
343353 
354
+static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
355
+{
356
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
357
+	struct device *dev = pci->dev;
358
+	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
359
+	struct device_node *node = dev->of_node;
360
+	struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
361
+
362
+	if (!pcie_intc_node) {
363
+		dev_err(dev, "No PCIe Intc node found\n");
364
+		return -ENODEV;
365
+	}
366
+
367
+	irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
368
+					 pp);
369
+	dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
370
+						   &intx_domain_ops, pp);
371
+	of_node_put(pcie_intc_node);
372
+	if (!dra7xx->irq_domain) {
373
+		dev_err(dev, "Failed to get a INTx IRQ domain\n");
374
+		return -ENODEV;
375
+	}
376
+
377
+	return 0;
378
+}
379
+
380
+static void dra7xx_pcie_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
381
+{
382
+	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
383
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
384
+	u64 msi_target;
385
+
386
+	msi_target = (u64)pp->msi_data;
387
+
388
+	msg->address_lo = lower_32_bits(msi_target);
389
+	msg->address_hi = upper_32_bits(msi_target);
390
+
391
+	msg->data = d->hwirq;
392
+
393
+	dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
394
+		(int)d->hwirq, msg->address_hi, msg->address_lo);
395
+}
396
+
397
+static int dra7xx_pcie_msi_set_affinity(struct irq_data *d,
398
+					const struct cpumask *mask,
399
+					bool force)
400
+{
401
+	return -EINVAL;
402
+}
403
+
404
+static void dra7xx_pcie_bottom_mask(struct irq_data *d)
405
+{
406
+	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
407
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
408
+	unsigned int res, bit, ctrl;
409
+	unsigned long flags;
410
+
411
+	raw_spin_lock_irqsave(&pp->lock, flags);
412
+
413
+	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
414
+	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
415
+	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
416
+
417
+	pp->irq_mask[ctrl] |= BIT(bit);
418
+	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res,
419
+			   pp->irq_mask[ctrl]);
420
+
421
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
422
+}
423
+
424
+static void dra7xx_pcie_bottom_unmask(struct irq_data *d)
425
+{
426
+	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
427
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
428
+	unsigned int res, bit, ctrl;
429
+	unsigned long flags;
430
+
431
+	raw_spin_lock_irqsave(&pp->lock, flags);
432
+
433
+	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
434
+	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
435
+	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
436
+
437
+	pp->irq_mask[ctrl] &= ~BIT(bit);
438
+	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res,
439
+			   pp->irq_mask[ctrl]);
440
+
441
+	raw_spin_unlock_irqrestore(&pp->lock, flags);
442
+}
443
+
444
+static void dra7xx_pcie_bottom_ack(struct irq_data *d)
445
+{
446
+	struct pcie_port *pp  = irq_data_get_irq_chip_data(d);
447
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
448
+	unsigned int res, bit, ctrl;
449
+
450
+	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
451
+	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
452
+	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
453
+
454
+	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
455
+}
456
+
457
+static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = {
458
+	.name = "DRA7XX-PCI-MSI",
459
+	.irq_ack = dra7xx_pcie_bottom_ack,
460
+	.irq_compose_msi_msg = dra7xx_pcie_setup_msi_msg,
461
+	.irq_set_affinity = dra7xx_pcie_msi_set_affinity,
462
+	.irq_mask = dra7xx_pcie_bottom_mask,
463
+	.irq_unmask = dra7xx_pcie_bottom_unmask,
464
+};
465
+
466
+static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
467
+{
468
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
469
+	struct device *dev = pci->dev;
470
+	u32 ctrl, num_ctrls;
471
+	int ret;
472
+
473
+	pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
474
+
475
+	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
476
+	/* Initialize IRQ Status array */
477
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
478
+		pp->irq_mask[ctrl] = ~0;
479
+		dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
480
+				    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
481
+				    pp->irq_mask[ctrl]);
482
+		dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
483
+				    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
484
+				    ~0);
485
+	}
486
+
487
+	ret = dw_pcie_allocate_domains(pp);
488
+	if (ret)
489
+		return ret;
490
+
491
+	pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
492
+					   sizeof(pp->msi_msg),
493
+					   DMA_FROM_DEVICE,
494
+					   DMA_ATTR_SKIP_CPU_SYNC);
495
+	ret = dma_mapping_error(dev, pp->msi_data);
496
+	if (ret) {
497
+		dev_err(dev, "Failed to map MSI data\n");
498
+		pp->msi_data = 0;
499
+		dw_pcie_free_msi(pp);
500
+	}
501
+	return ret;
502
+}
503
+
504
+static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
505
+	.host_init = dra7xx_pcie_host_init,
506
+	.msi_host_init = dra7xx_pcie_msi_host_init,
507
+};
508
+
344509 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
345510 {
346511 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
347512 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
348513 	enum pci_barno bar;
349514 
350
-	for (bar = BAR_0; bar <= BAR_5; bar++)
515
+	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
351516 		dw_pcie_ep_reset_bar(pci, bar);
352517 
353518 	dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
....@@ -390,9 +555,22 @@
390555 	return 0;
391556 }
392557 
393
-static struct dw_pcie_ep_ops pcie_ep_ops = {
558
+static const struct pci_epc_features dra7xx_pcie_epc_features = {
559
+	.linkup_notifier = true,
560
+	.msi_capable = true,
561
+	.msix_capable = false,
562
+};
563
+
564
+static const struct pci_epc_features*
565
+dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
566
+{
567
+	return &dra7xx_pcie_epc_features;
568
+}
569
+
570
+static const struct dw_pcie_ep_ops pcie_ep_ops = {
394571 	.ep_init = dra7xx_pcie_ep_init,
395572 	.raise_irq = dra7xx_pcie_raise_irq,
573
+	.get_features = dra7xx_pcie_get_features,
396574 };
397575 
398576 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
....@@ -407,13 +585,12 @@
407585 	ep = &pci->ep;
408586 	ep->ops = &pcie_ep_ops;
409587 
410
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
411
-	pci->dbi_base = devm_ioremap_resource(dev, res);
588
+	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
412589 	if (IS_ERR(pci->dbi_base))
413590 		return PTR_ERR(pci->dbi_base);
414591 
415
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
416
-	pci->dbi_base2 = devm_ioremap_resource(dev, res);
592
+	pci->dbi_base2 =
593
+		devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
417594 	if (IS_ERR(pci->dbi_base2))
418595 		return PTR_ERR(pci->dbi_base2);
419596 
....@@ -440,28 +617,16 @@
440617 	struct dw_pcie *pci = dra7xx->pci;
441618 	struct pcie_port *pp = &pci->pp;
442619 	struct device *dev = pci->dev;
443
-	struct resource *res;
444620 
445621 	pp->irq = platform_get_irq(pdev, 1);
446
-	if (pp->irq < 0) {
447
-		dev_err(dev, "missing IRQ resource\n");
622
+	if (pp->irq < 0)
448623 		return pp->irq;
449
-	}
450
-
451
-	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
452
-			       IRQF_SHARED | IRQF_NO_THREAD,
453
-			       "dra7-pcie-msi",	dra7xx);
454
-	if (ret) {
455
-		dev_err(dev, "failed to request irq\n");
456
-		return ret;
457
-	}
458624 
459625 	ret = dra7xx_pcie_init_irq_domain(pp);
460626 	if (ret < 0)
461627 		return ret;
462628 
463
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
464
-	pci->dbi_base = devm_ioremap_resource(dev, res);
629
+	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
465630 	if (IS_ERR(pci->dbi_base))
466631 		return PTR_ERR(pci->dbi_base);
467632 
....@@ -500,6 +665,10 @@
500665 	int i;
501666 
502667 	for (i = 0; i < phy_count; i++) {
668
+		ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
669
+		if (ret < 0)
670
+			goto err_phy;
671
+
503672 		ret = phy_init(dra7xx->phy[i]);
504673 		if (ret < 0)
505674 			goto err_phy;
....@@ -530,6 +699,26 @@
530699 	.mode = DW_PCIE_EP_TYPE,
531700 };
532701 
702
+static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
703
+	.b1co_mode_sel_mask = BIT(2),
704
+	.mode = DW_PCIE_RC_TYPE,
705
+};
706
+
707
+static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
708
+	.b1co_mode_sel_mask = GENMASK(3, 2),
709
+	.mode = DW_PCIE_RC_TYPE,
710
+};
711
+
712
+static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
713
+	.b1co_mode_sel_mask = BIT(2),
714
+	.mode = DW_PCIE_EP_TYPE,
715
+};
716
+
717
+static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
718
+	.b1co_mode_sel_mask = GENMASK(3, 2),
719
+	.mode = DW_PCIE_EP_TYPE,
720
+};
721
+
533722 static const struct of_device_id of_dra7xx_pcie_match[] = {
534723 	{
535724 		.compatible = "ti,dra7-pcie",
....@@ -538,6 +727,22 @@
538727 	{
539728 		.compatible = "ti,dra7-pcie-ep",
540729 		.data = &dra7xx_pcie_ep_of_data,
730
+	},
731
+	{
732
+		.compatible = "ti,dra746-pcie-rc",
733
+		.data = &dra746_pcie_rc_of_data,
734
+	},
735
+	{
736
+		.compatible = "ti,dra726-pcie-rc",
737
+		.data = &dra726_pcie_rc_of_data,
738
+	},
739
+	{
740
+		.compatible = "ti,dra746-pcie-ep",
741
+		.data = &dra746_pcie_ep_of_data,
742
+	},
743
+	{
744
+		.compatible = "ti,dra726-pcie-ep",
745
+		.data = &dra726_pcie_ep_of_data,
541746 	},
542747 	{},
543748 };
....@@ -584,6 +789,34 @@
584789 	return ret;
585790 }
586791 
792
+static int dra7xx_pcie_configure_two_lane(struct device *dev,
793
+					  u32 b1co_mode_sel_mask)
794
+{
795
+	struct device_node *np = dev->of_node;
796
+	struct regmap *pcie_syscon;
797
+	unsigned int pcie_reg;
798
+	u32 mask;
799
+	u32 val;
800
+
801
+	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
802
+	if (IS_ERR(pcie_syscon)) {
803
+		dev_err(dev, "unable to get ti,syscon-lane-sel\n");
804
+		return -EINVAL;
805
+	}
806
+
807
+	if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
808
+				       &pcie_reg)) {
809
+		dev_err(dev, "couldn't get lane selection reg offset\n");
810
+		return -EINVAL;
811
+	}
812
+
813
+	mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
814
+	val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
815
+	regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
816
+
817
+	return 0;
818
+}
819
+
587820 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
588821 {
589822 	u32 reg;
....@@ -594,7 +827,6 @@
594827 	struct phy **phy;
595828 	struct device_link **link;
596829 	void __iomem *base;
597
-	struct resource *res;
598830 	struct dw_pcie *pci;
599831 	struct dra7xx_pcie *dra7xx;
600832 	struct device *dev = &pdev->dev;
....@@ -604,6 +836,7 @@
604836 	const struct of_device_id *match;
605837 	const struct dra7xx_pcie_of_data *data;
606838 	enum dw_pcie_device_mode mode;
839
+	u32 b1co_mode_sel_mask;
607840 
608841 	match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
609842 	if (!match)
....@@ -611,6 +844,7 @@
611844 
612845 	data = (struct dra7xx_pcie_of_data *)match->data;
613846 	mode = (enum dw_pcie_device_mode)data->mode;
847
+	b1co_mode_sel_mask = data->b1co_mode_sel_mask;
614848 
615849 	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
616850 	if (!dra7xx)
....@@ -624,15 +858,12 @@
624858 	pci->ops = &dw_pcie_ops;
625859 
626860 	irq = platform_get_irq(pdev, 0);
627
-	if (irq < 0) {
628
-		dev_err(dev, "missing IRQ resource: %d\n", irq);
861
+	if (irq < 0)
629862 		return irq;
630
-	}
631863 
632
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
633
-	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
634
-	if (!base)
635
-		return -ENOMEM;
864
+	base = devm_platform_ioremap_resource_byname(pdev, "ti_conf");
865
+	if (IS_ERR(base))
866
+		return PTR_ERR(base);
636867 
637868 	phy_count = of_property_count_strings(np, "phy-names");
638869 	if (phy_count < 0) {
....@@ -666,6 +897,12 @@
666897 	dra7xx->pci = pci;
667898 	dra7xx->phy_count = phy_count;
668899 
900
+	if (phy_count == 2) {
901
+		ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
902
+		if (ret < 0)
903
+			dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
904
+	}
905
+
669906 	ret = dra7xx_pcie_enable_phy(dra7xx);
670907 	if (ret) {
671908 		dev_err(dev, "failed to enable phy\n");
....@@ -691,10 +928,6 @@
691928 	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
692929 	reg &= ~LTSSM_EN;
693930 	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
694
-
695
-	dra7xx->link_gen = of_pci_get_max_link_speed(np);
696
-	if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
697
-		dra7xx->link_gen = 2;
698931 
699932 	switch (mode) {
700933 	case DW_PCIE_RC_TYPE:
....@@ -746,9 +979,8 @@
746979 	return 0;
747980 
748981 err_gpio:
749
-	pm_runtime_put(dev);
750
-
751982 err_get_sync:
983
+	pm_runtime_put(dev);
752984 	pm_runtime_disable(dev);
753985 	dra7xx_pcie_disable_phy(dra7xx);
754986