forked from ~ljy/RK356X_SDK_RELEASE

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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2010  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2010  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../efuse.h"
....@@ -48,22 +26,25 @@
4826 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4927 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
5028 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
29
+	struct sk_buff_head free_list;
5130 	unsigned long flags;
5231 
32
+	skb_queue_head_init(&free_list);
5333 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
5434 	while (skb_queue_len(&ring->queue)) {
5535 		struct rtl_tx_desc *entry = &ring->desc[ring->idx];
5636 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
5737 
58
-		pci_unmap_single(rtlpci->pdev,
59
-				 rtlpriv->cfg->ops->get_desc(
60
-				 hw,
61
-				 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
62
-				 skb->len, PCI_DMA_TODEVICE);
63
-		kfree_skb(skb);
38
+		dma_unmap_single(&rtlpci->pdev->dev,
39
+				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
40
+						true, HW_DESC_TXBUFF_ADDR),
41
+				 skb->len, DMA_TO_DEVICE);
42
+		__skb_queue_tail(&free_list, skb);
6443 		ring->idx = (ring->idx + 1) % ring->entries;
6544 	}
6645 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
46
+
47
+	__skb_queue_purge(&free_list);
6748 }
6849 
6950 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
....@@ -165,9 +146,9 @@
165146 			if (content & IMR_CPWM) {
166147 				rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
167148 				rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
168
-				RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
169
-					 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
170
-					 rtlhal->fw_ps_state);
149
+				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
150
+					"Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
151
+					rtlhal->fw_ps_state);
171152 			}
172153 		}
173154 
....@@ -352,8 +333,8 @@
352333 	} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
353334 
354335 	if (!(bcnvalid_reg & BIT(0)))
355
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
356
-			 "Download RSVD page failed!\n");
336
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
337
+			"Download RSVD page failed!\n");
357338 	if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
358339 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
359340 		_rtl8821ae_return_beacon_queue_skb(hw);
....@@ -387,8 +368,8 @@
387368 			} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
388369 
389370 			if (!(bcnvalid_reg & BIT(0)))
390
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
391
-					 "2 Download RSVD page failed!\n");
371
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
372
+					"2 Download RSVD page failed!\n");
392373 		}
393374 	}
394375 
....@@ -480,8 +461,8 @@
480461 			*((bool *)(val)) = false;
481462 		break;
482463 	default:
483
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
484
-			 "switch case %#x not processed\n", variable);
464
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
465
+			"switch case %#x not processed\n", variable);
485466 		break;
486467 	}
487468 }
....@@ -533,8 +514,8 @@
533514 	case HW_VAR_SLOT_TIME:{
534515 		u8 e_aci;
535516 
536
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
537
-			 "HW_VAR_SLOT_TIME %x\n", val[0]);
517
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
518
+			"HW_VAR_SLOT_TIME %x\n", val[0]);
538519 
539520 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
540521 
....@@ -580,9 +561,9 @@
580561 
581562 			*val = min_spacing_to_set;
582563 
583
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
584
-				 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
585
-				  mac->min_space_cfg);
564
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
565
+				"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
566
+				mac->min_space_cfg);
586567 
587568 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
588569 				       mac->min_space_cfg);
....@@ -594,9 +575,9 @@
594575 		density_to_set = *((u8 *)val);
595576 		mac->min_space_cfg |= (density_to_set << 3);
596577 
597
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
598
-			 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
599
-			  mac->min_space_cfg);
578
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
579
+			"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
580
+			mac->min_space_cfg);
600581 
601582 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
602583 			       mac->min_space_cfg);
....@@ -654,9 +635,9 @@
654635 				acm_ctrl |= ACMHW_VOQEN;
655636 				break;
656637 			default:
657
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
658
-					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
659
-					 acm);
638
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
639
+					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
640
+					acm);
660641 				break;
661642 			}
662643 		} else {
....@@ -671,16 +652,16 @@
671652 				acm_ctrl &= (~ACMHW_VOQEN);
672653 				break;
673654 			default:
674
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
675
-					 "switch case %#x not processed\n",
676
-					 e_aci);
655
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
656
+					"switch case %#x not processed\n",
657
+					e_aci);
677658 				break;
678659 			}
679660 		}
680661 
681
-		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
682
-			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
683
-			 acm_ctrl);
662
+		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
663
+			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
664
+			acm_ctrl);
684665 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
685666 		break; }
686667 	case HW_VAR_RCR:
....@@ -783,9 +764,9 @@
783764 		u32	us_nav_upper = *(u32 *)val;
784765 
785766 		if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
786
-			RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
787
-				 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
788
-				 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
767
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
768
+				"The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
769
+				us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
789770 			break;
790771 		}
791772 		rtl_write_byte(rtlpriv, REG_NAV_UPPER,
....@@ -801,8 +782,8 @@
801782 				       array);
802783 		break; }
803784 	default:
804
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
805
-			 "switch case %#x not processed\n", variable);
785
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
786
+			"switch case %#x not processed\n", variable);
806787 		break;
807788 	}
808789 }
....@@ -932,16 +913,16 @@
932913 		if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
933914 					      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
934915 					      RTL8812_NIC_ENABLE_FLOW)) {
935
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
936
-					 "init 8812 MAC Fail as power on failure\n");
937
-				return false;
916
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
917
+				"init 8812 MAC Fail as power on failure\n");
918
+			return false;
938919 		}
939920 	} else {
940921 		/* HW Power on sequence */
941922 		if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
942923 					      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
943924 					      RTL8821A_NIC_ENABLE_FLOW)){
944
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
925
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
945926 				"init 8821 MAC Fail as power on failure\n");
946927 			return false;
947928 		}
....@@ -1183,14 +1164,14 @@
11831164 	u8 sec_reg_value;
11841165 	u8 tmp;
11851166 
1186
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1187
-		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1188
-		  rtlpriv->sec.pairwise_enc_algorithm,
1189
-		  rtlpriv->sec.group_enc_algorithm);
1167
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1168
+		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1169
+		rtlpriv->sec.pairwise_enc_algorithm,
1170
+		rtlpriv->sec.group_enc_algorithm);
11901171 
11911172 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1192
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1193
-			 "not open hw encryption\n");
1173
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1174
+			"not open hw encryption\n");
11941175 		return;
11951176 	}
11961177 
....@@ -1206,8 +1187,8 @@
12061187 	tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
12071188 	rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
12081189 
1209
-	RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1210
-		 "The SECR-value %x\n", sec_reg_value);
1190
+	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1191
+		"The SECR-value %x\n", sec_reg_value);
12111192 
12121193 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
12131194 }
....@@ -1229,10 +1210,10 @@
12291210 	rtlpriv->cfg->ops->set_hw_reg(hw,
12301211 		HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
12311212 
1232
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1233
-		 "Initialize MacId media status: from %d to %d\n",
1234
-		 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1235
-		 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1213
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1214
+		"Initialize MacId media status: from %d to %d\n",
1215
+		MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1216
+		MAC_ID_STATIC_FOR_BT_CLIENT_END);
12361217 }
12371218 
12381219 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
....@@ -1251,8 +1232,8 @@
12511232 	/* read reg 0x350 Bit[24] if 1 : TX hang */
12521233 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
12531234 	if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1254
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1255
-			 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1235
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1236
+			"CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
12561237 		return true;
12571238 	} else {
12581239 		return false;
....@@ -1269,7 +1250,7 @@
12691250 	bool release_mac_rx_pause;
12701251 	u8 backup_pcie_dma_pause;
12711252 
1272
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1253
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
12731254 
12741255 	/* 1. Disable register write lock. 0x1c[1] = 0 */
12751256 	tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
....@@ -1368,8 +1349,8 @@
13681349 
13691350 	fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
13701351 
1371
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1372
-		 fw_reason);
1352
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1353
+		fw_reason);
13731354 
13741355 	ppsc->wakeup_reason = 0;
13751356 
....@@ -1378,63 +1359,63 @@
13781359 	switch (fw_reason) {
13791360 	case FW_WOW_V2_PTK_UPDATE_EVENT:
13801361 		ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1381
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1382
-			 "It's a WOL PTK Key update event!\n");
1362
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1363
+			"It's a WOL PTK Key update event!\n");
13831364 		break;
13841365 	case FW_WOW_V2_GTK_UPDATE_EVENT:
13851366 		ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1386
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1387
-			 "It's a WOL GTK Key update event!\n");
1367
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1368
+			"It's a WOL GTK Key update event!\n");
13881369 		break;
13891370 	case FW_WOW_V2_DISASSOC_EVENT:
13901371 		ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1391
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1392
-			 "It's a disassociation event!\n");
1372
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1373
+			"It's a disassociation event!\n");
13931374 		break;
13941375 	case FW_WOW_V2_DEAUTH_EVENT:
13951376 		ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1396
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1397
-			 "It's a deauth event!\n");
1377
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1378
+			"It's a deauth event!\n");
13981379 		break;
13991380 	case FW_WOW_V2_FW_DISCONNECT_EVENT:
14001381 		ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1401
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1402
-			 "It's a Fw disconnect decision (AP lost) event!\n");
1382
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1383
+			"It's a Fw disconnect decision (AP lost) event!\n");
14031384 	break;
14041385 	case FW_WOW_V2_MAGIC_PKT_EVENT:
14051386 		ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1406
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1407
-			 "It's a magic packet event!\n");
1387
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1388
+			"It's a magic packet event!\n");
14081389 		break;
14091390 	case FW_WOW_V2_UNICAST_PKT_EVENT:
14101391 		ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1411
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1412
-			 "It's an unicast packet event!\n");
1392
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1393
+			"It's an unicast packet event!\n");
14131394 		break;
14141395 	case FW_WOW_V2_PATTERN_PKT_EVENT:
14151396 		ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1416
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1417
-			 "It's a pattern match event!\n");
1397
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1398
+			"It's a pattern match event!\n");
14181399 		break;
14191400 	case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
14201401 		ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1421
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1422
-			 "It's an RTD3 Ssid match event!\n");
1402
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1403
+			"It's an RTD3 Ssid match event!\n");
14231404 		break;
14241405 	case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
14251406 		ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1426
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1427
-			 "It's an RealWoW wake packet event!\n");
1407
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1408
+			"It's an RealWoW wake packet event!\n");
14281409 		break;
14291410 	case FW_WOW_V2_REALWOW_V2_ACKLOST:
14301411 		ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1431
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1432
-			 "It's an RealWoW ack lost event!\n");
1412
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1413
+			"It's an RealWoW ack lost event!\n");
14331414 		break;
14341415 	default:
1435
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1436
-			 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1437
-			  fw_reason);
1416
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1417
+			"WOL Read 0x1c7 = %02X, Unknown reason!\n",
1418
+			fw_reason);
14381419 		break;
14391420 	}
14401421 }
....@@ -1506,9 +1487,9 @@
15061487 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
15071488 				      (u8 *)(&support_remote_wakeup));
15081489 
1509
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1510
-		 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1511
-		  boundary, npq_rqpn_value, rqpn_val);
1490
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1491
+		"boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1492
+		boundary, npq_rqpn_value, rqpn_val);
15121493 
15131494 	/* stop PCIe DMA
15141495 	 * 1. 0x301[7:0] = 0xFE */
....@@ -1522,12 +1503,12 @@
15221503 		tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
15231504 		count++;
15241505 		if ((count % 200) == 0) {
1525
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1526
-				 "Tx queue is not empty for 20ms!\n");
1506
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1507
+				"Tx queue is not empty for 20ms!\n");
15271508 		}
15281509 		if (count >= 1000) {
1529
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1530
-				 "Wait for Tx FIFO empty timeout!\n");
1510
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1511
+				"Wait for Tx FIFO empty timeout!\n");
15311512 			break;
15321513 		}
15331514 	}
....@@ -1543,8 +1524,8 @@
15431524 		udelay(100);
15441525 		count++;
15451526 		if (count >= 500) {
1546
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1547
-				 "Wait for TX State Machine ready timeout !!\n");
1527
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1528
+				"Wait for TX State Machine ready timeout !!\n");
15481529 			break;
15491530 		}
15501531 	}
....@@ -1562,9 +1543,9 @@
15621543 		count++;
15631544 	} while (!(tmp & BIT(1)) && count < 100);
15641545 
1565
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1566
-		 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1567
-		  count, tmp);
1546
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1547
+		"Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1548
+		count, tmp);
15681549 
15691550 	/* reset BB
15701551 	 * 7.	0x02 [0] = 0 */
....@@ -1621,8 +1602,8 @@
16211602 	/* init LLT
16221603 	 * 17. init LLT */
16231604 	if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1624
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1625
-			 "Failed to init LLT table!\n");
1605
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
1606
+			"Failed to init LLT table!\n");
16261607 		return false;
16271608 	}
16281609 
....@@ -1642,7 +1623,7 @@
16421623 	tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
16431624 	rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
16441625 
1645
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1626
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
16461627 	return ret;
16471628 }
16481629 
....@@ -1677,12 +1658,12 @@
16771658 	u8 tmp  = 0;
16781659 	struct rtl_priv *rtlpriv = rtl_priv(hw);
16791660 
1680
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1661
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
16811662 
16821663 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
16831664 	if (!(tmp & (BIT(2) | BIT(3)))) {
1684
-		RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1685
-			 "0x160(%#x)return!!\n", tmp);
1665
+		rtl_dbg(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1666
+			"0x160(%#x)return!!\n", tmp);
16861667 		return;
16871668 	}
16881669 
....@@ -1692,7 +1673,7 @@
16921673 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
16931674 	_rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
16941675 
1695
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1676
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
16961677 }
16971678 
16981679 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
....@@ -1700,13 +1681,13 @@
17001681 	u8 tmp  = 0;
17011682 	struct rtl_priv *rtlpriv = rtl_priv(hw);
17021683 
1703
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1684
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
17041685 
17051686 	/* Check 0x98[10] */
17061687 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
17071688 	if (!(tmp & BIT(2))) {
1708
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1709
-			 "<---0x99(%#x) return!!\n", tmp);
1689
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1690
+			"<---0x99(%#x) return!!\n", tmp);
17101691 		return;
17111692 	}
17121693 
....@@ -1723,7 +1704,7 @@
17231704 	rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
17241705 	rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
17251706 
1726
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1707
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
17271708 }
17281709 
17291710 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
....@@ -1746,14 +1727,14 @@
17461727 
17471728 	/* Release Pcie Interface Rx DMA to allow wake packet DMA. */
17481729 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1749
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1730
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
17501731 
17511732 	/* Check wake up event.
17521733 	 * We should check wake packet bit before disable wowlan by H2C or
17531734 	 * Fw will clear the bit. */
17541735 	tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1755
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1756
-		 "Read REG_FTISR 0x13f = %#X\n", tmp);
1736
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1737
+		"Read REG_FTISR 0x13f = %#X\n", tmp);
17571738 
17581739 	/* Set the WoWLAN related function control disable. */
17591740 	rtl8821ae_set_fw_wowlan_mode(hw, false);
....@@ -1818,7 +1799,7 @@
18181799 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
18191800 		/* Combo (PCIe + USB) Card and PCIe-MF Card */
18201801 		/* 1. Run LPS WL RFOFF flow */
1821
-		/* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1802
+		/* rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
18221803 		"=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
18231804 		*/
18241805 		rtl_hal_pwrseqcmdparsing(rtlpriv,
....@@ -1884,8 +1865,8 @@
18841865 	tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
18851866 	if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
18861867 		rtlhal->mac_func_enable = true;
1887
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1888
-			 "MAC has already power on.\n");
1868
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1869
+			"MAC has already power on.\n");
18891870 	} else {
18901871 		rtlhal->mac_func_enable = false;
18911872 		rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
....@@ -1917,7 +1898,7 @@
19171898 	}
19181899 
19191900 	rtstatus = _rtl8821ae_init_mac(hw);
1920
-	if (rtstatus != true) {
1901
+	if (!rtstatus) {
19211902 		pr_err("Init MAC failed\n");
19221903 		err = 1;
19231904 		return err;
....@@ -1929,8 +1910,8 @@
19291910 
19301911 	err = rtl8821ae_download_fw(hw, false);
19311912 	if (err) {
1932
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1933
-			 "Failed to download FW. Init HW without FW now\n");
1913
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1914
+			"Failed to download FW. Init HW without FW now\n");
19341915 		err = 1;
19351916 		rtlhal->fw_ready = false;
19361917 		return err;
....@@ -2009,7 +1990,7 @@
20091990 	rtl8821ae_dm_init(hw);
20101991 	rtl8821ae_macid_initialize_mediastatus(hw);
20111992 
2012
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
1993
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s() <====\n", __func__);
20131994 	return err;
20141995 }
20151996 
....@@ -2022,16 +2003,16 @@
20222003 	u32 value32;
20232004 
20242005 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2025
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2026
-		 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2006
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2007
+		"ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
20272008 
20282009 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
20292010 		rtlphy->rf_type = RF_2T2R;
20302011 	else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
20312012 		rtlphy->rf_type = RF_1T1R;
20322013 
2033
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2034
-		 "RF_Type is %x!!\n", rtlphy->rf_type);
2014
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2015
+		"RF_Type is %x!!\n", rtlphy->rf_type);
20352016 
20362017 	if (value32 & TRP_VAUX_EN) {
20372018 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
....@@ -2071,44 +2052,44 @@
20712052 
20722053 	switch (version) {
20732054 	case VERSION_TEST_CHIP_1T1R_8812:
2074
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2075
-			 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2055
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2056
+			"Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
20762057 		break;
20772058 	case VERSION_TEST_CHIP_2T2R_8812:
2078
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2079
-			 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2059
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2060
+			"Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
20802061 		break;
20812062 	case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2082
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2083
-			 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2063
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2064
+			"Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
20842065 		break;
20852066 	case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2086
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2067
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2068
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
20882069 		break;
20892070 	case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2090
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2071
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2072
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
20922073 		break;
20932074 	case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2094
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2075
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2076
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
20962077 		break;
20972078 	case VERSION_TEST_CHIP_8821:
2098
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099
-			 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2079
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2080
+			"Chip Version ID: VERSION_TEST_CHIP_8821\n");
21002081 		break;
21012082 	case VERSION_NORMAL_TSMC_CHIP_8821:
2102
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2083
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2084
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
21042085 		break;
21052086 	case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2106
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2087
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2088
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
21082089 		break;
21092090 	default:
2110
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111
-			 "Chip Version ID: Unknown (0x%X)\n", version);
2091
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2092
+			"Chip Version ID: Unknown (0x%X)\n", version);
21122093 		break;
21132094 	}
21142095 
....@@ -2124,7 +2105,7 @@
21242105 	bt_msr &= 0xfc;
21252106 
21262107 	rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2127
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2108
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
21282109 		"clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
21292110 
21302111 	if (type == NL80211_IFTYPE_UNSPECIFIED ||
....@@ -2136,33 +2117,33 @@
21362117 		_rtl8821ae_resume_tx_beacon(hw);
21372118 		_rtl8821ae_disable_bcn_sub_func(hw);
21382119 	} else {
2139
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2140
-			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2141
-			 type);
2120
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2121
+			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2122
+			type);
21422123 	}
21432124 
21442125 	switch (type) {
21452126 	case NL80211_IFTYPE_UNSPECIFIED:
21462127 		bt_msr |= MSR_NOLINK;
21472128 		ledaction = LED_CTL_LINK;
2148
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2149
-			 "Set Network type to NO LINK!\n");
2129
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2130
+			"Set Network type to NO LINK!\n");
21502131 		break;
21512132 	case NL80211_IFTYPE_ADHOC:
21522133 		bt_msr |= MSR_ADHOC;
2153
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2154
-			 "Set Network type to Ad Hoc!\n");
2134
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2135
+			"Set Network type to Ad Hoc!\n");
21552136 		break;
21562137 	case NL80211_IFTYPE_STATION:
21572138 		bt_msr |= MSR_INFRA;
21582139 		ledaction = LED_CTL_LINK;
2159
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2160
-			 "Set Network type to STA!\n");
2140
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2141
+			"Set Network type to STA!\n");
21612142 		break;
21622143 	case NL80211_IFTYPE_AP:
21632144 		bt_msr |= MSR_AP;
2164
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2165
-			 "Set Network type to AP!\n");
2145
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2146
+			"Set Network type to AP!\n");
21662147 		break;
21672148 	default:
21682149 		pr_err("Network type %d not support!\n", type);
....@@ -2205,7 +2186,7 @@
22052186 {
22062187 	struct rtl_priv *rtlpriv = rtl_priv(hw);
22072188 
2208
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2189
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s!\n", __func__);
22092190 
22102191 	if (_rtl8821ae_set_media_status(hw, type))
22112192 		return -EOPNOTSUPP;
....@@ -2305,16 +2286,16 @@
23052286 	 * offset 0x34 from the Function Header */
23062287 
23072288 	pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2308
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2309
-		 "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2289
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2290
+		"PCI configuration 0x34 = 0x%2x\n", cap_pointer);
23102291 
23112292 	do {
23122293 		pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
23132294 		cap_id = cap_hdr & 0xFF;
23142295 
2315
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2316
-			 "in pci configuration, cap_pointer%x = %x\n",
2317
-			  cap_pointer, cap_id);
2296
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2297
+			"in pci configuration, cap_pointer%x = %x\n",
2298
+			cap_pointer, cap_id);
23182299 
23192300 		if (cap_id == 0x01) {
23202301 			break;
....@@ -2344,17 +2325,17 @@
23442325 			/* Read it back to check */
23452326 			pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
23462327 					     &pmcs_reg);
2347
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2348
-				 "Clear PME status 0x%2x to 0x%2x\n",
2349
-				  cap_pointer + 5, pmcs_reg);
2328
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2329
+				"Clear PME status 0x%2x to 0x%2x\n",
2330
+				cap_pointer + 5, pmcs_reg);
23502331 		} else {
2351
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2352
-				 "PME status(0x%2x) = 0x%2x\n",
2353
-				  cap_pointer + 5, pmcs_reg);
2332
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2333
+				"PME status(0x%2x) = 0x%2x\n",
2334
+				cap_pointer + 5, pmcs_reg);
23542335 		}
23552336 	} else {
2356
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2357
-			 "Cannot find PME Capability\n");
2337
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
2338
+			"Cannot find PME Capability\n");
23582339 	}
23592340 }
23602341 
....@@ -2376,13 +2357,13 @@
23762357 
23772358 	if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
23782359 	    || !rtlhal->enter_pnp_sleep) {
2379
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2360
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
23802361 		mac->link_state = MAC80211_NOLINK;
23812362 		opmode = NL80211_IFTYPE_UNSPECIFIED;
23822363 		_rtl8821ae_set_media_status(hw, opmode);
23832364 		_rtl8821ae_poweroff_adapter(hw);
23842365 	} else {
2385
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2366
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
23862367 		/* 3 <1> Prepare for configuring wowlan related infomations */
23872368 		/* Clear Fw WoWLAN event. */
23882369 		rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
....@@ -2432,9 +2413,9 @@
24322413 			udelay(10);
24332414 			tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
24342415 		}
2435
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2436
-			 "Wait Rx DMA Finished before host sleep. count=%d\n",
2437
-			  count);
2416
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2417
+			"Wait Rx DMA Finished before host sleep. count=%d\n",
2418
+			count);
24382419 
24392420 		/* reset trx ring */
24402421 		rtlpriv->intf_ops->reset_trx_ring(hw);
....@@ -2460,7 +2441,7 @@
24602441 
24612442 		/* Stop Pcie Interface Tx DMA. */
24622443 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2463
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2444
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
24642445 
24652446 		/* Wait for TxDMA idle. */
24662447 		count = 0;
....@@ -2469,9 +2450,9 @@
24692450 			udelay(10);
24702451 			count++;
24712452 		} while ((tmp != 0) && (count < 100));
2472
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2473
-			 "Wait Tx DMA Finished before host sleep. count=%d\n",
2474
-			  count);
2453
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2454
+			"Wait Tx DMA Finished before host sleep. count=%d\n",
2455
+			count);
24752456 
24762457 		if (rtlhal->hw_rof_enable) {
24772458 			printk("hw_rof_enable\n");
....@@ -2523,8 +2504,8 @@
25232504 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
25242505 	u16 bcn_interval = mac->beacon_interval;
25252506 
2526
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2527
-		 "beacon_interval:%d\n", bcn_interval);
2507
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
2508
+		"beacon_interval:%d\n", bcn_interval);
25282509 	rtl8821ae_disable_interrupt(hw);
25292510 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
25302511 	rtl8821ae_enable_interrupt(hw);
....@@ -2536,8 +2517,8 @@
25362517 	struct rtl_priv *rtlpriv = rtl_priv(hw);
25372518 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
25382519 
2539
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2540
-		 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2520
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
2521
+		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
25412522 
25422523 	if (add_msr)
25432524 		rtlpci->irq_mask[0] |= add_msr;
....@@ -2606,50 +2587,50 @@
26062587 	u8 *hwinfo)
26072588 {
26082589 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2609
-	u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2590
+	u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0;
26102591 
2611
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2612
-		 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2613
-		 (eeAddr+1), hwinfo[eeAddr+1]);
2614
-	if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2592
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2593
+		"hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2594
+		(eeaddr + 1), hwinfo[eeaddr + 1]);
2595
+	if (hwinfo[eeaddr + 1] == 0xFF)  /*YJ,add,120316*/
26152596 		autoload_fail = true;
26162597 
26172598 	if (autoload_fail) {
2618
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2619
-			 "auto load fail : Use Default value!\n");
2620
-		for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2599
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2600
+			"auto load fail : Use Default value!\n");
2601
+		for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
26212602 			/*2.4G default value*/
26222603 			for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2623
-				pwrinfo24g->index_cck_base[rfPath][group] =	0x2D;
2624
-				pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2604
+				pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2605
+				pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
26252606 			}
2626
-			for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2627
-				if (TxCount == 0) {
2628
-					pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2629
-					pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2607
+			for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2608
+				if (txcount == 0) {
2609
+					pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
2610
+					pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
26302611 				} else {
2631
-					pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2632
-					pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2633
-					pwrinfo24g->cck_diff[rfPath][TxCount] =	0xFE;
2634
-					pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2612
+					pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE;
2613
+					pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE;
2614
+					pwrinfo24g->cck_diff[rfpath][txcount] =	0xFE;
2615
+					pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE;
26352616 				}
26362617 			}
26372618 			/*5G default value*/
26382619 			for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2639
-				pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2620
+				pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A;
26402621 
2641
-			for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2642
-				if (TxCount == 0) {
2643
-					pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2644
-					pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2645
-					pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2646
-					pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2622
+			for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2623
+				if (txcount == 0) {
2624
+					pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
2625
+					pwrinfo5g->bw20_diff[rfpath][0] = 0x00;
2626
+					pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2627
+					pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
26472628 				} else {
2648
-					pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2649
-					pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2650
-					pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2651
-					pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2652
-					pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2629
+					pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE;
2630
+					pwrinfo5g->bw20_diff[rfpath][0] = 0xFE;
2631
+					pwrinfo5g->bw40_diff[rfpath][0] = 0xFE;
2632
+					pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2633
+					pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
26532634 				}
26542635 			}
26552636 		}
....@@ -2658,112 +2639,112 @@
26582639 
26592640 	rtl_priv(hw)->efuse.txpwr_fromeprom = true;
26602641 
2661
-	for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2642
+	for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
26622643 		/*2.4G default value*/
26632644 		for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2664
-			pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2665
-			if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2666
-				pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2645
+			pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++];
2646
+			if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
2647
+				pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
26672648 		}
26682649 		for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2669
-			pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2670
-			if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2671
-				pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2650
+			pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2651
+			if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
2652
+				pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
26722653 		}
2673
-		for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2674
-			if (TxCount == 0) {
2675
-				pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2654
+		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2655
+			if (txcount == 0) {
2656
+				pwrinfo24g->bw40_diff[rfpath][txcount] = 0;
26762657 				/*bit sign number to 8 bit sign number*/
2677
-				pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2678
-				if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2679
-					pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2658
+				pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2659
+				if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2660
+					pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
26802661 				/*bit sign number to 8 bit sign number*/
2681
-				pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2682
-				if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2683
-					pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2662
+				pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2663
+				if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2664
+					pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
26842665 
2685
-				pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2686
-				eeAddr++;
2666
+				pwrinfo24g->cck_diff[rfpath][txcount] = 0;
2667
+				eeaddr++;
26872668 			} else {
2688
-				pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2689
-				if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2690
-					pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2669
+				pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2670
+				if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3))
2671
+					pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0;
26912672 
2692
-				pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2693
-				if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2694
-					pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2673
+				pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2674
+				if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2675
+					pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
26952676 
2696
-				eeAddr++;
2677
+				eeaddr++;
26972678 
2698
-				pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2699
-				if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2700
-					pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2679
+				pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2680
+				if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2681
+					pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
27012682 
2702
-				pwrinfo24g->cck_diff[rfPath][TxCount] =	(hwinfo[eeAddr] & 0x0f);
2703
-				if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2704
-					pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2683
+				pwrinfo24g->cck_diff[rfpath][txcount] =	(hwinfo[eeaddr] & 0x0f);
2684
+				if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3))
2685
+					pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0;
27052686 
2706
-				eeAddr++;
2687
+				eeaddr++;
27072688 			}
27082689 		}
27092690 
27102691 		/*5G default value*/
27112692 		for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2712
-			pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2713
-			if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2714
-				pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2693
+			pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2694
+			if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
2695
+				pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE;
27152696 		}
27162697 
2717
-		for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2718
-			if (TxCount == 0) {
2719
-				pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2698
+		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2699
+			if (txcount == 0) {
2700
+				pwrinfo5g->bw40_diff[rfpath][txcount] = 0;
27202701 
2721
-				pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2722
-				if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2723
-					pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2702
+				pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4;
2703
+				if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2704
+					pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
27242705 
2725
-				pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2726
-				if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2727
-					pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2706
+				pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f);
2707
+				if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2708
+					pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
27282709 
2729
-				eeAddr++;
2710
+				eeaddr++;
27302711 			} else {
2731
-				pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2732
-				if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2733
-					pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2712
+				pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2713
+				if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3))
2714
+					pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0;
27342715 
2735
-				pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2736
-				if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2737
-					pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2716
+				pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2717
+				if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2718
+					pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
27382719 
2739
-				eeAddr++;
2720
+				eeaddr++;
27402721 			}
27412722 		}
27422723 
2743
-		pwrinfo5g->ofdm_diff[rfPath][1] =	(hwinfo[eeAddr] & 0xf0) >> 4;
2744
-		pwrinfo5g->ofdm_diff[rfPath][2] =	(hwinfo[eeAddr] & 0x0f);
2724
+		pwrinfo5g->ofdm_diff[rfpath][1] =	(hwinfo[eeaddr] & 0xf0) >> 4;
2725
+		pwrinfo5g->ofdm_diff[rfpath][2] =	(hwinfo[eeaddr] & 0x0f);
27452726 
2746
-		eeAddr++;
2727
+		eeaddr++;
27472728 
2748
-		pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2729
+		pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f);
27492730 
2750
-		eeAddr++;
2731
+		eeaddr++;
27512732 
2752
-		for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2753
-			if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2754
-				pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2733
+		for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) {
2734
+			if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2735
+				pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
27552736 		}
2756
-		for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2757
-			pwrinfo5g->bw80_diff[rfPath][TxCount] =	(hwinfo[eeAddr] & 0xf0) >> 4;
2737
+		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2738
+			pwrinfo5g->bw80_diff[rfpath][txcount] =	(hwinfo[eeaddr] & 0xf0) >> 4;
27582739 			/* 4bit sign number to 8 bit sign number */
2759
-			if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2760
-				pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2740
+			if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3))
2741
+				pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0;
27612742 			/* 4bit sign number to 8 bit sign number */
2762
-			pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2763
-			if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2764
-				pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2743
+			pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2744
+			if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3))
2745
+				pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0;
27652746 
2766
-			eeAddr++;
2747
+			eeaddr++;
27672748 		}
27682749 	}
27692750 }
....@@ -2930,8 +2911,8 @@
29302911 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
29312912 
29322913 	if (!autoload_fail) {
2933
-		rtlhal->pa_type_2g = hwinfo[0xBC];
2934
-		rtlhal->lna_type_2g = hwinfo[0xBD];
2914
+		rtlhal->pa_type_2g = hwinfo[0XBC];
2915
+		rtlhal->lna_type_2g = hwinfo[0XBD];
29352916 		if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
29362917 			rtlhal->pa_type_2g = 0;
29372918 			rtlhal->lna_type_2g = 0;
....@@ -2943,8 +2924,8 @@
29432924 					   (rtlhal->lna_type_2g & BIT(3))) ?
29442925 					  1 : 0;
29452926 
2946
-		rtlhal->pa_type_5g = hwinfo[0xBC];
2947
-		rtlhal->lna_type_5g = hwinfo[0xBF];
2927
+		rtlhal->pa_type_5g = hwinfo[0XBC];
2928
+		rtlhal->lna_type_5g = hwinfo[0XBF];
29482929 		if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
29492930 			rtlhal->pa_type_5g = 0;
29502931 			rtlhal->lna_type_5g = 0;
....@@ -2969,18 +2950,18 @@
29692950 	struct rtl_priv *rtlpriv = rtl_priv(hw);
29702951 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
29712952 
2972
-	u8 ext_type_pa_2g_a  = (hwinfo[0xBD] & BIT(2))      >> 2; /* 0xBD[2] */
2973
-	u8 ext_type_pa_2g_b  = (hwinfo[0xBD] & BIT(6))      >> 6; /* 0xBD[6] */
2974
-	u8 ext_type_pa_5g_a  = (hwinfo[0xBF] & BIT(2))      >> 2; /* 0xBF[2] */
2975
-	u8 ext_type_pa_5g_b  = (hwinfo[0xBF] & BIT(6))      >> 6; /* 0xBF[6] */
2976
-	/* 0xBD[1:0] */
2977
-	u8 ext_type_lna_2g_a = (hwinfo[0xBD] & (BIT(1) | BIT(0))) >> 0;
2978
-	/* 0xBD[5:4] */
2979
-	u8 ext_type_lna_2g_b = (hwinfo[0xBD] & (BIT(5) | BIT(4))) >> 4;
2980
-	/* 0xBF[1:0] */
2981
-	u8 ext_type_lna_5g_a = (hwinfo[0xBF] & (BIT(1) | BIT(0))) >> 0;
2982
-	/* 0xBF[5:4] */
2983
-	u8 ext_type_lna_5g_b = (hwinfo[0xBF] & (BIT(5) | BIT(4))) >> 4;
2953
+	u8 ext_type_pa_2g_a  = (hwinfo[0XBD] & BIT(2))      >> 2; /* 0XBD[2] */
2954
+	u8 ext_type_pa_2g_b  = (hwinfo[0XBD] & BIT(6))      >> 6; /* 0XBD[6] */
2955
+	u8 ext_type_pa_5g_a  = (hwinfo[0XBF] & BIT(2))      >> 2; /* 0XBF[2] */
2956
+	u8 ext_type_pa_5g_b  = (hwinfo[0XBF] & BIT(6))      >> 6; /* 0XBF[6] */
2957
+	/* 0XBD[1:0] */
2958
+	u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0;
2959
+	/* 0XBD[5:4] */
2960
+	u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4;
2961
+	/* 0XBF[1:0] */
2962
+	u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0;
2963
+	/* 0XBF[5:4] */
2964
+	u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4;
29842965 
29852966 	_rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
29862967 
....@@ -3008,8 +2989,8 @@
30082989 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
30092990 
30102991 	if (!autoload_fail) {
3011
-		rtlhal->pa_type_2g = hwinfo[0xBC];
3012
-		rtlhal->lna_type_2g = hwinfo[0xBD];
2992
+		rtlhal->pa_type_2g = hwinfo[0XBC];
2993
+		rtlhal->lna_type_2g = hwinfo[0XBD];
30132994 		if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
30142995 			rtlhal->pa_type_2g = 0;
30152996 			rtlhal->lna_type_2g = 0;
....@@ -3017,8 +2998,8 @@
30172998 		rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
30182999 		rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
30193000 
3020
-		rtlhal->pa_type_5g = hwinfo[0xBC];
3021
-		rtlhal->lna_type_5g = hwinfo[0xBF];
3001
+		rtlhal->pa_type_5g = hwinfo[0XBC];
3002
+		rtlhal->lna_type_5g = hwinfo[0XBF];
30223003 		if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
30233004 			rtlhal->pa_type_5g = 0;
30243005 			rtlhal->lna_type_5g = 0;
....@@ -3070,8 +3051,8 @@
30703051 		rtlhal->rfe_type = 0x04;
30713052 	}
30723053 
3073
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3074
-		 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3054
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3055
+		"RFE Type: 0x%2x\n", rtlhal->rfe_type);
30753056 }
30763057 
30773058 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
....@@ -3175,8 +3156,8 @@
31753156 		rtlefuse->board_type |= ODM_BOARD_BT;
31763157 
31773158 	rtlhal->board_type = rtlefuse->board_type;
3178
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3179
-		 "board_type = 0x%x\n", rtlefuse->board_type);
3159
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3160
+		"board_type = 0x%x\n", rtlefuse->board_type);
31803161 
31813162 	rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
31823163 	if (rtlefuse->eeprom_channelplan == 0xff)
....@@ -3198,8 +3179,8 @@
31983179 	}
31993180 
32003181 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3201
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3202
-		 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3182
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3183
+		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
32033184 
32043185 	if (!rtlefuse->autoload_failflag) {
32053186 		rtlefuse->antenna_div_cfg =
....@@ -3219,7 +3200,7 @@
32193200 		rtlefuse->antenna_div_type = 0;
32203201 	}
32213202 
3222
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3203
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
32233204 		"SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
32243205 		rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
32253206 
....@@ -3268,8 +3249,8 @@
32683249 	default:
32693250 		break;
32703251 	}
3271
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3272
-		 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3252
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
3253
+		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
32733254 }*/
32743255 
32753256 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
....@@ -3286,20 +3267,20 @@
32863267 	else
32873268 		rtlpriv->dm.rfpath_rxenable[0] =
32883269 		    rtlpriv->dm.rfpath_rxenable[1] = true;
3289
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3290
-						rtlhal->version);
3270
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3271
+		rtlhal->version);
32913272 
32923273 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
32933274 	if (tmp_u1b & BIT(4)) {
3294
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3275
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
32953276 		rtlefuse->epromtype = EEPROM_93C46;
32963277 	} else {
3297
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3278
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
32983279 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
32993280 	}
33003281 
33013282 	if (tmp_u1b & BIT(5)) {
3302
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3283
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
33033284 		rtlefuse->autoload_failflag = false;
33043285 		_rtl8821ae_read_adapter_info(hw, false);
33053286 	} else {
....@@ -3400,8 +3381,8 @@
34003381 
34013382 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
34023383 
3403
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3404
-		 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3384
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3385
+		"%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
34053386 }
34063387 
34073388 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
....@@ -3546,8 +3527,8 @@
35463527 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
35473528 	wirelessmode = sta_entry->wireless_mode;
35483529 
3549
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3550
-		 "wireless mode = 0x%x\n", wirelessmode);
3530
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3531
+		"wireless mode = 0x%x\n", wirelessmode);
35513532 	if (mac->opmode == NL80211_IFTYPE_STATION ||
35523533 		mac->opmode == NL80211_IFTYPE_MESH_POINT) {
35533534 		curtxbw_40mhz = mac->bw_40;
....@@ -3697,8 +3678,8 @@
36973678 	ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
36983679 							ratr_bitmap);
36993680 
3700
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3701
-		 "ratr_bitmap :%x\n", ratr_bitmap);
3681
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3682
+		"ratr_bitmap :%x\n", ratr_bitmap);
37023683 
37033684 	/* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
37043685 				       (ratr_index << 28)); */
....@@ -3714,10 +3695,10 @@
37143695 	rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
37153696 	rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
37163697 
3717
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3718
-		 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3719
-		 ratr_index, ratr_bitmap,
3720
-		 rate_mask[0], rate_mask[1],
3698
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3699
+		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3700
+		ratr_index, ratr_bitmap,
3701
+		rate_mask[0], rate_mask[1],
37213702 		 rate_mask[2], rate_mask[3],
37223703 		 rate_mask[4], rate_mask[5],
37233704 		 rate_mask[6]);
....@@ -3732,7 +3713,7 @@
37323713 	if (rtlpriv->dm.useramask)
37333714 		rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
37343715 	else
3735
-		/*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3716
+		/*rtl_dbg(rtlpriv, COMP_RATR,DBG_LOUD,
37363717 			   "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
37373718 		rtl8821ae_update_hal_rate_table(hw, sta);
37383719 }
....@@ -3804,16 +3785,16 @@
38043785 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
38053786 
38063787 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3807
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3808
-			 "GPIOChangeRF  - HW Radio ON, RF ON\n");
3788
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3789
+			"GPIOChangeRF  - HW Radio ON, RF ON\n");
38093790 
38103791 		e_rfpowerstate_toset = ERFON;
38113792 		ppsc->hwradiooff = false;
38123793 		b_actuallyset = true;
38133794 	} else if ((!ppsc->hwradiooff)
38143795 		   && (e_rfpowerstate_toset == ERFOFF)) {
3815
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3816
-			 "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3796
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3797
+			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
38173798 
38183799 		e_rfpowerstate_toset = ERFOFF;
38193800 		ppsc->hwradiooff = true;
....@@ -3863,7 +3844,7 @@
38633844 		u8 cam_offset = 0;
38643845 		u8 clear_number = 5;
38653846 
3866
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3847
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
38673848 
38683849 		for (idx = 0; idx < clear_number; idx++) {
38693850 			rtl_cam_mark_invalid(hw, cam_offset + idx);
....@@ -3890,8 +3871,8 @@
38903871 			enc_algo = CAM_AES;
38913872 			break;
38923873 		default:
3893
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3894
-				 "switch case %#x not processed\n", enc_algo);
3874
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3875
+				"switch case %#x not processed\n", enc_algo);
38953876 			enc_algo = CAM_TKIP;
38963877 			break;
38973878 		}
....@@ -3920,26 +3901,26 @@
39203901 		}
39213902 
39223903 		if (rtlpriv->sec.key_len[key_index] == 0) {
3923
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3924
-				 "delete one entry, entry_id is %d\n",
3925
-				 entry_id);
3904
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3905
+				"delete one entry, entry_id is %d\n",
3906
+				entry_id);
39263907 			if (mac->opmode == NL80211_IFTYPE_AP)
39273908 				rtl_cam_del_entry(hw, p_macaddr);
39283909 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
39293910 		} else {
3930
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3931
-				 "add one entry\n");
3911
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3912
+				"add one entry\n");
39323913 			if (is_pairwise) {
3933
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3934
-					 "set Pairwise key\n");
3914
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3915
+					"set Pairwise key\n");
39353916 
39363917 				rtl_cam_add_one_entry(hw, macaddr, key_index,
39373918 						      entry_id, enc_algo,
39383919 						      CAM_CONFIG_NO_USEDK,
39393920 						      rtlpriv->sec.key_buf[key_index]);
39403921 			} else {
3941
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3942
-					 "set group key\n");
3922
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3923
+					"set group key\n");
39433924 
39443925 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
39453926 					rtl_cam_add_one_entry(hw,
....@@ -4004,7 +3985,7 @@
40043985 	if (write_into_reg)
40053986 		rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
40063987 
4007
-	RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
3988
+	rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
40083989 		"receive_config=0x%08X, write_into_reg=%d\n",
40093990 		rtlpci->receive_config, write_into_reg);
40103991 }
....@@ -4033,10 +4014,10 @@
40334014 	rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
40344015 	for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
40354016 		/* Set Rx packet buffer offset.
4036
-		 * RxBufer pointer increases 1,
4017
+		 * RXBufer pointer increases 1,
40374018 		 * we can access 8 bytes in Rx packet buffer.
40384019 		 * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4039
-		 * RxBufer addr = (CAM start offset +
4020
+		 * RXBufer addr = (CAM start offset +
40404021 		 *                 per entry offset of a WKFM CAM)/8
40414022 		 *	* index: The index of the wake up frame mask
40424023 		 *	* WKFMCAM_SIZE: the total size of one WKFM CAM
....@@ -4057,9 +4038,9 @@
40574038 				cam |= BIT(26);
40584039 
40594040 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4060
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4061
-				 "WRITE entry[%d] 0x%x: %x\n", addr,
4062
-				  REG_PKTBUF_DBG_DATA_L, cam);
4041
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4042
+				"WRITE entry[%d] 0x%x: %x\n", addr,
4043
+				REG_PKTBUF_DBG_DATA_L, cam);
40634044 
40644045 			/* Write to Rx packet buffer. */
40654046 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
....@@ -4067,18 +4048,18 @@
40674048 			cam = rtl_pattern->mask[addr - 2];
40684049 
40694050 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4070
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4071
-				 "WRITE entry[%d] 0x%x: %x\n", addr,
4072
-				  REG_PKTBUF_DBG_DATA_L, cam);
4051
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4052
+				"WRITE entry[%d] 0x%x: %x\n", addr,
4053
+				REG_PKTBUF_DBG_DATA_L, cam);
40734054 
40744055 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
40754056 		} else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
40764057 			cam = rtl_pattern->mask[addr - 2];
40774058 
40784059 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4079
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4080
-				 "WRITE entry[%d] 0x%x: %x\n", addr,
4081
-				  REG_PKTBUF_DBG_DATA_H, cam);
4060
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4061
+				"WRITE entry[%d] 0x%x: %x\n", addr,
4062
+				REG_PKTBUF_DBG_DATA_H, cam);
40824063 
40834064 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
40844065 		}