update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/net/phy/mscc/mscc_main.c
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@@ -527,14 +527,27 @@
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  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
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  *    clock transitions at 1000 Mbps) if delays should be enabled
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  */
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-static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
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-				   u16 rgmii_rx_delay_mask,
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-				   u16 rgmii_tx_delay_mask)
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+static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl,
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+				     u16 rgmii_rx_delay_mask,
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+				     u16 rgmii_tx_delay_mask)
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 {
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 	u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
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 	u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
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 	u16 reg_val = 0;
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-	int rc;
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+	u16 mask = 0;
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+	int rc = 0;
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+
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+	/* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit
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+	 * to be unset for all PHY modes, so do that as part of the paged
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+	 * register modification.
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+	 * For some family members (like VSC8530/31/40/41) this bit is reserved
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+	 * and read-only, and the RX clock is enabled by default.
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+	 */
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+	if (rgmii_cntl == VSC8502_RGMII_CNTL)
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+		mask |= VSC8502_RGMII_RX_CLK_DISABLE;
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+
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+	if (phy_interface_is_rgmii(phydev))
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+		mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask;
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 	mutex_lock(&phydev->lock);
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@@ -545,10 +558,9 @@
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 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
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-	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
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-			      rgmii_cntl,
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-			      rgmii_rx_delay_mask | rgmii_tx_delay_mask,
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-			      reg_val);
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+	if (mask)
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+		rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
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+				      rgmii_cntl, mask, reg_val);
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 	mutex_unlock(&phydev->lock);
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@@ -557,19 +569,11 @@
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 static int vsc85xx_default_config(struct phy_device *phydev)
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 {
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-	int rc;
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-
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 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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-	if (phy_interface_mode_is_rgmii(phydev->interface)) {
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-		rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL,
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-					     VSC8502_RGMII_RX_DELAY_MASK,
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-					     VSC8502_RGMII_TX_DELAY_MASK);
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-		if (rc)
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-			return rc;
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-	}
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-
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-	return 0;
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+	return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL,
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+					 VSC8502_RGMII_RX_DELAY_MASK,
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+					 VSC8502_RGMII_TX_DELAY_MASK);
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 }
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 static int vsc85xx_get_tunable(struct phy_device *phydev,
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@@ -1646,13 +1650,11 @@
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 	if (ret)
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 		return ret;
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-	if (phy_interface_is_rgmii(phydev)) {
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-		ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL,
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-					      VSC8572_RGMII_RX_DELAY_MASK,
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-					      VSC8572_RGMII_TX_DELAY_MASK);
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-		if (ret)
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-			return ret;
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-	}
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+	ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL,
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+					VSC8572_RGMII_RX_DELAY_MASK,
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+					VSC8572_RGMII_TX_DELAY_MASK);
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+	if (ret)
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+		return ret;
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 	ret = genphy_soft_reset(phydev);
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 	if (ret)
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@@ -2563,6 +2565,7 @@
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 module_phy_driver(vsc85xx_driver);
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 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
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+	{ PHY_ID_VSC8502, 0xfffffff0, },
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 	{ PHY_ID_VSC8504, 0xfffffff0, },
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 	{ PHY_ID_VSC8514, 0xfffffff0, },
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 	{ PHY_ID_VSC8530, 0xfffffff0, },