update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/net/mdio/mdio-mux-meson-g12a.c
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@@ -4,6 +4,7 @@
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  */
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 #include <linux/bitfield.h>
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+#include <linux/delay.h>
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 #include <linux/clk.h>
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 #include <linux/clk-provider.h>
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 #include <linux/device.h>
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@@ -150,6 +151,7 @@
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 static int g12a_enable_internal_mdio(struct g12a_mdio_mux *priv)
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 {
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+	u32 value;
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 	int ret;
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 	/* Enable the phy clock */
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@@ -163,18 +165,25 @@
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 	/* Initialize ephy control */
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 	writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);
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-	writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
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-	       FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
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-	       FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
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-	       PHY_CNTL1_CLK_EN |
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-	       PHY_CNTL1_CLKFREQ |
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-	       PHY_CNTL1_PHY_ENB,
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-	       priv->regs + ETH_PHY_CNTL1);
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+
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+	/* Make sure we get a 0 -> 1 transition on the enable bit */
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+	value = FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
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+		FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
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+		FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
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+		PHY_CNTL1_CLK_EN |
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+		PHY_CNTL1_CLKFREQ;
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+	writel(value, priv->regs + ETH_PHY_CNTL1);
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 	writel(PHY_CNTL2_USE_INTERNAL |
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 	       PHY_CNTL2_SMI_SRC_MAC |
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 	       PHY_CNTL2_RX_CLK_EPHY,
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 	       priv->regs + ETH_PHY_CNTL2);
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+	value |= PHY_CNTL1_PHY_ENB;
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+	writel(value, priv->regs + ETH_PHY_CNTL1);
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+
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+	/* The phy needs a bit of time to power up */
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+	mdelay(10);
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+
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 	return 0;
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 }
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