.. | .. |
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18 | 18 | MLXSW_RES_ID_CQE_V1, |
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19 | 19 | MLXSW_RES_ID_CQE_V2, |
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20 | 20 | MLXSW_RES_ID_COUNTER_POOL_SIZE, |
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| 21 | + MLXSW_RES_ID_COUNTER_BANK_SIZE, |
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21 | 22 | MLXSW_RES_ID_MAX_SPAN, |
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22 | 23 | MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES, |
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23 | 24 | MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC, |
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24 | 25 | MLXSW_RES_ID_MAX_SYSTEM_PORT, |
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25 | 26 | MLXSW_RES_ID_MAX_LAG, |
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26 | 27 | MLXSW_RES_ID_MAX_LAG_MEMBERS, |
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27 | | - MLXSW_RES_ID_MAX_BUFFER_SIZE, |
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| 28 | + MLXSW_RES_ID_LOCAL_PORTS_IN_1X, |
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| 29 | + MLXSW_RES_ID_LOCAL_PORTS_IN_2X, |
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| 30 | + MLXSW_RES_ID_LOCAL_PORTS_IN_4X, |
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| 31 | + MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER, |
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28 | 32 | MLXSW_RES_ID_CELL_SIZE, |
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| 33 | + MLXSW_RES_ID_MAX_HEADROOM_SIZE, |
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29 | 34 | MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS, |
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30 | 35 | MLXSW_RES_ID_ACL_MAX_TCAM_RULES, |
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31 | 36 | MLXSW_RES_ID_ACL_MAX_REGIONS, |
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.. | .. |
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41 | 46 | MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB, |
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42 | 47 | MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB, |
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43 | 48 | MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB, |
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| 49 | + MLXSW_RES_ID_ACL_MAX_BF_LOG, |
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| 50 | + MLXSW_RES_ID_MAX_GLOBAL_POLICERS, |
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44 | 51 | MLXSW_RES_ID_MAX_CPU_POLICERS, |
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45 | 52 | MLXSW_RES_ID_MAX_VRS, |
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46 | 53 | MLXSW_RES_ID_MAX_RIFS, |
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47 | 54 | MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES, |
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48 | 55 | MLXSW_RES_ID_MAX_LPM_TREES, |
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| 56 | + MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4, |
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| 57 | + MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6, |
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49 | 58 | |
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50 | 59 | /* Internal resources. |
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51 | 60 | * Determined by the SW, not queried from the HW. |
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.. | .. |
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68 | 77 | [MLXSW_RES_ID_CQE_V1] = 0x2211, |
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69 | 78 | [MLXSW_RES_ID_CQE_V2] = 0x2212, |
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70 | 79 | [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410, |
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| 80 | + [MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411, |
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71 | 81 | [MLXSW_RES_ID_MAX_SPAN] = 0x2420, |
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72 | 82 | [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443, |
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73 | 83 | [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449, |
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74 | 84 | [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502, |
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75 | 85 | [MLXSW_RES_ID_MAX_LAG] = 0x2520, |
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76 | 86 | [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521, |
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77 | | - [MLXSW_RES_ID_MAX_BUFFER_SIZE] = 0x2802, /* Bytes */ |
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| 87 | + [MLXSW_RES_ID_LOCAL_PORTS_IN_1X] = 0x2610, |
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| 88 | + [MLXSW_RES_ID_LOCAL_PORTS_IN_2X] = 0x2611, |
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| 89 | + [MLXSW_RES_ID_LOCAL_PORTS_IN_4X] = 0x2612, |
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| 90 | + [MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805, /* Bytes */ |
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78 | 91 | [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */ |
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| 92 | + [MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811, /* Bytes */ |
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79 | 93 | [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901, |
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80 | 94 | [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902, |
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81 | 95 | [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903, |
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.. | .. |
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91 | 105 | [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951, |
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92 | 106 | [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952, |
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93 | 107 | [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953, |
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| 108 | + [MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960, |
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| 109 | + [MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10, |
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94 | 110 | [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13, |
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95 | 111 | [MLXSW_RES_ID_MAX_VRS] = 0x2C01, |
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96 | 112 | [MLXSW_RES_ID_MAX_RIFS] = 0x2C02, |
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97 | 113 | [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10, |
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98 | 114 | [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30, |
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| 115 | + [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02, |
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| 116 | + [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03, |
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99 | 117 | }; |
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100 | 118 | |
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101 | 119 | struct mlxsw_res { |
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