hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/net/ethernet/intel/i40e/i40e_diag.c
....@@ -44,7 +44,7 @@
4444 return 0;
4545 }
4646
47
-struct i40e_diag_reg_test_info i40e_reg_list[] = {
47
+const struct i40e_diag_reg_test_info i40e_reg_list[] = {
4848 /* offset mask elements stride */
4949 {I40E_QTX_CTL(0), 0x0000FFBF, 1,
5050 I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
....@@ -78,27 +78,28 @@
7878 {
7979 i40e_status ret_code = 0;
8080 u32 reg, mask;
81
+ u32 elements;
8182 u32 i, j;
8283
8384 for (i = 0; i40e_reg_list[i].offset != 0 &&
8485 !ret_code; i++) {
8586
87
+ elements = i40e_reg_list[i].elements;
8688 /* set actual reg range for dynamically allocated resources */
8789 if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
8890 hw->func_caps.num_tx_qp != 0)
89
- i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
91
+ elements = hw->func_caps.num_tx_qp;
9092 if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
9193 i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
9294 i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
9395 i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
9496 i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
9597 hw->func_caps.num_msix_vectors != 0)
96
- i40e_reg_list[i].elements =
97
- hw->func_caps.num_msix_vectors - 1;
98
+ elements = hw->func_caps.num_msix_vectors - 1;
9899
99100 /* test register access */
100101 mask = i40e_reg_list[i].mask;
101
- for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) {
102
+ for (j = 0; j < elements && !ret_code; j++) {
102103 reg = i40e_reg_list[i].offset +
103104 (j * i40e_reg_list[i].stride);
104105 ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);