.. | .. |
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117 | 117 | u32 rsvd1; |
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118 | 118 | }; |
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119 | 119 | |
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| 120 | +#define HCLGE_PFC_DISABLE 0 |
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| 121 | +#define HCLGE_PFC_TX_RX_DISABLE 0 |
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| 122 | + |
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120 | 123 | struct hclge_pfc_en_cmd { |
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121 | 124 | u8 tx_rx_en_bitmap; |
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122 | 125 | u8 pri_en_bitmap; |
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.. | .. |
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164 | 167 | void hclge_tm_pfc_info_update(struct hclge_dev *hdev); |
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165 | 168 | int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); |
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166 | 169 | int hclge_tm_init_hw(struct hclge_dev *hdev, bool init); |
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| 170 | +int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, |
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| 171 | + u8 pfc_bitmap); |
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167 | 172 | int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); |
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168 | 173 | int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); |
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169 | 174 | int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats); |
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