.. | .. |
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71 | 71 | static void hclge_sync_mac_table(struct hclge_dev *hdev); |
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72 | 72 | static void hclge_restore_hw_table(struct hclge_dev *hdev); |
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73 | 73 | static void hclge_sync_promisc_mode(struct hclge_dev *hdev); |
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| 74 | +static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, |
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| 75 | + int wait_cnt); |
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74 | 76 | |
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75 | 77 | static struct hnae3_ae_algo ae_algo; |
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76 | 78 | |
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.. | .. |
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3123 | 3125 | static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, |
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3124 | 3126 | u32 regclr) |
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3125 | 3127 | { |
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| 3128 | +#define HCLGE_IMP_RESET_DELAY 5 |
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| 3129 | + |
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3126 | 3130 | switch (event_type) { |
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3127 | 3131 | case HCLGE_VECTOR0_EVENT_RST: |
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| 3132 | + if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) |
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| 3133 | + mdelay(HCLGE_IMP_RESET_DELAY); |
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| 3134 | + |
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3128 | 3135 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); |
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3129 | 3136 | break; |
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3130 | 3137 | case HCLGE_VECTOR0_EVENT_MBX: |
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.. | .. |
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6558 | 6565 | |
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6559 | 6566 | static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) |
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6560 | 6567 | { |
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| 6568 | +#define HCLGE_LINK_STATUS_WAIT_CNT 3 |
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| 6569 | + |
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6561 | 6570 | struct hclge_desc desc; |
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6562 | 6571 | struct hclge_config_mac_mode_cmd *req = |
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6563 | 6572 | (struct hclge_config_mac_mode_cmd *)desc.data; |
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.. | .. |
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6582 | 6591 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); |
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6583 | 6592 | |
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6584 | 6593 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
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6585 | | - if (ret) |
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| 6594 | + if (ret) { |
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6586 | 6595 | dev_err(&hdev->pdev->dev, |
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6587 | 6596 | "mac enable fail, ret =%d.\n", ret); |
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| 6597 | + return; |
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| 6598 | + } |
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| 6599 | + |
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| 6600 | + if (!enable) |
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| 6601 | + hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, |
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| 6602 | + HCLGE_LINK_STATUS_WAIT_CNT); |
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6588 | 6603 | } |
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6589 | 6604 | |
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6590 | 6605 | static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, |
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.. | .. |
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6647 | 6662 | } while (++i < HCLGE_PHY_LINK_STATUS_NUM); |
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6648 | 6663 | } |
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6649 | 6664 | |
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6650 | | -static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret) |
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| 6665 | +static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, |
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| 6666 | + int wait_cnt) |
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6651 | 6667 | { |
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6652 | | -#define HCLGE_MAC_LINK_STATUS_NUM 100 |
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6653 | | - |
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6654 | 6668 | int link_status; |
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6655 | 6669 | int i = 0; |
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6656 | 6670 | int ret; |
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.. | .. |
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6663 | 6677 | return 0; |
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6664 | 6678 | |
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6665 | 6679 | msleep(HCLGE_LINK_STATUS_MS); |
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6666 | | - } while (++i < HCLGE_MAC_LINK_STATUS_NUM); |
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| 6680 | + } while (++i < wait_cnt); |
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6667 | 6681 | return -EBUSY; |
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6668 | 6682 | } |
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6669 | 6683 | |
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6670 | 6684 | static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, |
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6671 | 6685 | bool is_phy) |
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6672 | 6686 | { |
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| 6687 | +#define HCLGE_MAC_LINK_STATUS_NUM 100 |
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| 6688 | + |
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6673 | 6689 | int link_ret; |
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6674 | 6690 | |
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6675 | 6691 | link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; |
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.. | .. |
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6677 | 6693 | if (is_phy) |
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6678 | 6694 | hclge_phy_link_status_wait(hdev, link_ret); |
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6679 | 6695 | |
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6680 | | - return hclge_mac_link_status_wait(hdev, link_ret); |
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| 6696 | + return hclge_mac_link_status_wait(hdev, link_ret, |
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| 6697 | + HCLGE_MAC_LINK_STATUS_NUM); |
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6681 | 6698 | } |
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6682 | 6699 | |
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6683 | 6700 | static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) |
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.. | .. |
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7023 | 7040 | /* If it is not PF reset or FLR, the firmware will disable the MAC, |
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7024 | 7041 | * so it only need to stop phy here. |
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7025 | 7042 | */ |
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7026 | | - if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && |
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7027 | | - hdev->reset_type != HNAE3_FUNC_RESET && |
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7028 | | - hdev->reset_type != HNAE3_FLR_RESET) { |
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7029 | | - hclge_mac_stop_phy(hdev); |
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7030 | | - hclge_update_link_status(hdev); |
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7031 | | - return; |
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| 7043 | + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { |
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| 7044 | + hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, |
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| 7045 | + HCLGE_PFC_DISABLE); |
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| 7046 | + if (hdev->reset_type != HNAE3_FUNC_RESET && |
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| 7047 | + hdev->reset_type != HNAE3_FLR_RESET) { |
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| 7048 | + hclge_mac_stop_phy(hdev); |
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| 7049 | + hclge_update_link_status(hdev); |
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| 7050 | + return; |
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| 7051 | + } |
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7032 | 7052 | } |
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7033 | 7053 | |
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7034 | 7054 | for (i = 0; i < handle->kinfo.num_tqps; i++) |
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.. | .. |
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7835 | 7855 | if (mac_type == HCLGE_MAC_ADDR_UC) { |
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7836 | 7856 | if (is_all_added) |
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7837 | 7857 | vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; |
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7838 | | - else |
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| 7858 | + else if (hclge_is_umv_space_full(vport, true)) |
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7839 | 7859 | vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; |
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7840 | 7860 | } else { |
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7841 | 7861 | if (is_all_added) |
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