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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/mtd/nand/raw/marvell_nand.c
....@@ -2443,6 +2443,12 @@
24432443 			NDTR1_WAIT_MODE;
24442444 	}
24452445 
2446
+	/*
2447
+	 * Reset nfc->selected_chip so the next command will cause the timing
2448
+	 * registers to be updated in marvell_nfc_select_target().
2449
+	 */
2450
+	nfc->selected_chip = NULL;
2451
+
24462452 	return 0;
24472453 }
24482454 
....@@ -2885,10 +2891,6 @@
28852891 		regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL,
28862892 				   GENCONF_CLK_GATING_CTRL_ND_GATE,
28872893 				   GENCONF_CLK_GATING_CTRL_ND_GATE);
2888
-
2889
-		regmap_update_bits(sysctrl_base, GENCONF_ND_CLK_CTRL,
2890
-				   GENCONF_ND_CLK_CTRL_EN,
2891
-				   GENCONF_ND_CLK_CTRL_EN);
28922894 	}
28932895 
28942896 	/* Configure the DMA if appropriate */