.. | .. |
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224 | 224 | div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); |
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225 | 225 | sdhci_enable_clk(host, div); |
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226 | 226 | |
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227 | | - /* enable auto gate sdhc_enable_auto_gate */ |
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228 | | - val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); |
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229 | | - mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | |
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230 | | - SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; |
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231 | | - if (mask != (val & mask)) { |
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232 | | - val |= mask; |
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233 | | - sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); |
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| 227 | + /* Enable CLK_AUTO when the clock is greater than 400K. */ |
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| 228 | + if (clk > 400000) { |
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| 229 | + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); |
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| 230 | + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | |
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| 231 | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; |
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| 232 | + if (mask != (val & mask)) { |
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| 233 | + val |= mask; |
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| 234 | + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); |
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| 235 | + } |
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234 | 236 | } |
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235 | 237 | } |
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236 | 238 | |
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