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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/mmc/host/sdhci-of-esdhc.c
....@@ -1,16 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Freescale eSDHC controller driver.
34  *
45  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
56  * Copyright (c) 2009 MontaVista Software, Inc.
7
+ * Copyright 2020 NXP
68  *
79  * Authors: Xiaobo Xie <X.Xie@freescale.com>
810  *	    Anton Vorontsov <avorontsov@ru.mvista.com>
9
- *
10
- * This program is free software; you can redistribute it and/or modify
11
- * it under the terms of the GNU General Public License as published by
12
- * the Free Software Foundation; either version 2 of the License, or (at
13
- * your option) any later version.
1411  */
1512 
1613 #include <linux/err.h>
....@@ -23,7 +20,9 @@
2320 #include <linux/clk.h>
2421 #include <linux/ktime.h>
2522 #include <linux/dma-mapping.h>
23
+#include <linux/iopoll.h>
2624 #include <linux/mmc/host.h>
25
+#include <linux/mmc/mmc.h>
2726 #include "sdhci-pltfm.h"
2827 #include "sdhci-esdhc.h"
2928 
....@@ -78,8 +77,17 @@
7877 	u8 vendor_ver;
7978 	u8 spec_ver;
8079 	bool quirk_incorrect_hostver;
80
+	bool quirk_limited_clk_division;
81
+	bool quirk_unreliable_pulse_detection;
82
+	bool quirk_tuning_erratum_type1;
83
+	bool quirk_tuning_erratum_type2;
84
+	bool quirk_ignore_data_inhibit;
85
+	bool quirk_delay_before_data_reset;
86
+	bool quirk_trans_complete_erratum;
87
+	bool in_sw_tuning;
8188 	unsigned int peripheral_clock;
8289 	const struct esdhc_clk_fixup *clk_fixup;
90
+	u32 div_ratio;
8391 };
8492 
8593 /**
....@@ -118,6 +126,7 @@
118126 			return ret;
119127 		}
120128 	}
129
+
121130 	/*
122131 	 * The DAT[3:0] line signal levels and the CMD line signal level are
123132 	 * not compatible with standard SDHC register. The line signal levels
....@@ -129,6 +138,16 @@
129138 		ret = value & 0x000fffff;
130139 		ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
131140 		ret |= (value << 1) & SDHCI_CMD_LVL;
141
+
142
+		/*
143
+		 * Some controllers have unreliable Data Line Active
144
+		 * bit for commands with busy signal. This affects
145
+		 * Command Inhibit (data) bit. Just ignore it since
146
+		 * MMC core driver has already polled card status
147
+		 * with CMD13 after any command with busy siganl.
148
+		 */
149
+		if (esdhc->quirk_ignore_data_inhibit)
150
+			ret &= ~SDHCI_DATA_INHIBIT;
132151 		return ret;
133152 	}
134153 
....@@ -154,6 +173,9 @@
154173 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
155174 	u16 ret;
156175 	int shift = (spec_reg & 0x2) * 8;
176
+
177
+	if (spec_reg == SDHCI_TRANSFER_MODE)
178
+		return pltfm_host->xfer_mode_shadow;
157179 
158180 	if (spec_reg == SDHCI_HOST_VERSION)
159181 		ret = value & 0xffff;
....@@ -393,6 +415,8 @@
393415 
394416 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
395417 {
418
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
419
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
396420 	int base = reg & ~0x3;
397421 	u32 value;
398422 	u32 ret;
....@@ -401,10 +425,24 @@
401425 	ret = esdhc_writew_fixup(host, reg, val, value);
402426 	if (reg != SDHCI_TRANSFER_MODE)
403427 		iowrite32be(ret, host->ioaddr + base);
428
+
429
+	/* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
430
+	 * 1us later after ESDHC_EXTN is set.
431
+	 */
432
+	if (base == ESDHC_SYSTEM_CONTROL_2) {
433
+		if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
434
+		    esdhc->in_sw_tuning) {
435
+			udelay(1);
436
+			ret |= ESDHC_SMPCLKSEL;
437
+			iowrite32be(ret, host->ioaddr + base);
438
+		}
439
+	}
404440 }
405441 
406442 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
407443 {
444
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
445
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
408446 	int base = reg & ~0x3;
409447 	u32 value;
410448 	u32 ret;
....@@ -413,6 +451,18 @@
413451 	ret = esdhc_writew_fixup(host, reg, val, value);
414452 	if (reg != SDHCI_TRANSFER_MODE)
415453 		iowrite32(ret, host->ioaddr + base);
454
+
455
+	/* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
456
+	 * 1us later after ESDHC_EXTN is set.
457
+	 */
458
+	if (base == ESDHC_SYSTEM_CONTROL_2) {
459
+		if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
460
+		    esdhc->in_sw_tuning) {
461
+			udelay(1);
462
+			ret |= ESDHC_SMPCLKSEL;
463
+			iowrite32(ret, host->ioaddr + base);
464
+		}
465
+	}
416466 }
417467 
418468 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
....@@ -520,91 +570,36 @@
520570 
521571 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
522572 {
523
-	u32 val;
573
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
574
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
524575 	ktime_t timeout;
576
+	u32 val, clk_en;
577
+
578
+	clk_en = ESDHC_CLOCK_SDCLKEN;
579
+
580
+	/*
581
+	 * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version
582
+	 * is 2.2 or lower.
583
+	 */
584
+	if (esdhc->vendor_ver <= VENDOR_V_22)
585
+		clk_en |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
586
+			   ESDHC_CLOCK_PEREN);
525587 
526588 	val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
527589 
528590 	if (enable)
529
-		val |= ESDHC_CLOCK_SDCLKEN;
591
+		val |= clk_en;
530592 	else
531
-		val &= ~ESDHC_CLOCK_SDCLKEN;
593
+		val &= ~clk_en;
532594 
533595 	sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
534596 
535
-	/* Wait max 20 ms */
597
+	/*
598
+	 * Wait max 20 ms. If vendor version is 2.2 or lower, do not
599
+	 * wait clock stable bit which does not exist.
600
+	 */
536601 	timeout = ktime_add_ms(ktime_get(), 20);
537
-	val = ESDHC_CLOCK_STABLE;
538
-	while  (1) {
539
-		bool timedout = ktime_after(ktime_get(), timeout);
540
-
541
-		if (sdhci_readl(host, ESDHC_PRSSTAT) & val)
542
-			break;
543
-		if (timedout) {
544
-			pr_err("%s: Internal clock never stabilised.\n",
545
-				mmc_hostname(host->mmc));
546
-			break;
547
-		}
548
-		udelay(10);
549
-	}
550
-}
551
-
552
-static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
553
-{
554
-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
555
-	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
556
-	int pre_div = 1;
557
-	int div = 1;
558
-	ktime_t timeout;
559
-	long fixup = 0;
560
-	u32 temp;
561
-
562
-	host->mmc->actual_clock = 0;
563
-
564
-	if (clock == 0) {
565
-		esdhc_clock_enable(host, false);
566
-		return;
567
-	}
568
-
569
-	/* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
570
-	if (esdhc->vendor_ver < VENDOR_V_23)
571
-		pre_div = 2;
572
-
573
-	if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
574
-		esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
575
-		fixup = esdhc->clk_fixup->sd_dflt_max_clk;
576
-	else if (esdhc->clk_fixup)
577
-		fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
578
-
579
-	if (fixup && clock > fixup)
580
-		clock = fixup;
581
-
582
-	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
583
-	temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
584
-		  ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
585
-	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
586
-
587
-	while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
588
-		pre_div *= 2;
589
-
590
-	while (host->max_clk / pre_div / div > clock && div < 16)
591
-		div++;
592
-
593
-	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
594
-		clock, host->max_clk / pre_div / div);
595
-	host->mmc->actual_clock = host->max_clk / pre_div / div;
596
-	pre_div >>= 1;
597
-	div--;
598
-
599
-	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
600
-	temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
601
-		| (div << ESDHC_DIVIDER_SHIFT)
602
-		| (pre_div << ESDHC_PREDIV_SHIFT));
603
-	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
604
-
605
-	/* Wait max 20 ms */
606
-	timeout = ktime_add_ms(ktime_get(), 20);
607
-	while (1) {
602
+	while (esdhc->vendor_ver > VENDOR_V_22) {
608603 		bool timedout = ktime_after(ktime_get(), timeout);
609604 
610605 		if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
....@@ -612,13 +607,168 @@
612607 		if (timedout) {
613608 			pr_err("%s: Internal clock never stabilised.\n",
614609 				mmc_hostname(host->mmc));
615
-			return;
610
+			break;
616611 		}
617
-		udelay(10);
612
+		usleep_range(10, 20);
613
+	}
614
+}
615
+
616
+static void esdhc_flush_async_fifo(struct sdhci_host *host)
617
+{
618
+	ktime_t timeout;
619
+	u32 val;
620
+
621
+	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
622
+	val |= ESDHC_FLUSH_ASYNC_FIFO;
623
+	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
624
+
625
+	/* Wait max 20 ms */
626
+	timeout = ktime_add_ms(ktime_get(), 20);
627
+	while (1) {
628
+		bool timedout = ktime_after(ktime_get(), timeout);
629
+
630
+		if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
631
+		      ESDHC_FLUSH_ASYNC_FIFO))
632
+			break;
633
+		if (timedout) {
634
+			pr_err("%s: flushing asynchronous FIFO timeout.\n",
635
+				mmc_hostname(host->mmc));
636
+			break;
637
+		}
638
+		usleep_range(10, 20);
639
+	}
640
+}
641
+
642
+static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
643
+{
644
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
645
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
646
+	unsigned int pre_div = 1, div = 1;
647
+	unsigned int clock_fixup = 0;
648
+	ktime_t timeout;
649
+	u32 temp;
650
+
651
+	if (clock == 0) {
652
+		host->mmc->actual_clock = 0;
653
+		esdhc_clock_enable(host, false);
654
+		return;
618655 	}
619656 
620
-	temp |= ESDHC_CLOCK_SDCLKEN;
657
+	/* Start pre_div at 2 for vendor version < 2.3. */
658
+	if (esdhc->vendor_ver < VENDOR_V_23)
659
+		pre_div = 2;
660
+
661
+	/* Fix clock value. */
662
+	if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
663
+	    esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
664
+		clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk;
665
+	else if (esdhc->clk_fixup)
666
+		clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
667
+
668
+	if (clock_fixup == 0 || clock < clock_fixup)
669
+		clock_fixup = clock;
670
+
671
+	/* Calculate pre_div and div. */
672
+	while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
673
+		pre_div *= 2;
674
+
675
+	while (host->max_clk / pre_div / div > clock_fixup && div < 16)
676
+		div++;
677
+
678
+	esdhc->div_ratio = pre_div * div;
679
+
680
+	/* Limit clock division for HS400 200MHz clock for quirk. */
681
+	if (esdhc->quirk_limited_clk_division &&
682
+	    clock == MMC_HS200_MAX_DTR &&
683
+	    (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
684
+	     host->flags & SDHCI_HS400_TUNING)) {
685
+		if (esdhc->div_ratio <= 4) {
686
+			pre_div = 4;
687
+			div = 1;
688
+		} else if (esdhc->div_ratio <= 8) {
689
+			pre_div = 4;
690
+			div = 2;
691
+		} else if (esdhc->div_ratio <= 12) {
692
+			pre_div = 4;
693
+			div = 3;
694
+		} else {
695
+			pr_warn("%s: using unsupported clock division.\n",
696
+				mmc_hostname(host->mmc));
697
+		}
698
+		esdhc->div_ratio = pre_div * div;
699
+	}
700
+
701
+	host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
702
+
703
+	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
704
+		clock, host->mmc->actual_clock);
705
+
706
+	/* Set clock division into register. */
707
+	pre_div >>= 1;
708
+	div--;
709
+
710
+	esdhc_clock_enable(host, false);
711
+
712
+	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
713
+	temp &= ~ESDHC_CLOCK_MASK;
714
+	temp |= ((div << ESDHC_DIVIDER_SHIFT) |
715
+		(pre_div << ESDHC_PREDIV_SHIFT));
621716 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
717
+
718
+	/*
719
+	 * Wait max 20 ms. If vendor version is 2.2 or lower, do not
720
+	 * wait clock stable bit which does not exist.
721
+	 */
722
+	timeout = ktime_add_ms(ktime_get(), 20);
723
+	while (esdhc->vendor_ver > VENDOR_V_22) {
724
+		bool timedout = ktime_after(ktime_get(), timeout);
725
+
726
+		if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
727
+			break;
728
+		if (timedout) {
729
+			pr_err("%s: Internal clock never stabilised.\n",
730
+				mmc_hostname(host->mmc));
731
+			break;
732
+		}
733
+		usleep_range(10, 20);
734
+	}
735
+
736
+	/* Additional setting for HS400. */
737
+	if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
738
+	    clock == MMC_HS200_MAX_DTR) {
739
+		temp = sdhci_readl(host, ESDHC_TBCTL);
740
+		sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
741
+		temp = sdhci_readl(host, ESDHC_SDCLKCTL);
742
+		sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
743
+		esdhc_clock_enable(host, true);
744
+
745
+		temp = sdhci_readl(host, ESDHC_DLLCFG0);
746
+		temp |= ESDHC_DLL_ENABLE;
747
+		if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
748
+			temp |= ESDHC_DLL_FREQ_SEL;
749
+		sdhci_writel(host, temp, ESDHC_DLLCFG0);
750
+
751
+		temp |= ESDHC_DLL_RESET;
752
+		sdhci_writel(host, temp, ESDHC_DLLCFG0);
753
+		udelay(1);
754
+		temp &= ~ESDHC_DLL_RESET;
755
+		sdhci_writel(host, temp, ESDHC_DLLCFG0);
756
+
757
+		/* Wait max 20 ms */
758
+		if (read_poll_timeout(sdhci_readl, temp,
759
+				      temp & ESDHC_DLL_STS_SLV_LOCK,
760
+				      10, 20000, false,
761
+				      host, ESDHC_DLLSTAT0))
762
+			pr_err("%s: timeout for delay chain lock.\n",
763
+			       mmc_hostname(host->mmc));
764
+
765
+		temp = sdhci_readl(host, ESDHC_TBCTL);
766
+		sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
767
+
768
+		esdhc_clock_enable(host, false);
769
+		esdhc_flush_async_fifo(host);
770
+	}
771
+	esdhc_clock_enable(host, true);
622772 }
623773 
624774 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
....@@ -645,17 +795,65 @@
645795 
646796 static void esdhc_reset(struct sdhci_host *host, u8 mask)
647797 {
648
-	u32 val;
798
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
799
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
800
+	u32 val, bus_width = 0;
801
+
802
+	/*
803
+	 * Add delay to make sure all the DMA transfers are finished
804
+	 * for quirk.
805
+	 */
806
+	if (esdhc->quirk_delay_before_data_reset &&
807
+	    (mask & SDHCI_RESET_DATA) &&
808
+	    (host->flags & SDHCI_REQ_USE_DMA))
809
+		mdelay(5);
810
+
811
+	/*
812
+	 * Save bus-width for eSDHC whose vendor version is 2.2
813
+	 * or lower for data reset.
814
+	 */
815
+	if ((mask & SDHCI_RESET_DATA) &&
816
+	    (esdhc->vendor_ver <= VENDOR_V_22)) {
817
+		val = sdhci_readl(host, ESDHC_PROCTL);
818
+		bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
819
+	}
649820 
650821 	sdhci_reset(host, mask);
651822 
652
-	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
653
-	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
823
+	/*
824
+	 * Restore bus-width setting and interrupt registers for eSDHC
825
+	 * whose vendor version is 2.2 or lower for data reset.
826
+	 */
827
+	if ((mask & SDHCI_RESET_DATA) &&
828
+	    (esdhc->vendor_ver <= VENDOR_V_22)) {
829
+		val = sdhci_readl(host, ESDHC_PROCTL);
830
+		val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
831
+		val |= bus_width;
832
+		sdhci_writel(host, val, ESDHC_PROCTL);
654833 
655
-	if (mask & SDHCI_RESET_ALL) {
834
+		sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
835
+		sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
836
+	}
837
+
838
+	/*
839
+	 * Some bits have to be cleaned manually for eSDHC whose spec
840
+	 * version is higher than 3.0 for all reset.
841
+	 */
842
+	if ((mask & SDHCI_RESET_ALL) &&
843
+	    (esdhc->spec_ver >= SDHCI_SPEC_300)) {
656844 		val = sdhci_readl(host, ESDHC_TBCTL);
657845 		val &= ~ESDHC_TB_EN;
658846 		sdhci_writel(host, val, ESDHC_TBCTL);
847
+
848
+		/*
849
+		 * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to
850
+		 * 0 for quirk.
851
+		 */
852
+		if (esdhc->quirk_unreliable_pulse_detection) {
853
+			val = sdhci_readl(host, ESDHC_DLLCFG1);
854
+			val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
855
+			sdhci_writel(host, val, ESDHC_DLLCFG1);
856
+		}
659857 	}
660858 }
661859 
....@@ -704,6 +902,7 @@
704902 		scfg_node = of_find_matching_node(NULL, scfg_device_ids);
705903 		if (scfg_node)
706904 			scfg_base = of_iomap(scfg_node, 0);
905
+		of_node_put(scfg_node);
707906 		if (scfg_base) {
708907 			sdhciovselcr = SDHCIOVSELCR_TGLEN |
709908 				       SDHCIOVSELCR_VSELVAL;
....@@ -729,23 +928,303 @@
729928 	}
730929 }
731930 
931
+static struct soc_device_attribute soc_tuning_erratum_type1[] = {
932
+	{ .family = "QorIQ T1023", },
933
+	{ .family = "QorIQ T1040", },
934
+	{ .family = "QorIQ T2080", },
935
+	{ .family = "QorIQ LS1021A", },
936
+	{ },
937
+};
938
+
939
+static struct soc_device_attribute soc_tuning_erratum_type2[] = {
940
+	{ .family = "QorIQ LS1012A", },
941
+	{ .family = "QorIQ LS1043A", },
942
+	{ .family = "QorIQ LS1046A", },
943
+	{ .family = "QorIQ LS1080A", },
944
+	{ .family = "QorIQ LS2080A", },
945
+	{ .family = "QorIQ LA1575A", },
946
+	{ },
947
+};
948
+
949
+static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
950
+{
951
+	u32 val;
952
+
953
+	esdhc_clock_enable(host, false);
954
+	esdhc_flush_async_fifo(host);
955
+
956
+	val = sdhci_readl(host, ESDHC_TBCTL);
957
+	if (enable)
958
+		val |= ESDHC_TB_EN;
959
+	else
960
+		val &= ~ESDHC_TB_EN;
961
+	sdhci_writel(host, val, ESDHC_TBCTL);
962
+
963
+	esdhc_clock_enable(host, true);
964
+}
965
+
966
+static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start,
967
+				    u8 *window_end)
968
+{
969
+	u32 val;
970
+
971
+	/* Write TBCTL[11:8]=4'h8 */
972
+	val = sdhci_readl(host, ESDHC_TBCTL);
973
+	val &= ~(0xf << 8);
974
+	val |= 8 << 8;
975
+	sdhci_writel(host, val, ESDHC_TBCTL);
976
+
977
+	mdelay(1);
978
+
979
+	/* Read TBCTL[31:0] register and rewrite again */
980
+	val = sdhci_readl(host, ESDHC_TBCTL);
981
+	sdhci_writel(host, val, ESDHC_TBCTL);
982
+
983
+	mdelay(1);
984
+
985
+	/* Read the TBSTAT[31:0] register twice */
986
+	val = sdhci_readl(host, ESDHC_TBSTAT);
987
+	val = sdhci_readl(host, ESDHC_TBSTAT);
988
+
989
+	*window_end = val & 0xff;
990
+	*window_start = (val >> 8) & 0xff;
991
+}
992
+
993
+static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start,
994
+				    u8 *window_end)
995
+{
996
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
997
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
998
+	u8 start_ptr, end_ptr;
999
+
1000
+	if (esdhc->quirk_tuning_erratum_type1) {
1001
+		*window_start = 5 * esdhc->div_ratio;
1002
+		*window_end = 3 * esdhc->div_ratio;
1003
+		return;
1004
+	}
1005
+
1006
+	esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr);
1007
+
1008
+	/* Reset data lines by setting ESDHCCTL[RSTD] */
1009
+	sdhci_reset(host, SDHCI_RESET_DATA);
1010
+	/* Write 32'hFFFF_FFFF to IRQSTAT register */
1011
+	sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
1012
+
1013
+	/* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2
1014
+	 * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2,
1015
+	 * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio
1016
+	 * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio.
1017
+	 */
1018
+
1019
+	if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) {
1020
+		*window_start = 8 * esdhc->div_ratio;
1021
+		*window_end = 4 * esdhc->div_ratio;
1022
+	} else {
1023
+		*window_start = 5 * esdhc->div_ratio;
1024
+		*window_end = 3 * esdhc->div_ratio;
1025
+	}
1026
+}
1027
+
1028
+static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode,
1029
+				   u8 window_start, u8 window_end)
1030
+{
1031
+	struct sdhci_host *host = mmc_priv(mmc);
1032
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1033
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1034
+	u32 val;
1035
+	int ret;
1036
+
1037
+	/* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */
1038
+	val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
1039
+	      ESDHC_WNDW_STRT_PTR_MASK;
1040
+	val |= window_end & ESDHC_WNDW_END_PTR_MASK;
1041
+	sdhci_writel(host, val, ESDHC_TBPTR);
1042
+
1043
+	/* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */
1044
+	val = sdhci_readl(host, ESDHC_TBCTL);
1045
+	val &= ~ESDHC_TB_MODE_MASK;
1046
+	val |= ESDHC_TB_MODE_SW;
1047
+	sdhci_writel(host, val, ESDHC_TBCTL);
1048
+
1049
+	esdhc->in_sw_tuning = true;
1050
+	ret = sdhci_execute_tuning(mmc, opcode);
1051
+	esdhc->in_sw_tuning = false;
1052
+	return ret;
1053
+}
1054
+
7321055 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
7331056 {
7341057 	struct sdhci_host *host = mmc_priv(mmc);
1058
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1059
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1060
+	u8 window_start, window_end;
1061
+	int ret, retries = 1;
1062
+	bool hs400_tuning;
1063
+	unsigned int clk;
7351064 	u32 val;
7361065 
737
-	/* Use tuning block for tuning procedure */
738
-	esdhc_clock_enable(host, false);
739
-	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
740
-	val |= ESDHC_FLUSH_ASYNC_FIFO;
741
-	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1066
+	/* For tuning mode, the sd clock divisor value
1067
+	 * must be larger than 3 according to reference manual.
1068
+	 */
1069
+	clk = esdhc->peripheral_clock / 3;
1070
+	if (host->clock > clk)
1071
+		esdhc_of_set_clock(host, clk);
7421072 
1073
+	esdhc_tuning_block_enable(host, true);
1074
+
1075
+	/*
1076
+	 * The eSDHC controller takes the data timeout value into account
1077
+	 * during tuning. If the SD card is too slow sending the response, the
1078
+	 * timer will expire and a "Buffer Read Ready" interrupt without data
1079
+	 * is triggered. This leads to tuning errors.
1080
+	 *
1081
+	 * Just set the timeout to the maximum value because the core will
1082
+	 * already take care of it in sdhci_send_tuning().
1083
+	 */
1084
+	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
1085
+
1086
+	hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1087
+
1088
+	do {
1089
+		if (esdhc->quirk_limited_clk_division &&
1090
+		    hs400_tuning)
1091
+			esdhc_of_set_clock(host, host->clock);
1092
+
1093
+		/* Do HW tuning */
1094
+		val = sdhci_readl(host, ESDHC_TBCTL);
1095
+		val &= ~ESDHC_TB_MODE_MASK;
1096
+		val |= ESDHC_TB_MODE_3;
1097
+		sdhci_writel(host, val, ESDHC_TBCTL);
1098
+
1099
+		ret = sdhci_execute_tuning(mmc, opcode);
1100
+		if (ret)
1101
+			break;
1102
+
1103
+		/* For type2 affected platforms of the tuning erratum,
1104
+		 * tuning may succeed although eSDHC might not have
1105
+		 * tuned properly. Need to check tuning window.
1106
+		 */
1107
+		if (esdhc->quirk_tuning_erratum_type2 &&
1108
+		    !host->tuning_err) {
1109
+			esdhc_tuning_window_ptr(host, &window_start,
1110
+						&window_end);
1111
+			if (abs(window_start - window_end) >
1112
+			    (4 * esdhc->div_ratio + 2))
1113
+				host->tuning_err = -EAGAIN;
1114
+		}
1115
+
1116
+		/* If HW tuning fails and triggers erratum,
1117
+		 * try workaround.
1118
+		 */
1119
+		ret = host->tuning_err;
1120
+		if (ret == -EAGAIN &&
1121
+		    (esdhc->quirk_tuning_erratum_type1 ||
1122
+		     esdhc->quirk_tuning_erratum_type2)) {
1123
+			/* Recover HS400 tuning flag */
1124
+			if (hs400_tuning)
1125
+				host->flags |= SDHCI_HS400_TUNING;
1126
+			pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
1127
+				mmc_hostname(mmc));
1128
+			/* Do SW tuning */
1129
+			esdhc_prepare_sw_tuning(host, &window_start,
1130
+						&window_end);
1131
+			ret = esdhc_execute_sw_tuning(mmc, opcode,
1132
+						      window_start,
1133
+						      window_end);
1134
+			if (ret)
1135
+				break;
1136
+
1137
+			/* Retry both HW/SW tuning with reduced clock. */
1138
+			ret = host->tuning_err;
1139
+			if (ret == -EAGAIN && retries) {
1140
+				/* Recover HS400 tuning flag */
1141
+				if (hs400_tuning)
1142
+					host->flags |= SDHCI_HS400_TUNING;
1143
+
1144
+				clk = host->max_clk / (esdhc->div_ratio + 1);
1145
+				esdhc_of_set_clock(host, clk);
1146
+				pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
1147
+					mmc_hostname(mmc));
1148
+			} else {
1149
+				break;
1150
+			}
1151
+		} else {
1152
+			break;
1153
+		}
1154
+	} while (retries--);
1155
+
1156
+	if (ret) {
1157
+		esdhc_tuning_block_enable(host, false);
1158
+	} else if (hs400_tuning) {
1159
+		val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1160
+		val |= ESDHC_FLW_CTL_BG;
1161
+		sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1162
+	}
1163
+
1164
+	return ret;
1165
+}
1166
+
1167
+static void esdhc_set_uhs_signaling(struct sdhci_host *host,
1168
+				   unsigned int timing)
1169
+{
1170
+	u32 val;
1171
+
1172
+	/*
1173
+	 * There are specific registers setting for HS400 mode.
1174
+	 * Clean all of them if controller is in HS400 mode to
1175
+	 * exit HS400 mode before re-setting any speed mode.
1176
+	 */
7431177 	val = sdhci_readl(host, ESDHC_TBCTL);
744
-	val |= ESDHC_TB_EN;
745
-	sdhci_writel(host, val, ESDHC_TBCTL);
746
-	esdhc_clock_enable(host, true);
1178
+	if (val & ESDHC_HS400_MODE) {
1179
+		val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1180
+		val &= ~ESDHC_FLW_CTL_BG;
1181
+		sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
7471182 
748
-	return sdhci_execute_tuning(mmc, opcode);
1183
+		val = sdhci_readl(host, ESDHC_SDCLKCTL);
1184
+		val &= ~ESDHC_CMD_CLK_CTL;
1185
+		sdhci_writel(host, val, ESDHC_SDCLKCTL);
1186
+
1187
+		esdhc_clock_enable(host, false);
1188
+		val = sdhci_readl(host, ESDHC_TBCTL);
1189
+		val &= ~ESDHC_HS400_MODE;
1190
+		sdhci_writel(host, val, ESDHC_TBCTL);
1191
+		esdhc_clock_enable(host, true);
1192
+
1193
+		val = sdhci_readl(host, ESDHC_DLLCFG0);
1194
+		val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL);
1195
+		sdhci_writel(host, val, ESDHC_DLLCFG0);
1196
+
1197
+		val = sdhci_readl(host, ESDHC_TBCTL);
1198
+		val &= ~ESDHC_HS400_WNDW_ADJUST;
1199
+		sdhci_writel(host, val, ESDHC_TBCTL);
1200
+
1201
+		esdhc_tuning_block_enable(host, false);
1202
+	}
1203
+
1204
+	if (timing == MMC_TIMING_MMC_HS400)
1205
+		esdhc_tuning_block_enable(host, true);
1206
+	else
1207
+		sdhci_set_uhs_signaling(host, timing);
1208
+}
1209
+
1210
+static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
1211
+{
1212
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1213
+	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
1214
+	u32 command;
1215
+
1216
+	if (esdhc->quirk_trans_complete_erratum) {
1217
+		command = SDHCI_GET_CMD(sdhci_readw(host,
1218
+					SDHCI_COMMAND));
1219
+		if (command == MMC_WRITE_MULTIPLE_BLOCK &&
1220
+				sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
1221
+				intmask & SDHCI_INT_DATA_END) {
1222
+			intmask &= ~SDHCI_INT_DATA_END;
1223
+			sdhci_writel(host, SDHCI_INT_DATA_END,
1224
+					SDHCI_INT_STATUS);
1225
+		}
1226
+	}
1227
+	return intmask;
7491228 }
7501229 
7511230 #ifdef CONFIG_PM_SLEEP
....@@ -794,7 +1273,8 @@
7941273 	.adma_workaround = esdhc_of_adma_workaround,
7951274 	.set_bus_width = esdhc_pltfm_set_bus_width,
7961275 	.reset = esdhc_reset,
797
-	.set_uhs_signaling = sdhci_set_uhs_signaling,
1276
+	.set_uhs_signaling = esdhc_set_uhs_signaling,
1277
+	.irq = esdhc_irq,
7981278 };
7991279 
8001280 static const struct sdhci_ops sdhci_esdhc_le_ops = {
....@@ -811,7 +1291,8 @@
8111291 	.adma_workaround = esdhc_of_adma_workaround,
8121292 	.set_bus_width = esdhc_pltfm_set_bus_width,
8131293 	.reset = esdhc_reset,
814
-	.set_uhs_signaling = sdhci_set_uhs_signaling,
1294
+	.set_uhs_signaling = esdhc_set_uhs_signaling,
1295
+	.irq = esdhc_irq,
8151296 };
8161297 
8171298 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
....@@ -837,6 +1318,20 @@
8371318 	{ },
8381319 };
8391320 
1321
+static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
1322
+	{ .family = "QorIQ LX2160A", .revision = "1.0", },
1323
+	{ .family = "QorIQ LX2160A", .revision = "2.0", },
1324
+	{ .family = "QorIQ LS1028A", .revision = "1.0", },
1325
+	{ },
1326
+};
1327
+
1328
+static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
1329
+	{ .family = "QorIQ LX2160A", .revision = "1.0", },
1330
+	{ .family = "QorIQ LX2160A", .revision = "2.0", },
1331
+	{ .family = "QorIQ LS1028A", .revision = "1.0", },
1332
+	{ },
1333
+};
1334
+
8401335 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
8411336 {
8421337 	const struct of_device_id *match;
....@@ -859,20 +1354,38 @@
8591354 	else
8601355 		esdhc->quirk_incorrect_hostver = false;
8611356 
1357
+	if (soc_device_match(soc_fixup_sdhc_clkdivs))
1358
+		esdhc->quirk_limited_clk_division = true;
1359
+	else
1360
+		esdhc->quirk_limited_clk_division = false;
1361
+
1362
+	if (soc_device_match(soc_unreliable_pulse_detection))
1363
+		esdhc->quirk_unreliable_pulse_detection = true;
1364
+	else
1365
+		esdhc->quirk_unreliable_pulse_detection = false;
1366
+
8621367 	match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
8631368 	if (match)
8641369 		esdhc->clk_fixup = match->data;
8651370 	np = pdev->dev.of_node;
1371
+
1372
+	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
1373
+		esdhc->quirk_delay_before_data_reset = true;
1374
+		esdhc->quirk_trans_complete_erratum = true;
1375
+	}
1376
+
8661377 	clk = of_clk_get(np, 0);
8671378 	if (!IS_ERR(clk)) {
8681379 		/*
8691380 		 * esdhc->peripheral_clock would be assigned with a value
8701381 		 * which is eSDHC base clock when use periperal clock.
871
-		 * For ls1046a, the clock value got by common clk API is
872
-		 * peripheral clock while the eSDHC base clock is 1/2
873
-		 * peripheral clock.
1382
+		 * For some platforms, the clock value got by common clk
1383
+		 * API is peripheral clock while the eSDHC base clock is
1384
+		 * 1/2 peripheral clock.
8741385 		 */
875
-		if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
1386
+		if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
1387
+		    of_device_is_compatible(np, "fsl,ls1028a-esdhc") ||
1388
+		    of_device_is_compatible(np, "fsl,ls1088a-esdhc"))
8761389 			esdhc->peripheral_clock = clk_get_rate(clk) / 2;
8771390 		else
8781391 			esdhc->peripheral_clock = clk_get_rate(clk);
....@@ -880,13 +1393,25 @@
8801393 		clk_put(clk);
8811394 	}
8821395 
883
-	if (esdhc->peripheral_clock) {
884
-		esdhc_clock_enable(host, false);
885
-		val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1396
+	esdhc_clock_enable(host, false);
1397
+	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1398
+	/*
1399
+	 * This bit is not able to be reset by SDHCI_RESET_ALL. Need to
1400
+	 * initialize it as 1 or 0 once, to override the different value
1401
+	 * which may be configured in bootloader.
1402
+	 */
1403
+	if (esdhc->peripheral_clock)
8861404 		val |= ESDHC_PERIPHERAL_CLK_SEL;
887
-		sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
888
-		esdhc_clock_enable(host, true);
889
-	}
1405
+	else
1406
+		val &= ~ESDHC_PERIPHERAL_CLK_SEL;
1407
+	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1408
+	esdhc_clock_enable(host, true);
1409
+}
1410
+
1411
+static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
1412
+{
1413
+	esdhc_tuning_block_enable(mmc_priv(mmc), false);
1414
+	return 0;
8901415 }
8911416 
8921417 static int sdhci_esdhc_probe(struct platform_device *pdev)
....@@ -912,6 +1437,7 @@
9121437 	host->mmc_host_ops.start_signal_voltage_switch =
9131438 		esdhc_signal_voltage_switch;
9141439 	host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
1440
+	host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
9151441 	host->tuning_delay = 1;
9161442 
9171443 	esdhc_init(pdev, host);
....@@ -920,6 +1446,16 @@
9201446 
9211447 	pltfm_host = sdhci_priv(host);
9221448 	esdhc = sdhci_pltfm_priv(pltfm_host);
1449
+	if (soc_device_match(soc_tuning_erratum_type1))
1450
+		esdhc->quirk_tuning_erratum_type1 = true;
1451
+	else
1452
+		esdhc->quirk_tuning_erratum_type1 = false;
1453
+
1454
+	if (soc_device_match(soc_tuning_erratum_type2))
1455
+		esdhc->quirk_tuning_erratum_type2 = true;
1456
+	else
1457
+		esdhc->quirk_tuning_erratum_type2 = false;
1458
+
9231459 	if (esdhc->vendor_ver == VENDOR_V_22)
9241460 		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
9251461 
....@@ -941,12 +1477,14 @@
9411477 	if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
9421478 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
9431479 
1480
+	esdhc->quirk_ignore_data_inhibit = false;
9441481 	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
9451482 		/*
9461483 		 * Freescale messed up with P2020 as it has a non-standard
9471484 		 * host control register
9481485 		 */
9491486 		host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
1487
+		esdhc->quirk_ignore_data_inhibit = true;
9501488 	}
9511489 
9521490 	/* call to generic mmc_of_parse to support additional capabilities */