hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/mmc/host/sdhci-of-esdhc.c
....@@ -126,6 +126,7 @@
126126 return ret;
127127 }
128128 }
129
+
129130 /*
130131 * The DAT[3:0] line signal levels and the CMD line signal level are
131132 * not compatible with standard SDHC register. The line signal levels
....@@ -137,6 +138,16 @@
137138 ret = value & 0x000fffff;
138139 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
139140 ret |= (value << 1) & SDHCI_CMD_LVL;
141
+
142
+ /*
143
+ * Some controllers have unreliable Data Line Active
144
+ * bit for commands with busy signal. This affects
145
+ * Command Inhibit (data) bit. Just ignore it since
146
+ * MMC core driver has already polled card status
147
+ * with CMD13 after any command with busy siganl.
148
+ */
149
+ if (esdhc->quirk_ignore_data_inhibit)
150
+ ret &= ~SDHCI_DATA_INHIBIT;
140151 return ret;
141152 }
142153
....@@ -148,19 +159,6 @@
148159 if (spec_reg == SDHCI_CAPABILITIES_1) {
149160 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
150161 SDHCI_SUPPORT_DDR50);
151
- return ret;
152
- }
153
-
154
- /*
155
- * Some controllers have unreliable Data Line Active
156
- * bit for commands with busy signal. This affects
157
- * Command Inhibit (data) bit. Just ignore it since
158
- * MMC core driver has already polled card status
159
- * with CMD13 after any command with busy siganl.
160
- */
161
- if ((spec_reg == SDHCI_PRESENT_STATE) &&
162
- (esdhc->quirk_ignore_data_inhibit == true)) {
163
- ret = value & ~SDHCI_DATA_INHIBIT;
164162 return ret;
165163 }
166164