.. | .. |
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126 | 126 | return ret; |
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127 | 127 | } |
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128 | 128 | } |
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| 129 | + |
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129 | 130 | /* |
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130 | 131 | * The DAT[3:0] line signal levels and the CMD line signal level are |
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131 | 132 | * not compatible with standard SDHC register. The line signal levels |
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.. | .. |
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137 | 138 | ret = value & 0x000fffff; |
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138 | 139 | ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; |
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139 | 140 | ret |= (value << 1) & SDHCI_CMD_LVL; |
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| 141 | + |
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| 142 | + /* |
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| 143 | + * Some controllers have unreliable Data Line Active |
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| 144 | + * bit for commands with busy signal. This affects |
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| 145 | + * Command Inhibit (data) bit. Just ignore it since |
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| 146 | + * MMC core driver has already polled card status |
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| 147 | + * with CMD13 after any command with busy siganl. |
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| 148 | + */ |
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| 149 | + if (esdhc->quirk_ignore_data_inhibit) |
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| 150 | + ret &= ~SDHCI_DATA_INHIBIT; |
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140 | 151 | return ret; |
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141 | 152 | } |
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142 | 153 | |
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.. | .. |
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148 | 159 | if (spec_reg == SDHCI_CAPABILITIES_1) { |
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149 | 160 | ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | |
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150 | 161 | SDHCI_SUPPORT_DDR50); |
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151 | | - return ret; |
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152 | | - } |
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153 | | - |
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154 | | - /* |
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155 | | - * Some controllers have unreliable Data Line Active |
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156 | | - * bit for commands with busy signal. This affects |
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157 | | - * Command Inhibit (data) bit. Just ignore it since |
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158 | | - * MMC core driver has already polled card status |
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159 | | - * with CMD13 after any command with busy siganl. |
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160 | | - */ |
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161 | | - if ((spec_reg == SDHCI_PRESENT_STATE) && |
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162 | | - (esdhc->quirk_ignore_data_inhibit == true)) { |
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163 | | - ret = value & ~SDHCI_DATA_INHIBIT; |
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164 | 162 | return ret; |
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165 | 163 | } |
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166 | 164 | |
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