update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/mmc/host/renesas_sdhi_core.c
..
..
@@ -537,7 +537,7 @@
537
537
 			 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
538
538
 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
539
539
 
540
-	if (priv->adjust_hs400_calib_table)
540
+	if (priv->quirks && (priv->quirks->hs400_calib_table || priv->quirks->hs400_bad_taps))
541
541
 		renesas_sdhi_adjust_hs400_mode_disable(host);
542
542
 
543
543
 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
..
..
@@ -556,16 +556,18 @@
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 {
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 	struct renesas_sdhi *priv = host_to_priv(host);
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558
 
559
-	renesas_sdhi_reset_scc(host, priv);
560
-	renesas_sdhi_reset_hs400_mode(host, priv);
561
-	priv->needs_adjust_hs400 = false;
559
+	if (priv->scc_ctl) {
560
+		renesas_sdhi_reset_scc(host, priv);
561
+		renesas_sdhi_reset_hs400_mode(host, priv);
562
+		priv->needs_adjust_hs400 = false;
562
563
 
563
-	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
564
-			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
564
+		sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
565
+				sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
565
566
 
566
-	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
567
-		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
568
-		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
567
+		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
568
+			       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
569
+			       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
570
+	}
569
571
 
570
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 	if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
571
573
 		sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
..
..
@@ -1010,11 +1012,9 @@
1010
1012
 		host->ops.start_signal_voltage_switch =
1011
1013
 			renesas_sdhi_start_signal_voltage_switch;
1012
1014
 		host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1013
-
1014
-		if (of_data && of_data->scc_offset) {
1015
-			priv->scc_ctl = host->ctl + of_data->scc_offset;
1016
-			host->reset = renesas_sdhi_reset;
1017
-		}
1015
+		host->reset = renesas_sdhi_reset;
1016
+	} else {
1017
+		host->sdcard_irq_mask_all = TMIO_MASK_ALL;
1018
1018
 	}
1019
1019
 
1020
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 	/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
..
..
@@ -1070,10 +1070,6 @@
1070
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 			quirks->hs400_calib_table + 1);
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 	}
1072
1072
 
1073
-	ret = tmio_mmc_host_probe(host);
1074
-	if (ret < 0)
1075
-		goto edisclk;
1076
-
1077
1073
 	/* Enable tuning iff we have an SCC and a supported mode */
1078
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 	if (of_data && of_data->scc_offset &&
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 	    (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
..
..
@@ -1098,12 +1094,15 @@
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 		if (!hit)
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 			dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1100
1096
 
1097
+		priv->scc_ctl = host->ctl + of_data->scc_offset;
1101
1098
 		host->check_retune = renesas_sdhi_check_scc_error;
1102
1099
 		host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1103
1100
 		host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1104
1101
 		host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1105
1102
 		host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1106
1103
 	}
1104
+
1105
+	sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
1107
1106
 
1108
1107
 	num_irqs = platform_irq_count(pdev);
1109
1108
 	if (num_irqs < 0) {
..
..
@@ -1130,6 +1129,10 @@
1130
1129
 			goto eirq;
1131
1130
 	}
1132
1131
 
1132
+	ret = tmio_mmc_host_probe(host);
1133
+	if (ret < 0)
1134
+		goto edisclk;
1135
+
1133
1136
 	dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1134
1137
 		 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1135
1138