.. | .. |
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124 | 124 | EXPORT_SYMBOL(rv1106_sdmmc_put_lock); |
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125 | 125 | #endif |
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126 | 126 | |
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| 127 | +#define RV1106_RAMDON_DATA_SIZE 508 |
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| 128 | + |
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127 | 129 | #if defined(CONFIG_DEBUG_FS) |
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128 | 130 | static int dw_mci_req_show(struct seq_file *s, void *v) |
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129 | 131 | { |
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.. | .. |
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525 | 527 | tasklet_schedule(&host->tasklet); |
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526 | 528 | } |
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527 | 529 | |
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528 | | - if (host->need_xfer_timer && |
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529 | | - host->dir_status == DW_MCI_RECV_STATUS) |
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| 530 | + if (host->need_xfer_timer) |
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530 | 531 | del_timer(&host->xfer_timer); |
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531 | 532 | } |
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532 | 533 | |
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.. | .. |
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739 | 740 | if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) { |
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740 | 741 | desc->des0 = desc_last->des0; |
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741 | 742 | desc->des2 = desc_last->des2; |
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742 | | - desc->des1 = 0x8; /* Random dirty data for last one desc */ |
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| 743 | + desc->des1 = RV1106_RAMDON_DATA_SIZE; /* Random dirty data for last one desc */ |
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743 | 744 | desc_last = desc; |
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744 | 745 | } |
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745 | 746 | |
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.. | .. |
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1447 | 1448 | return; |
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1448 | 1449 | } |
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1449 | 1450 | |
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1450 | | - if (host->is_rv1106_sd) { |
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1451 | | - u32 reg; |
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1452 | | - |
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1453 | | - readl_poll_timeout(host->regs + SDMMC_STATUS, reg, |
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1454 | | - reg & BIT(2), USEC_PER_MSEC, 500 * USEC_PER_MSEC); |
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1455 | | - } |
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1456 | | - |
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1457 | 1451 | spin_lock_bh(&host->lock); |
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1458 | 1452 | |
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1459 | 1453 | if (host->is_rv1106_sd) |
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.. | .. |
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1549 | 1543 | slot->host->vqmmc_enabled = true; |
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1550 | 1544 | } |
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1551 | 1545 | |
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| 1546 | +#ifndef CONFIG_ROCKCHIP_THUNDER_BOOT_MMC |
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1552 | 1547 | /* Reset our state machine after powering on */ |
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1553 | 1548 | dw_mci_ctrl_reset(slot->host, |
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1554 | 1549 | SDMMC_CTRL_ALL_RESET_FLAGS); |
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| 1550 | +#endif |
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1555 | 1551 | } |
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1556 | 1552 | |
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1557 | 1553 | /* Adjust clock / bus width after power is up */ |
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.. | .. |
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1874 | 1870 | |
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1875 | 1871 | WARN_ON(host->cmd || host->data); |
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1876 | 1872 | |
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| 1873 | + if (host->need_xfer_timer) |
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| 1874 | + del_timer(&host->xfer_timer); |
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| 1875 | + |
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1877 | 1876 | host->slot->mrq = NULL; |
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1878 | 1877 | host->mrq = NULL; |
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1879 | 1878 | if (!list_empty(&host->queue)) { |
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.. | .. |
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2019 | 2018 | host->bus_hz); |
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2020 | 2019 | |
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2021 | 2020 | /* add a bit spare time */ |
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2022 | | - xfer_ms += 100; |
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2023 | | - |
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| 2021 | + if (host->dir_status == DW_MCI_RECV_STATUS) |
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| 2022 | + xfer_ms += 100; |
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| 2023 | + else |
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| 2024 | + xfer_ms += 2500; |
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2024 | 2025 | spin_lock_irqsave(&host->irq_lock, irqflags); |
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2025 | 2026 | if (!test_bit(EVENT_XFER_COMPLETE, &host->pending_events)) |
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2026 | 2027 | mod_timer(&host->xfer_timer, |
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.. | .. |
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2155 | 2156 | send_stop_abort(host, data); |
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2156 | 2157 | dw_mci_stop_dma(host); |
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2157 | 2158 | state = STATE_DATA_ERROR; |
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| 2159 | + if (host->dir_status == DW_MCI_SEND_STATUS) { |
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| 2160 | + data->bytes_xfered = 0; |
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| 2161 | + data->error = -ETIMEDOUT; |
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| 2162 | + host->data = NULL; |
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| 2163 | + dw_mci_request_end(host, mrq); |
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| 2164 | + goto unlock; |
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| 2165 | + } |
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2158 | 2166 | break; |
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2159 | 2167 | } |
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2160 | 2168 | |
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.. | .. |
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2166 | 2174 | */ |
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2167 | 2175 | if (host->dir_status == DW_MCI_RECV_STATUS) |
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2168 | 2176 | dw_mci_set_drto(host); |
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2169 | | - if (host->need_xfer_timer && |
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2170 | | - host->dir_status == DW_MCI_RECV_STATUS) |
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| 2177 | + if (host->need_xfer_timer) |
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2171 | 2178 | dw_mci_set_xfer_timeout(host); |
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2172 | 2179 | break; |
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2173 | 2180 | } |
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.. | .. |
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2209 | 2216 | */ |
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2210 | 2217 | if (host->dir_status == DW_MCI_RECV_STATUS) |
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2211 | 2218 | dw_mci_set_drto(host); |
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| 2219 | + if (host->need_xfer_timer && host->dir_status == DW_MCI_SEND_STATUS) |
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| 2220 | + dw_mci_set_xfer_timeout(host); |
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2212 | 2221 | break; |
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2213 | 2222 | } |
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2214 | 2223 | |
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.. | .. |
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2225 | 2234 | } |
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2226 | 2235 | |
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2227 | 2236 | /* stop command for open-ended transfer*/ |
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2228 | | - if (data->stop) |
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| 2237 | + if (data->stop) { |
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| 2238 | + if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) { |
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| 2239 | + int fifo_count; |
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| 2240 | + |
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| 2241 | + if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, fifo_count, |
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| 2242 | + ((fifo_count >> 17) & 0x7FF) <= RV1106_RAMDON_DATA_SIZE / 4, |
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| 2243 | + 0, 5000 * USEC_PER_MSEC)) |
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| 2244 | + data->error = -ETIMEDOUT; |
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| 2245 | + udelay(1); |
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| 2246 | + dw_mci_reset(host); |
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| 2247 | + } |
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2229 | 2248 | send_stop_abort(host, data); |
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| 2249 | + } |
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2230 | 2250 | } else { |
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2231 | 2251 | /* |
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2232 | 2252 | * If we don't have a command complete now we'll |
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.. | .. |
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2757 | 2777 | del_timer(&host->cto_timer); |
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2758 | 2778 | mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); |
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2759 | 2779 | host->cmd_status = pending; |
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2760 | | - if ((host->need_xfer_timer) && |
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2761 | | - host->dir_status == DW_MCI_RECV_STATUS) |
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| 2780 | + if (host->need_xfer_timer) |
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2762 | 2781 | del_timer(&host->xfer_timer); |
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2763 | 2782 | smp_wmb(); /* drain writebuffer */ |
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2764 | 2783 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); |
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.. | .. |
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3663 | 3682 | mci_writel(host, INTMASK, ret); |
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3664 | 3683 | } |
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3665 | 3684 | |
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3666 | | - if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) |
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| 3685 | + if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) |
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3667 | 3686 | dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); |
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3668 | 3687 | |
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3669 | 3688 | /* Force setup bus to guarantee available clock output */ |
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