hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/mmc/host/dw_mmc.c
....@@ -124,6 +124,8 @@
124124 EXPORT_SYMBOL(rv1106_sdmmc_put_lock);
125125 #endif
126126
127
+#define RV1106_RAMDON_DATA_SIZE 508
128
+
127129 #if defined(CONFIG_DEBUG_FS)
128130 static int dw_mci_req_show(struct seq_file *s, void *v)
129131 {
....@@ -525,8 +527,7 @@
525527 tasklet_schedule(&host->tasklet);
526528 }
527529
528
- if (host->need_xfer_timer &&
529
- host->dir_status == DW_MCI_RECV_STATUS)
530
+ if (host->need_xfer_timer)
530531 del_timer(&host->xfer_timer);
531532 }
532533
....@@ -739,7 +740,7 @@
739740 if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) {
740741 desc->des0 = desc_last->des0;
741742 desc->des2 = desc_last->des2;
742
- desc->des1 = 0x8; /* Random dirty data for last one desc */
743
+ desc->des1 = RV1106_RAMDON_DATA_SIZE; /* Random dirty data for last one desc */
743744 desc_last = desc;
744745 }
745746
....@@ -1447,13 +1448,6 @@
14471448 return;
14481449 }
14491450
1450
- if (host->is_rv1106_sd) {
1451
- u32 reg;
1452
-
1453
- readl_poll_timeout(host->regs + SDMMC_STATUS, reg,
1454
- reg & BIT(2), USEC_PER_MSEC, 500 * USEC_PER_MSEC);
1455
- }
1456
-
14571451 spin_lock_bh(&host->lock);
14581452
14591453 if (host->is_rv1106_sd)
....@@ -1549,9 +1543,11 @@
15491543 slot->host->vqmmc_enabled = true;
15501544 }
15511545
1546
+#ifndef CONFIG_ROCKCHIP_THUNDER_BOOT_MMC
15521547 /* Reset our state machine after powering on */
15531548 dw_mci_ctrl_reset(slot->host,
15541549 SDMMC_CTRL_ALL_RESET_FLAGS);
1550
+#endif
15551551 }
15561552
15571553 /* Adjust clock / bus width after power is up */
....@@ -1874,6 +1870,9 @@
18741870
18751871 WARN_ON(host->cmd || host->data);
18761872
1873
+ if (host->need_xfer_timer)
1874
+ del_timer(&host->xfer_timer);
1875
+
18771876 host->slot->mrq = NULL;
18781877 host->mrq = NULL;
18791878 if (!list_empty(&host->queue)) {
....@@ -2019,8 +2018,10 @@
20192018 host->bus_hz);
20202019
20212020 /* add a bit spare time */
2022
- xfer_ms += 100;
2023
-
2021
+ if (host->dir_status == DW_MCI_RECV_STATUS)
2022
+ xfer_ms += 100;
2023
+ else
2024
+ xfer_ms += 2500;
20242025 spin_lock_irqsave(&host->irq_lock, irqflags);
20252026 if (!test_bit(EVENT_XFER_COMPLETE, &host->pending_events))
20262027 mod_timer(&host->xfer_timer,
....@@ -2155,6 +2156,13 @@
21552156 send_stop_abort(host, data);
21562157 dw_mci_stop_dma(host);
21572158 state = STATE_DATA_ERROR;
2159
+ if (host->dir_status == DW_MCI_SEND_STATUS) {
2160
+ data->bytes_xfered = 0;
2161
+ data->error = -ETIMEDOUT;
2162
+ host->data = NULL;
2163
+ dw_mci_request_end(host, mrq);
2164
+ goto unlock;
2165
+ }
21582166 break;
21592167 }
21602168
....@@ -2166,8 +2174,7 @@
21662174 */
21672175 if (host->dir_status == DW_MCI_RECV_STATUS)
21682176 dw_mci_set_drto(host);
2169
- if (host->need_xfer_timer &&
2170
- host->dir_status == DW_MCI_RECV_STATUS)
2177
+ if (host->need_xfer_timer)
21712178 dw_mci_set_xfer_timeout(host);
21722179 break;
21732180 }
....@@ -2209,6 +2216,8 @@
22092216 */
22102217 if (host->dir_status == DW_MCI_RECV_STATUS)
22112218 dw_mci_set_drto(host);
2219
+ if (host->need_xfer_timer && host->dir_status == DW_MCI_SEND_STATUS)
2220
+ dw_mci_set_xfer_timeout(host);
22122221 break;
22132222 }
22142223
....@@ -2225,8 +2234,19 @@
22252234 }
22262235
22272236 /* stop command for open-ended transfer*/
2228
- if (data->stop)
2237
+ if (data->stop) {
2238
+ if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) {
2239
+ int fifo_count;
2240
+
2241
+ if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, fifo_count,
2242
+ ((fifo_count >> 17) & 0x7FF) <= RV1106_RAMDON_DATA_SIZE / 4,
2243
+ 0, 5000 * USEC_PER_MSEC))
2244
+ data->error = -ETIMEDOUT;
2245
+ udelay(1);
2246
+ dw_mci_reset(host);
2247
+ }
22292248 send_stop_abort(host, data);
2249
+ }
22302250 } else {
22312251 /*
22322252 * If we don't have a command complete now we'll
....@@ -2757,8 +2777,7 @@
27572777 del_timer(&host->cto_timer);
27582778 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
27592779 host->cmd_status = pending;
2760
- if ((host->need_xfer_timer) &&
2761
- host->dir_status == DW_MCI_RECV_STATUS)
2780
+ if (host->need_xfer_timer)
27622781 del_timer(&host->xfer_timer);
27632782 smp_wmb(); /* drain writebuffer */
27642783 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
....@@ -3663,7 +3682,7 @@
36633682 mci_writel(host, INTMASK, ret);
36643683 }
36653684
3666
- if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3685
+ if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
36673686 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
36683687
36693688 /* Force setup bus to guarantee available clock output */