update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/mfd/rkx110_x120/rkx120_linkrx.c
..
..
@@ -24,6 +24,7 @@
24
24
  #define TRAIN_CLK_SEL_I2S		UPDATE(2, 31, 30)
25
25
  #define DUAL_LVDS_CHANNEL_SWAP		BIT(29)
26
26
  #define VIDEO_FREQ_AUTO_EN		BIT(28)
27
+ #define ENGINE_CFG_MASK		GENMASK(23, 20)
27
28
  #define ENGINE1_2_LANE			BIT(23)
28
29
  #define ENGINE1_EN			BIT(22)
29
30
  #define ENGINE0_2_LANE			BIT(21)
..
..
@@ -36,6 +37,9 @@
36
37
  #define LANE0_DATA_WIDTH_16BIT		UPDATE(1, 13, 12)
37
38
  #define LANE0_DATA_WIDTH_24BIT		UPDATE(2, 13, 12)
38
39
  #define LANE0_DATA_WIDTH_32BIT		UPDATE(3, 13, 12)
40
+ #define LANE1_PKT_LOSE_NUM_CLR		BIT(9)
41
+ #define LANE0_PKT_LOSE_NUM_CLR		BIT(8)
42
+ #define LANE_CFG_MASK			GENMASK(5, 4)
39
43
  #define LANE0_EN			BIT(4)
40
44
  #define LANE1_EN			BIT(5)
41
45
  #define DES_EN				BIT(0)
..
..
@@ -77,6 +81,7 @@
77
81
  #define ORDER_FIFO0_WR_ID(x)		UPDATE(x, 2, 0)
78
82
 
79
83
 #define RKLINK_DES_SOURCE_CFG		LINK_REG(0x0024)
84
+ #define E1_STREAM_CFG_MASK		GENMASK(23, 20)
80
85
  #define E1_CAMERA_SRC_CSI		UPDATE(0, 23, 21)
81
86
  #define E1_CAMERA_SRC_LVDS		UPDATE(1, 23, 21)
82
87
  #define E1_CAMERA_SRC_DVP		UPDATE(2, 23, 21)
..
..
@@ -87,6 +92,7 @@
87
92
  #define E1_DISPLAY_SRC_RGB		UPDATE(5, 23, 21)
88
93
  #define E1_STREAM_CAMERA		UPDATE(0, 20, 20)
89
94
  #define E1_STREAM_DISPLAY		UPDATE(1, 20, 20)
95
+ #define E0_STREAM_CFG_MASK		GENMASK(19, 16)
90
96
  #define E0_CAMERA_SRC_CSI		UPDATE(0, 19, 17)
91
97
  #define E0_CAMERA_SRC_LVDS		UPDATE(1, 19, 17)
92
98
  #define E0_CAMERA_SRC_DVP		UPDATE(2, 19, 17)
..
..
@@ -97,6 +103,7 @@
97
103
  #define E0_DISPLAY_SRC_RGB		UPDATE(5, 19, 17)
98
104
  #define E0_STREAM_CAMERA		UPDATE(0, 16, 16)
99
105
  #define E0_STREAM_DISPLAY		UPDATE(1, 16, 16)
106
+ #define LANE_ID_CFG_MASK		GENMASK(7, 0)
100
107
  #define LANE1_ENGINE_ID(x)		UPDATE(x, 7, 6)
101
108
  #define LANE1_LANE_ID(x)		UPDATE(x, 5, 5)
102
109
  #define LNAE1_ID_SEL(x)		UPDATE(x, 4, 4)
..
..
@@ -104,6 +111,9 @@
104
111
  #define LANE0_LANE_ID(x)		UPDATE(x, 1, 1)
105
112
  #define LNAE0_ID_SEL(x)		UPDATE(x, 0, 0)
106
113
 
114
+#define DES_RKLINK_REC01_PKT_LENGTH	LINK_REG(0x0028)
115
+#define E1_REPKT_LENGTH(x)		UPDATE(x, 29, 16)
116
+#define E0_REPKT_LENGTH(x)		UPDATE(x, 13, 0)
107
117
 #define RKLINK_DES_REG01_ENGIN_DEL	0x0030
108
118
 #define E1_ENGINE_DELAY(x)		UPDATE(x, 31, 16)
109
119
 #define E0_ENGINE_DELAY(x)		UPDATE(x, 15, 0)
..
..
@@ -112,6 +122,42 @@
112
122
 #define E2_FIRST_FRAME_DEL		BIT(6)
113
123
 #define E1_FIRST_FRAME_DEL		BIT(5)
114
124
 #define E0_FIRST_FRAME_DEL		BIT(4)
125
+#define RKLINK_DES_FIFO_STATUS		LINK_REG(0x0084)
126
+ #define AUDIO_FIFO_UNDERRUN		BIT(29)
127
+ #define AUDIO_ORDER_UNDERRUN		BIT(28)
128
+ #define VIDEO_DATA_FIFO_UNDERRUN	BIT(27)
129
+ #define VIDEO_ORDER_UNDERRUN		BIT(26)
130
+ #define CMD_FIFO_UNDERRUN		BIT(25)
131
+ #define E1_ORDER_MIS			BIT(15)
132
+ #define E0_ORDER_MIS			BIT(14)
133
+ #define AUDIO_FIFO_OVERFLOW		BIT(13)
134
+ #define AUDIO_ORDER_OVERFLOW		BIT(12)
135
+ #define VIDEO_DATA_FIFO_OVERFLOW	GENMASK(11, 8)
136
+ #define VIDEO_ORDER_OVERFLOW		GENMASK(7, 4)
137
+ #define CMD_FIFO_OVERFLOW		GENMASK(3, 0)
138
+#define RKLINK_DES_SINK_IRQ_EN		LINK_REG(0x0088)
139
+ #define COMP_NOT_ENOUGH_IRQ_FLAG	BIT(26)
140
+ #define VIDEO_FM_IRQ_FLAG		BIT(25)
141
+ #define AUDIO_FM_IRQ_FLAG		BIT(24)
142
+ #define ORDER_MIS_IRQ_FLAG		BIT(23)
143
+ #define FIFO_UNDERRUN_IRQ_FLAG		BIT(22)
144
+ #define FIFO_OVERFLOW_IRQ_FLAG		BIT(21)
145
+ #define PKT_LOSE_IRQ_FLAG		BIT(20)
146
+ #define LAST_ERROR_IRQ_FLAG		BIT(19)
147
+ #define ECC2BIT_ERROR_IRQ_FLAG		BIT(18)
148
+ #define ECC1BIT_ERROR_IRQ_FLAG		BIT(17)
149
+ #define CRC_ERROR_IRQ_FLAG		BIT(16)
150
+ #define COMP_NOT_ENOUGH_IRQ_OUTPUT_EN	BIT(10)
151
+ #define VIDEO_FM_IRQ_OUTPUT_EN		BIT(9)
152
+ #define AUDIO_FM_IRQ_OUTPUT_EN		BIT(8)
153
+ #define ORDER_MIS_IRQ_OUTPUT_EN	BIT(7)
154
+ #define FIFO_UNDERRUN_IRQ_OUTPUT_EN	BIT(6)
155
+ #define FIFO_OVERFLOW_IRQ_OUTPUT_EN	BIT(5)
156
+ #define PKT_LOSE_IRQ_OUTPUT_EN		BIT(4)
157
+ #define LAST_ERROR_IRQ_OUTPUT_EN	BIT(3)
158
+ #define ECC2BIT_ERROR_IRQ_OUTPUT_EN	BIT(2)
159
+ #define ECC1BIT_ERROR_IRQ_OUTPUT_EN	BIT(1)
160
+ #define CRC_ERROR_IRQ_OUTPUT_EN	BIT(0)
115
161
 
116
162
 #define DES_RKLINK_STOP_CFG		LINK_REG(0x009C)
117
163
  #define STOP_AUDIO			BIT(4)
..
..
@@ -144,6 +190,7 @@
144
190
 #define PCS_REG24(id)			PCS_REG(id, 0x24)
145
191
 #define PCS_REG28(id)			PCS_REG(id, 0x28)
146
192
 #define PCS_REG30(id)			PCS_REG(id, 0x30)
193
+ #define DES_PCS_INI_EN(x)		HIWORD_UPDATE(x, GENMASK(15, 0), 0)
147
194
 #define PCS_REG34(id)			PCS_REG(id, 0x34)
148
195
 #define PCS_REG40(id)			PCS_REG(id, 0x40)
149
196
 
..
..
@@ -222,6 +269,19 @@
222
269
 
223
270
 #define DES_PMA_LOAD0E(id)		PMA_REG(id, 0x48)
224
271
 #define DES_PMA_REG100(id)		PMA_REG(id, 0x100)
272
+
273
+#define DES_PMA_IRQ_EN(id)		PMA_REG(id, 0xF0)
274
+ #define FORCE_INITIAL_IRQ_EN		HIWORD_UPDATE(1, BIT(6), 6)
275
+ #define RX_RDY_NEG_IRQ_EN		HIWORD_UPDATE(1, BIT(5), 5)
276
+ #define RX_LOS_IRQ_EN			HIWORD_UPDATE(1, BIT(4), 4)
277
+ #define RX_RDY_TIMEOUT_IRQ_EN		HIWORD_UPDATE(1, BIT(2), 2)
278
+ #define PLL_LOCK_TIMEOUT_IRQ_EN	HIWORD_UPDATE(1, BIT(0), 0)
279
+#define DES_PMA_IRQ_STATUS(id)		PMA_REG(id, 0xF4)
280
+ #define FORCE_INITIAL_IRQ_STATUS	BIT(6)
281
+ #define RX_RDY_NEG_IRQ_STATUS		BIT(5)
282
+ #define RX_LOS_IRQ_STATUS		BIT(4)
283
+ #define RX_RDY_TIMEOUT_IRQ_STATUS	BIT(2)
284
+ #define PLL_LOCK_TIMEOUT_IRQ_STATUS	BIT(0)
225
285
 
226
286
 static const struct rk_serdes_pt des_pt[] = {
227
287
 	{
..
..
@@ -409,9 +469,9 @@
409
469
 	},
410
470
 };
411
471
 
412
-static int rk_des_get_stream_source(struct rk_serdes_route *route, u32 port, u8 engine_id)
472
+static int rk_des_get_stream_source(u32 stream_type, u32 port, u8 engine_id)
413
473
 {
414
-	if (route->stream_type == STREAM_DISPLAY) {
474
+	if (stream_type == STREAM_DISPLAY) {
415
475
 		if (port & RK_SERDES_RGB_TX)
416
476
 			return engine_id ? E1_DISPLAY_SRC_RGB : E0_DISPLAY_SRC_RGB;
417
477
 		else if (port & RK_SERDES_LVDS_TX0)
..
..
@@ -472,139 +532,267 @@
472
532
 			      E1_FIRST_FRAME_DEL | E0_FIRST_FRAME_DEL);
473
533
 }
474
534
 
475
-static int rk120_link_rx_cfg(struct rk_serdes *serdes, struct rk_serdes_route *route, u8 remote_id)
535
+static int rk120_linkrx_des_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
476
536
 {
477
-	struct hwclk *hwclk = serdes->chip[remote_id].hwclk;
478
-	struct i2c_client *client;
479
-	u32 stream_type;
480
-	u32 rx_src;
481
-	u32 ctrl_val, mask, val;
482
-	u32 lane0_dsource_id, lane1_dsource_id;
483
-	bool is_rx_dual_lanes;
484
-	bool is_rx_dual_channels;
537
+	struct i2c_client *client = serdes->chip[dev_id].client;
485
538
 
486
-	if (route->stream_type == STREAM_DISPLAY) {
487
-		client = serdes->chip[remote_id].client;
488
-		stream_type = E0_STREAM_DISPLAY;
539
+	serdes->i2c_update_bits(client, RKLINK_DES_LANE_ENGINE_CFG, DES_EN, enable ? DES_EN : 0);
540
+
541
+	return 0;
542
+}
543
+
544
+static int rk120_linkrx_video_fm_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
545
+{
546
+	struct i2c_client *client = serdes->chip[dev_id].client;
547
+
548
+	serdes->i2c_update_bits(client, RKLINK_DES_LANE_ENGINE_CFG, VIDEO_FREQ_AUTO_EN,
549
+				enable ? VIDEO_FREQ_AUTO_EN : 0);
550
+
551
+	return 0;
552
+}
553
+
554
+static int rk120_linkrx_engine_lane_enable(struct rk_serdes *serdes, u8 dev_id,
555
+					   bool dual_channels, bool dual_lanes)
556
+{
557
+	struct i2c_client *client = serdes->chip[dev_id].client;
558
+	u32 val = 0;
559
+
560
+	/*
561
+	 * config engine and lane as fallow:
562
+	 * 1.linkrx receive 1 channel data in 1 lane, enable engine0 and engine0 use 1 lane.
563
+	 * 2.linkrx receive 1 channel data in 2 lane, enable engine0 and engine0 user 2 lanes.
564
+	 * 3.linkrx receive 2 channel data in 1 lane, enable engine0, enagine1. engine0 use
565
+	 *   1 lane, engine1 use 1 lane.
566
+	 * 4.linkrx receive 2 channel data in 2 lane, enable engine0, enagine1. engine0 use
567
+	 *   1 lane, engine1 use 1 lane.
568
+	 */
569
+	if (dual_channels) {
570
+		val |= ENGINE0_EN | ENGINE1_EN;
489
571
 	} else {
490
-		client = serdes->chip[DEVICE_LOCAL].client;
491
-		stream_type = E0_STREAM_CAMERA;
572
+		val |= ENGINE0_EN;
573
+		if (dual_lanes)
574
+			val |= ENGINE0_2_LANE;
492
575
 	}
493
576
 
494
-	is_rx_dual_lanes = (serdes->route_flag & ROUTE_MULTI_LANE) &&
495
-			   !(serdes->route_flag & ROUTE_MULTI_REMOTE);
496
-	is_rx_dual_channels = (serdes->route_flag & ROUTE_MULTI_CHANNEL) &&
497
-			       !(serdes->route_flag & ROUTE_MULTI_REMOTE);
577
+	serdes->i2c_update_bits(client, RKLINK_DES_LANE_ENGINE_CFG, ENGINE_CFG_MASK, val);
498
578
 
499
-	serdes->i2c_read_reg(client, RKLINK_DES_LANE_ENGINE_CFG, &ctrl_val);
579
+	return 0;
580
+}
500
581
 
501
-	ctrl_val &= ~LANE1_EN;
502
-	ctrl_val |= LANE0_EN;
503
-	ctrl_val |= ENGINE0_EN;
504
-	if (is_rx_dual_lanes) {
505
-		ctrl_val |= LANE1_EN;
506
-		if (is_rx_dual_channels)
507
-			ctrl_val |= ENGINE1_EN;
508
-		else
509
-			ctrl_val |= ENGINE0_2_LANE;
510
-	} else {
511
-		if (is_rx_dual_channels)
512
-			ctrl_val |= ENGINE1_EN;
513
-	}
514
-	serdes->i2c_write_reg(client, RKLINK_DES_LANE_ENGINE_CFG, ctrl_val);
582
+static int rk120_linkrx_lane_enable(struct rk_serdes *serdes, u8 dev_id, u32 lanes)
583
+{
584
+	struct i2c_client *client = serdes->chip[dev_id].client;
585
+	u32 val;
515
586
 
516
-	mask = LANE0_ENGINE_CFG_MASK;
517
-	val = LANE0_ENGINE0;
518
-	if (is_rx_dual_lanes) {
519
-		if (is_rx_dual_channels) {
520
-			mask |= LANE1_ENGINE_CFG_MASK;
521
-			val |= LANE1_ENGINE1;
587
+	/*
588
+	 * when 1 lane connect to linkrx, enable lane0;
589
+	 * when 2 lane connect to linkrx, enable lane0 and lane1;
590
+	 */
591
+
592
+	if (lanes == 1)
593
+		val = LANE0_EN;
594
+	else if (lanes == 2)
595
+		val = LANE0_EN | LANE1_EN;
596
+	else
597
+		val = 0;
598
+
599
+	serdes->i2c_update_bits(client, RKLINK_DES_LANE_ENGINE_CFG, LANE_CFG_MASK, val);
600
+
601
+	return 0;
602
+}
603
+
604
+static int rk120_linkrx_lane_engine_dst_cfg(struct rk_serdes *serdes, u8 dev_id,
605
+					     bool dual_channels, bool dual_lanes)
606
+{
607
+	struct i2c_client *client = serdes->chip[dev_id].client;
608
+	u32 mask, val;
609
+
610
+	/*
611
+	 * config lane dst engine as fallow:
612
+	 * 1. 1 channel 1 lane: lane0 data send to engine0
613
+	 * 2. 1 channel 2 lane: lane0 data send to engine0, lane1 data send to engine0
614
+	 * 3. 2 channel 1 lane: lane0 data send to engine0, lane0 data send to engine1
615
+	 * 4. 2 channel 2 lane: lane0 data send to engine0, lane1 data send to engine1
616
+	 */
617
+	if (dual_channels) {
618
+		if (dual_lanes) {
619
+			mask = LANE0_ENGINE_CFG_MASK | LANE1_ENGINE_CFG_MASK;
620
+			val = LANE0_ENGINE0 | LANE1_ENGINE1;
522
621
 		} else {
523
-			mask |= LANE1_ENGINE_CFG_MASK;
524
-			val |= LANE1_ENGINE0;
622
+			mask = LANE0_ENGINE_CFG_MASK | LANE1_ENGINE_CFG_MASK;
623
+			val = LANE0_ENGINE0 | LANE0_ENGINE1;
525
624
 		}
526
625
 	} else {
527
-		if (is_rx_dual_channels)
528
-			val |= LANE0_ENGINE1;
529
-	}
530
626
 
627
+		if (dual_lanes) {
628
+			mask = LANE0_ENGINE_CFG_MASK | LANE1_ENGINE_CFG_MASK;
629
+			val = LANE0_ENGINE0 | LANE1_ENGINE0;
630
+		} else {
631
+			mask = LANE0_ENGINE_CFG_MASK | LANE1_ENGINE_CFG_MASK;
632
+			val = LANE0_ENGINE0 | LANE1_ENGINE1;
633
+		}
634
+	}
531
635
 	serdes->i2c_update_bits(client, RKLINK_DES_LANE_ENGINE_DST, mask, val);
532
636
 
533
-	serdes->i2c_read_reg(client, RKLINK_DES_SOURCE_CFG, &val);
637
+	return 0;
638
+}
534
639
 
535
-	val &= ~(LANE0_ENGINE_ID(1) | LANE0_LANE_ID(1) | LANE1_ENGINE_ID(1) |
536
-		 LANE1_LANE_ID(1) | LNAE0_ID_SEL(1) | LNAE1_ID_SEL(1));
640
+static int rk120_linkrx_config_pkt_length(struct rk_serdes *serdes, u8 dev_id, u32 length)
641
+{
642
+	struct i2c_client *client = serdes->chip[dev_id].client;
537
643
 
538
-	if (is_rx_dual_lanes) {
539
-		if (is_rx_dual_channels) {
540
-			val |= LANE0_ENGINE_ID(0);
541
-			val |= LANE0_LANE_ID(0);
542
-			val |= LNAE0_ID_SEL(1);
543
-			val |= LANE1_ENGINE_ID(1);
544
-			val |= LANE1_LANE_ID(0);
545
-			val |= LNAE1_ID_SEL(1);
546
-			stream_type |= E1_STREAM_DISPLAY;
644
+	serdes->i2c_write_reg(client, DES_RKLINK_REC01_PKT_LENGTH, E0_REPKT_LENGTH(length) |
645
+			      E1_REPKT_LENGTH(length));
646
+
647
+	return 0;
648
+}
649
+
650
+static int rk120_linkrx_lane_id_cfg(struct rk_serdes *serdes, u8 dev_id,
651
+				     bool dual_channels, bool dual_lanes)
652
+{
653
+	struct i2c_client *client = serdes->chip[dev_id].client;
654
+	u32 val;
655
+
656
+	if (dual_channels) {
657
+		if (dual_lanes) {
658
+			val = LANE0_ENGINE_ID(0) | LANE0_LANE_ID(0) | LNAE0_ID_SEL(1) |
659
+			      LANE1_ENGINE_ID(1) | LANE1_LANE_ID(0) | LNAE1_ID_SEL(1);
547
660
 		} else {
548
-			val |= LANE0_ENGINE_ID(0);
549
-			val |= LANE0_LANE_ID(0);
550
-			val |= LNAE0_ID_SEL(1);
551
-			val |= LANE1_ENGINE_ID(0);
552
-			val |= LANE1_LANE_ID(1);
553
-			val |= LNAE0_ID_SEL(1);
661
+			val = LANE0_ENGINE_ID(0) | LANE0_LANE_ID(0) | LANE1_ENGINE_ID(1) |
662
+			      LANE1_LANE_ID(0);
554
663
 		}
555
664
 	} else {
556
-		if (is_rx_dual_channels) {
557
-			val |= LANE0_ENGINE_ID(0);
558
-			val |= LANE0_LANE_ID(0);
559
-			val |= LANE1_ENGINE_ID(1);
560
-			val |= LANE1_LANE_ID(0);
561
-			stream_type |= E1_STREAM_DISPLAY;
665
+		if (dual_lanes) {
666
+			val = LANE0_ENGINE_ID(0) | LANE0_LANE_ID(0) | LNAE0_ID_SEL(1) |
667
+			      LANE1_ENGINE_ID(0) | LANE1_LANE_ID(1) | LNAE1_ID_SEL(1);
562
668
 		} else {
563
-			val |= LNAE0_ID_SEL(1);
669
+			val = LNAE0_ID_SEL(1);
564
670
 		}
565
671
 	}
566
-	val |= stream_type;
567
-	if (remote_id == DEVICE_REMOTE0)
568
-		rx_src = rk_des_get_stream_source(route, route->remote0_port0, 0);
569
-	else
570
-		rx_src = rk_des_get_stream_source(route, route->remote1_port0, 0);
571
-	val |= rx_src;
572
-	if (is_rx_dual_channels) {
573
-		rx_src = rk_des_get_stream_source(route, route->remote0_port1, 1);
574
-		val |= rx_src;
575
-	}
576
-	serdes->i2c_write_reg(client, RKLINK_DES_SOURCE_CFG, val);
577
672
 
578
-	if (is_rx_dual_lanes || is_rx_dual_channels) {
579
-		mask = DATA_FIFO0_WR_ID_MASK | DATA_FIFO1_WR_ID_MASK | DATA_FIFO2_WR_ID_MASK |
580
-			DATA_FIFO3_WR_ID_MASK;
581
-		mask |= DATA_FIFO0_RD_ID_MASK | DATA_FIFO1_RD_ID_MASK | DATA_FIFO2_RD_ID_MASK |
582
-			DATA_FIFO3_RD_ID_MASK;
583
-		if (is_rx_dual_channels) {
584
-			lane0_dsource_id = (0 << 1) | 0;
585
-			lane1_dsource_id = (1 << 1) | 0;
586
-		} else {
673
+	serdes->i2c_update_bits(client, RKLINK_DES_SOURCE_CFG, LANE_ID_CFG_MASK, val);
674
+
675
+	return 0;
676
+}
677
+
678
+static int rk120_linkrx_stream_type_cfg(struct rk_serdes *serdes, u32 stream_type,
679
+					 u8 dev_id, u32 port, u32 engine_id)
680
+{
681
+	struct i2c_client *client = serdes->chip[dev_id].client;
682
+	u32 val, mask, rx_src;
683
+
684
+	mask = engine_id ? E1_STREAM_CFG_MASK : E0_STREAM_CFG_MASK;
685
+	if (stream_type == STREAM_DISPLAY)
686
+		val =  engine_id ? E1_STREAM_DISPLAY : E0_STREAM_DISPLAY;
687
+	else
688
+		val =  engine_id ? E1_STREAM_CAMERA : E0_STREAM_CAMERA;
689
+
690
+	rx_src = rk_des_get_stream_source(stream_type, port, engine_id);
691
+	val |= rx_src;
692
+	serdes->i2c_update_bits(client, RKLINK_DES_SOURCE_CFG, mask, val);
693
+
694
+	return 0;
695
+}
696
+
697
+static int rk120_linkrx_data_and_order_id_cfg(struct rk_serdes *serdes, u8 dev_id,
698
+					       bool dual_channels, bool dual_lanes)
699
+{
700
+	struct i2c_client *client = serdes->chip[dev_id].client;
701
+	u32 lane0_dsource_id, lane1_dsource_id;
702
+	u32 data_id_mask;
703
+	u32 order_id_mask;
704
+	u32 val;
705
+
706
+	data_id_mask = DATA_FIFO0_WR_ID_MASK | DATA_FIFO1_WR_ID_MASK |
707
+		       DATA_FIFO2_WR_ID_MASK | DATA_FIFO3_WR_ID_MASK |
708
+		       DATA_FIFO0_RD_ID_MASK | DATA_FIFO1_RD_ID_MASK |
709
+		       DATA_FIFO2_RD_ID_MASK | DATA_FIFO3_RD_ID_MASK;
710
+	order_id_mask = ORDER_FIFO0_WR_ID_MASK | ORDER_FIFO1_WR_ID_MASK |
711
+			ORDER_FIFO0_RD_ID_MASK | ORDER_FIFO1_RD_ID_MASK;
712
+
713
+	if (dual_channels) {
714
+		lane0_dsource_id = (0 << 1) | 0;
715
+		lane1_dsource_id = (1 << 1) | 0;
716
+	} else {
717
+		if (dual_lanes) {
587
718
 			lane0_dsource_id = (0 << 1) | 0;
588
719
 			lane1_dsource_id = (0 << 1) | 1;
720
+		} else {
721
+			lane0_dsource_id = (0 << 1) | 0;
722
+			lane1_dsource_id = (1 << 1) | 0;
589
723
 		}
590
-		val = DATA_FIFO0_WR_ID(lane0_dsource_id) | DATA_FIFO1_WR_ID(lane0_dsource_id);
591
-		val |= DATA_FIFO0_RD_ID(lane0_dsource_id) | DATA_FIFO1_RD_ID(lane0_dsource_id);
592
-
593
-		val |= DATA_FIFO2_WR_ID(lane1_dsource_id) | DATA_FIFO3_WR_ID(lane1_dsource_id);
594
-		val |= DATA_FIFO2_RD_ID(lane1_dsource_id) | DATA_FIFO3_RD_ID(lane1_dsource_id);
595
-
596
-		serdes->i2c_update_bits(client, RKLINK_DES_DATA_ID_CFG, mask, val);
597
-
598
-		mask = ORDER_FIFO0_WR_ID_MASK | ORDER_FIFO1_WR_ID_MASK |
599
-			ORDER_FIFO0_RD_ID_MASK | ORDER_FIFO1_RD_ID_MASK;
600
-		val = ORDER_FIFO0_WR_ID(lane0_dsource_id) | ORDER_FIFO1_WR_ID(lane1_dsource_id) |
601
-			ORDER_FIFO0_RD_ID(lane0_dsource_id) | ORDER_FIFO1_RD_ID(lane1_dsource_id);
602
-
603
-		serdes->i2c_update_bits(client, RKLINK_DES_ORDER_ID_CFG, mask, val);
604
724
 	}
605
725
 
606
-	ctrl_val |= DES_EN;
607
-	serdes->i2c_write_reg(client, RKLINK_DES_LANE_ENGINE_CFG, ctrl_val);
726
+	val = DATA_FIFO0_WR_ID(lane0_dsource_id) | DATA_FIFO1_WR_ID(lane0_dsource_id) |
727
+	      DATA_FIFO0_RD_ID(lane0_dsource_id) | DATA_FIFO1_RD_ID(lane0_dsource_id) |
728
+	      DATA_FIFO2_WR_ID(lane1_dsource_id) | DATA_FIFO3_WR_ID(lane1_dsource_id) |
729
+	      DATA_FIFO2_RD_ID(lane1_dsource_id) | DATA_FIFO3_RD_ID(lane1_dsource_id);
730
+	serdes->i2c_update_bits(client, RKLINK_DES_DATA_ID_CFG, data_id_mask, val);
731
+
732
+	val = ORDER_FIFO0_WR_ID(lane0_dsource_id) | ORDER_FIFO1_WR_ID(lane1_dsource_id) |
733
+	      ORDER_FIFO0_RD_ID(lane0_dsource_id) | ORDER_FIFO1_RD_ID(lane1_dsource_id);
734
+
735
+	serdes->i2c_update_bits(client, RKLINK_DES_ORDER_ID_CFG, order_id_mask, val);
736
+
737
+	return 0;
738
+}
739
+
740
+static int rk120_display_linkrx_cfg(struct rk_serdes *serdes,
741
+				    struct rk_serdes_route *route, u8 dev_id)
742
+{
743
+	struct hwclk *hwclk = serdes->chip[dev_id].hwclk;
744
+	bool is_rx_dual_lanes = false;
745
+	bool is_rx_dual_channels = false;
746
+
747
+	if (serdes->route_nr == 1) {
748
+		is_rx_dual_lanes = (serdes->lane_nr == 2) &&
749
+				   !(route->route_flag & ROUTE_MULTI_REMOTE);
750
+		is_rx_dual_channels = (route->route_flag & ROUTE_MULTI_CHANNEL) &&
751
+				       !(route->route_flag & ROUTE_MULTI_REMOTE);
752
+	} else {
753
+		is_rx_dual_lanes = (serdes->lane_nr == 2) && (serdes->remote_nr == 1);
754
+		is_rx_dual_channels = (serdes->channel_nr == 2) && (serdes->remote_nr == 1);
755
+	}
756
+
757
+	rk120_linkrx_video_fm_enable(serdes, dev_id, true);
758
+	rk120_linkrx_engine_lane_enable(serdes, dev_id, is_rx_dual_channels, is_rx_dual_lanes);
759
+	rk120_linkrx_lane_enable(serdes, dev_id, is_rx_dual_lanes ? 2 : 1);
760
+
761
+	rk120_linkrx_lane_engine_dst_cfg(serdes, dev_id, is_rx_dual_channels, is_rx_dual_lanes);
762
+	rk120_linkrx_lane_id_cfg(serdes, dev_id, is_rx_dual_channels, is_rx_dual_lanes);
763
+	if (route->local_port0) {
764
+		if (dev_id == DEVICE_REMOTE0) {
765
+			rk120_linkrx_stream_type_cfg(serdes, route->stream_type, dev_id,
766
+						     route->remote0_port0, 0);
767
+			if (is_rx_dual_channels)
768
+				rk120_linkrx_stream_type_cfg(serdes, route->stream_type, dev_id,
769
+						     route->remote0_port1, 1);
770
+		} else {
771
+			rk120_linkrx_stream_type_cfg(serdes, route->stream_type, dev_id,
772
+						     route->remote1_port0, 0);
773
+		}
774
+	} else {
775
+		rk120_linkrx_stream_type_cfg(serdes, route->stream_type, dev_id,
776
+					     route->remote1_port0, 0);
777
+	}
778
+
779
+	rk120_linkrx_data_and_order_id_cfg(serdes, dev_id, is_rx_dual_channels,
780
+					    is_rx_dual_lanes);
781
+	if (serdes->version == SERDES_V1) {
782
+		/*
783
+		 * The serdes v1 have a bug when enable video suspend function, which
784
+		 * is used to enhance the i2c frequency. A workaround ways to do it is
785
+		 * reducing the video packet length:
786
+		 * length = ((hactive x 24 / 32 / 16) + 15) / 16 * 16
787
+		 */
788
+		u32 length;
789
+
790
+		length = route->vm.hactive * 24 / 32 / 16;
791
+		length = (length + 15) / 16 * 16;
792
+		rk120_linkrx_config_pkt_length(serdes, dev_id, length);
793
+	}
794
+
795
+	rk120_linkrx_des_enable(serdes, dev_id, true);
608
796
 
609
797
 	hwclk_set_rate(hwclk, RKX120_CPS_E0_CLK_RKLINK_RX_PRE, route->vm.pixelclock);
610
798
 	dev_info(serdes->dev, "RKX120_CPS_E0_CLK_RKLINK_RX_PRE:%d\n",
..
..
@@ -616,17 +804,17 @@
616
804
 	}
617
805
 
618
806
 	if (route->remote0_port0 == RK_SERDES_RGB_TX || route->remote1_port0 == RK_SERDES_RGB_TX)
619
-		rk_serdes_link_rx_rgb_enable(serdes, route, remote_id);
807
+		rk_serdes_link_rx_rgb_enable(serdes, route, dev_id);
620
808
 
621
809
 	if (route->remote0_port0 == RK_SERDES_LVDS_TX0 ||
622
810
 	    route->remote1_port0 == RK_SERDES_LVDS_TX0 ||
623
811
 	    route->remote0_port0 == RK_SERDES_LVDS_TX1 ||
624
812
 	    route->remote1_port0 == RK_SERDES_LVDS_TX1 ||
625
813
 	    route->remote0_port0 == RK_SERDES_DUAL_LVDS_TX)
626
-		rk_serdes_link_rx_lvds_enable(serdes, route, remote_id);
814
+		rk_serdes_link_rx_lvds_enable(serdes, route, dev_id);
627
815
 
628
816
 	if (route->remote0_port0 == RK_SERDES_DSI_TX0 || route->remote1_port0 == RK_SERDES_DSI_TX0)
629
-		rk_serdes_link_rx_dsi_enable(serdes, route, remote_id);
817
+		rk_serdes_link_rx_dsi_enable(serdes, route, dev_id);
630
818
 
631
819
 	return 0;
632
820
 }
..
..
@@ -643,17 +831,18 @@
643
831
 	return 0;
644
832
 }
645
833
 
646
-int rkx120_linkrx_enable(struct rk_serdes *serdes, struct rk_serdes_route *route, u8 remote_id)
834
+int rkx120_display_linkrx_enable(struct rk_serdes *serdes,
835
+				 struct rk_serdes_route *route, u8 dev_id)
647
836
 {
648
-	rk120_link_rx_cfg(serdes, route, remote_id);
837
+	rk120_display_linkrx_cfg(serdes, route, dev_id);
649
838
 
650
-	rk120_des_pcs_cfg(serdes, route, remote_id, 0);
651
-	rk120_des_pma_cfg(serdes, route, remote_id, 0);
652
-	if ((serdes->route_flag & ROUTE_MULTI_LANE) &&
653
-	    !(serdes->route_flag & ROUTE_MULTI_REMOTE)) {
654
-		rk120_des_pcs_cfg(serdes, route, remote_id, 1);
655
-		rk120_des_pma_cfg(serdes, route, remote_id, 1);
839
+	rk120_des_pcs_cfg(serdes, route, dev_id, 0);
840
+	rk120_des_pma_cfg(serdes, route, dev_id, 0);
841
+	if ((serdes->lane_nr == 2) && (serdes->remote_nr == 1)) {
842
+		rk120_des_pcs_cfg(serdes, route, dev_id, 1);
843
+		rk120_des_pma_cfg(serdes, route, dev_id, 1);
656
844
 	}
845
+
657
846
 
658
847
 	return 0;
659
848
 }
..
..
@@ -691,7 +880,7 @@
691
880
 	}
692
881
 }
693
882
 
694
-void rkx120_linkrx_wait_link_ready(struct rk_serdes *serdes, u8 id)
883
+int rkx120_linkrx_wait_link_ready(struct rk_serdes *serdes, u8 id)
695
884
 {
696
885
 	struct i2c_client *client = serdes->chip[DEVICE_LOCAL].client;
697
886
 	u32 val;
..
..
@@ -711,6 +900,8 @@
711
900
 		dev_err(&client->dev, "wait link ready timeout: 0x%08x\n", val);
712
901
 	else
713
902
 		dev_info(&client->dev, "link success: 0x%08x\n", val);
903
+
904
+	return ret;
714
905
 }
715
906
 
716
907
 static void rkx120_pma_link_config(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
..
..
@@ -795,3 +986,354 @@
795
986
 
796
987
 	serdes->i2c_update_bits(client, DES_GRF_SOC_CON4, mask, val);
797
988
 }
989
+
990
+
991
+static void rkx120_linkrx_irq_enable(struct rk_serdes *serdes, u8 dev_id)
992
+{
993
+	struct i2c_client *client = serdes->chip[dev_id].client;
994
+
995
+	serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, DES_IRQ_LINK_EN);
996
+
997
+	serdes->i2c_write_reg(client, RKLINK_DES_SINK_IRQ_EN, FIFO_UNDERRUN_IRQ_OUTPUT_EN |
998
+			      FIFO_OVERFLOW_IRQ_OUTPUT_EN);
999
+}
1000
+
1001
+static void rkx120_linkrx_irq_disable(struct rk_serdes *serdes, u8 dev_id)
1002
+{
1003
+	struct i2c_client *client = serdes->chip[dev_id].client;
1004
+	u32 val = 0;
1005
+
1006
+	serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, DES_IRQ_LINK_DIS);
1007
+
1008
+	serdes->i2c_read_reg(client, RKLINK_DES_SINK_IRQ_EN, &val);
1009
+	val &= ~(FIFO_UNDERRUN_IRQ_OUTPUT_EN | FIFO_OVERFLOW_IRQ_OUTPUT_EN);
1010
+	serdes->i2c_write_reg(client, RKLINK_DES_SINK_IRQ_EN, val);
1011
+}
1012
+
1013
+static void rkx120_linkrx_fifo_handler(struct rk_serdes *serdes, u8 dev_id)
1014
+{
1015
+	struct i2c_client *client = serdes->chip[dev_id].client;
1016
+	u32 value;
1017
+
1018
+	serdes->i2c_read_reg(client, RKLINK_DES_FIFO_STATUS, &value);
1019
+	dev_err(serdes->dev, "des rklink fifo status:0x%x\n", value);
1020
+
1021
+	if (value & AUDIO_FIFO_UNDERRUN)
1022
+		dev_err(serdes->dev, "linkrx audio fifo underrun\n");
1023
+	if (value & AUDIO_ORDER_UNDERRUN)
1024
+		dev_err(serdes->dev, "linkrx audio order underrun\n");
1025
+	if (value & VIDEO_DATA_FIFO_UNDERRUN)
1026
+		dev_err(serdes->dev, "linkrx video data fifo underrun\n");
1027
+	if (value & VIDEO_ORDER_UNDERRUN)
1028
+		dev_err(serdes->dev, "linkrx video order underrun\n");
1029
+	if (value & CMD_FIFO_UNDERRUN)
1030
+		dev_err(serdes->dev, "linkrx cmd fifo underrun\n");
1031
+	if (value & E1_ORDER_MIS)
1032
+		dev_err(serdes->dev, "linkrx e1 order miss\n");
1033
+	if (value & E0_ORDER_MIS)
1034
+		dev_err(serdes->dev, "linkrx e0 order miss\n");
1035
+	if (value & AUDIO_FIFO_OVERFLOW)
1036
+		dev_err(serdes->dev, "linkrx audio fifo overflow\n");
1037
+	if (value & AUDIO_ORDER_OVERFLOW)
1038
+		dev_err(serdes->dev, "linkrx audio order overflow\n");
1039
+	if (value & VIDEO_DATA_FIFO_OVERFLOW)
1040
+		dev_err(serdes->dev, "linkrx video data fifo overflow\n");
1041
+	if (value & VIDEO_ORDER_OVERFLOW)
1042
+		dev_err(serdes->dev, "linkrx video order overflow\n");
1043
+	if (value & CMD_FIFO_OVERFLOW)
1044
+		dev_err(serdes->dev, "linkrx cmd fifo overflow\n");
1045
+
1046
+	serdes->i2c_write_reg(client, RKLINK_DES_FIFO_STATUS, value);
1047
+}
1048
+
1049
+static void rkx120_linkrx_irq_handler(struct rk_serdes *serdes, u8 dev_id)
1050
+{
1051
+	struct i2c_client *client = serdes->chip[dev_id].client;
1052
+	u32 flag, value;
1053
+	int i = 0;
1054
+
1055
+	serdes->i2c_read_reg(client, RKLINK_DES_SINK_IRQ_EN, &flag);
1056
+	flag &= COMP_NOT_ENOUGH_IRQ_FLAG | VIDEO_FM_IRQ_FLAG | AUDIO_FM_IRQ_FLAG |
1057
+		ORDER_MIS_IRQ_FLAG | FIFO_UNDERRUN_IRQ_FLAG | FIFO_OVERFLOW_IRQ_FLAG |
1058
+		PKT_LOSE_IRQ_FLAG | LAST_ERROR_IRQ_FLAG | ECC2BIT_ERROR_IRQ_FLAG |
1059
+		ECC1BIT_ERROR_IRQ_FLAG | CRC_ERROR_IRQ_FLAG;
1060
+	dev_info(serdes->dev, "linkrx irq flag:0x%08x\n", flag);
1061
+	while (flag) {
1062
+		switch (flag & BIT(i)) {
1063
+		case COMP_NOT_ENOUGH_IRQ_FLAG:
1064
+			break;
1065
+		case VIDEO_FM_IRQ_FLAG:
1066
+			break;
1067
+		case AUDIO_FM_IRQ_FLAG:
1068
+			break;
1069
+		case ORDER_MIS_IRQ_FLAG:
1070
+		case FIFO_UNDERRUN_IRQ_FLAG:
1071
+		case FIFO_OVERFLOW_IRQ_FLAG:
1072
+			flag &= ~(ORDER_MIS_IRQ_FLAG | FIFO_UNDERRUN_IRQ_FLAG |
1073
+				FIFO_OVERFLOW_IRQ_FLAG);
1074
+			rkx120_linkrx_fifo_handler(serdes, dev_id);
1075
+			break;
1076
+		case PKT_LOSE_IRQ_FLAG:
1077
+			/* clear pkt lost irq flag */
1078
+			serdes->i2c_read_reg(client, RKLINK_DES_LANE_ENGINE_CFG, &value);
1079
+			value |= LANE0_PKT_LOSE_NUM_CLR | LANE1_PKT_LOSE_NUM_CLR;
1080
+			serdes->i2c_write_reg(client, RKLINK_DES_LANE_ENGINE_CFG, value);
1081
+			break;
1082
+		case LAST_ERROR_IRQ_FLAG:
1083
+		case ECC2BIT_ERROR_IRQ_FLAG:
1084
+		case ECC1BIT_ERROR_IRQ_FLAG:
1085
+		case CRC_ERROR_IRQ_FLAG:
1086
+			flag &= ~(LAST_ERROR_IRQ_FLAG | ECC2BIT_ERROR_IRQ_FLAG |
1087
+				ECC1BIT_ERROR_IRQ_FLAG | CRC_ERROR_IRQ_FLAG);
1088
+			serdes->i2c_read_reg(client, RKLINK_DES_SINK_IRQ_EN, &value);
1089
+			dev_info(serdes->dev, "linkrx ecc crc result:0x%08x\n", value);
1090
+			/* clear ecc crc irq flag */
1091
+			serdes->i2c_write_reg(client, RKLINK_DES_SINK_IRQ_EN, value);
1092
+			break;
1093
+		default:
1094
+			break;
1095
+		}
1096
+		flag &= ~BIT(i);
1097
+		i++;
1098
+	}
1099
+}
1100
+static void rkx120_pcs_irq_enable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
1101
+{
1102
+	struct i2c_client *client = serdes->chip[dev_id].client;
1103
+	u32 val = 0;
1104
+
1105
+	val = pcs_id ? DES_IRQ_PCS1_EN : DES_IRQ_PCS0_EN;
1106
+	serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, val);
1107
+
1108
+	serdes->i2c_write_reg(client, PCS_REG30(pcs_id), DES_PCS_INI_EN(0xffff));
1109
+}
1110
+
1111
+static void rkx120_pcs_irq_disable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
1112
+{
1113
+	struct i2c_client *client = serdes->chip[dev_id].client;
1114
+	u32 val = 0;
1115
+
1116
+	val = pcs_id ? DES_IRQ_PCS1_DIS : DES_IRQ_PCS0_DIS;
1117
+	serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, val);
1118
+
1119
+	serdes->i2c_write_reg(client, PCS_REG30(pcs_id), DES_PCS_INI_EN(0));
1120
+}
1121
+
1122
+static void rkx120_pcs_irq_handler(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
1123
+{
1124
+	struct i2c_client *client = serdes->chip[dev_id].client;
1125
+	u32 value;
1126
+
1127
+	serdes->i2c_read_reg(client, PCS_REG20(pcs_id), &value);
1128
+	dev_info(serdes->dev, "des pcs%d fatal status:0x%08x\n", pcs_id, value);
1129
+
1130
+	/* clear fatal status */
1131
+	serdes->i2c_write_reg(client, PCS_REG10(pcs_id), 0xffffffff);
1132
+	serdes->i2c_write_reg(client, PCS_REG10(pcs_id), 0xffff0000);
1133
+}
1134
+
1135
+static void rkx120_pma_irq_enable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
1136
+{
1137
+	struct i2c_client *client = serdes->chip[dev_id].client;
1138
+	u32 val = 0;
1139
+
1140
+	val = pcs_id ? DES_IRQ_PMA_ADAPT1_EN : DES_IRQ_PMA_ADAPT0_EN;
1141
+	serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, val);
1142
+
1143
+	serdes->i2c_write_reg(client, DES_PMA_IRQ_EN(pcs_id), FORCE_INITIAL_IRQ_EN |
1144
+			      RX_RDY_NEG_IRQ_EN | RX_LOS_IRQ_EN | RX_RDY_TIMEOUT_IRQ_EN |
1145
+			      PLL_LOCK_TIMEOUT_IRQ_EN);
1146
+}
1147
+
1148
+static void rkx120_pma_irq_disable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
1149
+{
1150
+	struct i2c_client *client = serdes->chip[dev_id].client;
1151
+	u32 val = 0;
1152
+
1153
+	val = pcs_id ? DES_IRQ_PMA_ADAPT1_DIS : DES_IRQ_PMA_ADAPT0_DIS;
1154
+	serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, val);
1155
+
1156
+	serdes->i2c_write_reg(client, DES_PMA_IRQ_EN(pcs_id), 0);
1157
+}
1158
+
1159
+static void rkx120_pma_irq_handler(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
1160
+{
1161
+	struct i2c_client *client = serdes->chip[dev_id].client;
1162
+	u32 value;
1163
+
1164
+	serdes->i2c_read_reg(client, DES_PMA_IRQ_STATUS(pcs_id), &value);
1165
+	dev_info(serdes->dev, "des pma%d irq status:0x%08x\n", pcs_id, value);
1166
+
1167
+	if (value & FORCE_INITIAL_IRQ_STATUS)
1168
+		dev_info(serdes->dev, "des pma trig force initial pulse status\n");
1169
+	else if (value & RX_RDY_NEG_IRQ_STATUS)
1170
+		dev_info(serdes->dev, "des pma trig rx rdy neg status\n");
1171
+	else if (value & RX_LOS_IRQ_STATUS)
1172
+		dev_info(serdes->dev, "des pma trig rx los status\n");
1173
+	else if (value & RX_RDY_TIMEOUT_IRQ_STATUS)
1174
+		dev_info(serdes->dev, "des pma trig rx rdy timeout status\n");
1175
+	else if (value & PLL_LOCK_TIMEOUT_IRQ_STATUS)
1176
+		dev_info(serdes->dev, "des pma trig pll lock timeout status\n");
1177
+
1178
+	/* clear pma irq status */
1179
+	serdes->i2c_write_reg(client, DES_PMA_IRQ_STATUS(pcs_id), value);
1180
+}
1181
+
1182
+static void rkx120_remote_irq_enable(struct rk_serdes *serdes, u8 dev_id)
1183
+{
1184
+	struct i2c_client *client = serdes->chip[dev_id].client;
1185
+
1186
+	if (serdes->stream_type == STREAM_CAMERA) {
1187
+		serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, DES_IRQ_REMOTE_EN);
1188
+		rkx110_irq_enable(serdes, DEVICE_REMOTE0);
1189
+	}
1190
+}
1191
+
1192
+static void rkx120_remote_irq_disable(struct rk_serdes *serdes, u8 dev_id)
1193
+{
1194
+	struct i2c_client *client = serdes->chip[dev_id].client;
1195
+
1196
+	if (serdes->stream_type == STREAM_CAMERA) {
1197
+		serdes->i2c_write_reg(client, DES_GRF_IRQ_EN, DES_IRQ_REMOTE_DIS);
1198
+		rkx110_irq_disable(serdes, DEVICE_REMOTE0);
1199
+	}
1200
+}
1201
+
1202
+static void rkx120_remote_irq_handler(struct rk_serdes *serdes, u8 dev_id)
1203
+{
1204
+	if (serdes->stream_type == STREAM_CAMERA)
1205
+		rkx110_irq_handler(serdes, DEVICE_REMOTE0);
1206
+}
1207
+
1208
+void rkx120_irq_enable(struct rk_serdes *serdes, u8 dev_id)
1209
+{
1210
+	/* enable pcs irq */
1211
+	rkx120_pcs_irq_enable(serdes, 0, dev_id);
1212
+
1213
+	/* enable efuse irq */
1214
+
1215
+	/* enable gpio irq */
1216
+
1217
+	/* enable csitx irq */
1218
+
1219
+	/* enable mipi dsi host irq */
1220
+
1221
+	/* enable pma adapt irq */
1222
+	rkx120_pma_irq_enable(serdes, 0, dev_id);
1223
+
1224
+	/* enable remote irq and other lane irq */
1225
+	rkx120_remote_irq_enable(serdes, dev_id);
1226
+
1227
+	/* enable pwm irq */
1228
+
1229
+	/* enable dvp tx irq */
1230
+
1231
+	/* enable link irq */
1232
+	rkx120_linkrx_irq_enable(serdes, dev_id);
1233
+
1234
+	/* enable ext irq */
1235
+
1236
+	/* enable ext irq */
1237
+}
1238
+
1239
+void rkx120_irq_disable(struct rk_serdes *serdes, u8 dev_id)
1240
+{
1241
+	/* disable pcs irq */
1242
+	rkx120_pcs_irq_disable(serdes, 0, dev_id);
1243
+
1244
+	/* disable efuse irq */
1245
+
1246
+	/* disable gpio irq */
1247
+
1248
+	/* disable csitx irq */
1249
+
1250
+	/* disable mipi dsi host irq */
1251
+
1252
+	/* disable pma adapt irq */
1253
+	rkx120_pma_irq_disable(serdes, 0, dev_id);
1254
+
1255
+	/* disable remote irq */
1256
+	rkx120_remote_irq_disable(serdes, dev_id);
1257
+
1258
+	/* disable pwm irq */
1259
+
1260
+	/* disable dvp tx irq */
1261
+
1262
+	/* disable link irq */
1263
+	rkx120_linkrx_irq_disable(serdes, dev_id);
1264
+
1265
+	/* disable ext irq */
1266
+}
1267
+
1268
+int rkx120_irq_handler(struct rk_serdes *serdes, u8 dev_id)
1269
+{
1270
+	struct i2c_client *client = serdes->chip[dev_id].client;
1271
+	u32 status = 0;
1272
+	u32 mask = 0;
1273
+	u32 i = 0;
1274
+
1275
+	serdes->i2c_read_reg(client, DES_GRF_IRQ_EN, &mask);
1276
+	serdes->i2c_read_reg(client, DES_GRF_IRQ_STATUS, &status);
1277
+	dev_info(serdes->dev, "dev%d get the des irq status:0x%08x\n", dev_id, status);
1278
+	status &= mask;
1279
+
1280
+	while (status) {
1281
+		switch (status & BIT(i)) {
1282
+		case DES_IRQ_PCS0:
1283
+			rkx120_pcs_irq_handler(serdes, 0, dev_id);
1284
+			break;
1285
+		case DES_IRQ_PCS1:
1286
+			rkx120_pcs_irq_handler(serdes, 1, dev_id);
1287
+			break;
1288
+		case DES_IRQ_EFUSE:
1289
+			/* TBD */
1290
+			break;
1291
+		case DES_IRQ_GPIO0:
1292
+			/* TBD */
1293
+			break;
1294
+		case DES_IRQ_GPIO1:
1295
+			/* TBD */
1296
+			break;
1297
+		case DES_IRQ_CSITX0:
1298
+			/* TBD */
1299
+			break;
1300
+		case DES_IRQ_CSITX1:
1301
+			/* TBD */
1302
+			break;
1303
+		case DES_IRQ_MIPI_DSI_HOST:
1304
+			/* TBD */
1305
+			break;
1306
+		case DES_IRQ_PMA_ADAPT0:
1307
+			rkx120_pma_irq_handler(serdes, 0, dev_id);
1308
+			break;
1309
+		case DES_IRQ_PMA_ADAPT1:
1310
+			rkx120_pma_irq_handler(serdes, 1, dev_id);
1311
+			break;
1312
+		case DES_IRQ_REMOTE:
1313
+			rkx120_remote_irq_handler(serdes, dev_id);
1314
+			break;
1315
+		case DES_IRQ_PWM:
1316
+			/* TBD */
1317
+			break;
1318
+		case DES_IRQ_DVP_TX:
1319
+			/* TBD */
1320
+			break;
1321
+		case DES_IRQ_LINK:
1322
+			rkx120_linkrx_irq_handler(serdes, dev_id);
1323
+			break;
1324
+		case DES_IRQ_EXT:
1325
+			/* TBD */
1326
+			break;
1327
+		case DES_IRQ_OTHER_LANE:
1328
+			/* TBD */
1329
+			break;
1330
+		default:
1331
+			break;
1332
+		}
1333
+		status &= ~BIT(i);
1334
+		i++;
1335
+	}
1336
+
1337
+	return 0;
1338
+}
1339
+