~hc/RK356X_SDK_RELEASE.git

..	..	@@ -11,4 +11,188 @@
11	11	#ifndef __MFD_SERDES_MAXIM_MAX96789_H__
12	12	#define __MFD_SERDES_MAXIM_MAX96789_H__
13	13
	14	+#include <linux/bitfield.h>
	15	+
	16	+#define GPIO_A_REG(gpio) (0x02be + ((gpio) * 3))
	17	+#define GPIO_B_REG(gpio) (0x02bf + ((gpio) * 3))
	18	+#define GPIO_C_REG(gpio) (0x02c0 + ((gpio) * 3))
	19	+
	20	+/* 0000h */
	21	+#define DEV_ADDR GENMASK(7, 1)
	22	+#define CFG_BLOCK BIT(0)
	23	+
	24	+/* 0001h */
	25	+#define IIC_2_EN BIT(7)
	26	+#define IIC_1_EN BIT(6)
	27	+#define DIS_REM_CC BIT(4)
	28	+#define TX_RATE GENMASK(3, 2)
	29	+
	30	+/* 0002h */
	31	+#define VID_TX_EN_U BIT(7)
	32	+#define VID_TX_EN_Z BIT(6)
	33	+#define VID_TX_EN_Y BIT(5)
	34	+#define VID_TX_EN_X BIT(4)
	35	+#define AUD_TX_EN_Y BIT(3)
	36	+#define AUD_TX_EN_X BIT(2)
	37	+
	38	+/* 0003h */
	39	+#define UART_2_EN BIT(5)
	40	+#define UART_1_EN BIT(4)
	41	+
	42	+/* 0004h */
	43	+#define GMSL2_B BIT(7)
	44	+#define GMSL2_A BIT(6)
	45	+#define LINK_EN_B BIT(5)
	46	+#define LINK_EN_A BIT(4)
	47	+#define AUD_TX_SRC_Y BIT(1)
	48	+#define AUD_TX_SRC_X BIT(0)
	49	+
	50	+
	51	+/* 0005h */
	52	+#define LOCK_EN BIT(7)
	53	+#define ERRB_EN BIT(6)
	54	+#define PU_LF3 BIT(3)
	55	+#define PU_LF2 BIT(2)
	56	+#define PU_LF1 BIT(1)
	57	+#define PU_LF0 BIT(0)
	58	+
	59	+/* 0006h */
	60	+#define RCLKEN BIT(5)
	61	+
	62	+/* 0010h */
	63	+#define RESET_ALL BIT(7)
	64	+#define RESET_LINK BIT(6)
	65	+#define RESET_ONESHOT BIT(5)
	66	+#define AUTO_LINK BIT(4)
	67	+#define SLEEP BIT(3)
	68	+#define REG_ENABLE BIT(2)
	69	+#define LINK_CFG GENMASK(1, 0)
	70	+
	71	+/* 0013h */
	72	+#define LINK_MODE GENMASK(5, 4)
	73	+#define LOCKED BIT(3)
	74	+
	75	+/* 0026h */
	76	+#define LF_1 GENMASK(6, 4)
	77	+#define LF_0 GENMASK(2, 0)
	78	+
	79	+/* 0048h */
	80	+#define REM_MS_EN BIT(5)
	81	+#define LOC_MS_EN BIT(4)
	82	+
	83	+/* 0053h */
	84	+#define TX_SPLIT_MASK_B BIT(5)
	85	+#define TX_SPLIT_MASK_A BIT(4)
	86	+#define TX_STR_SEL GENMASK(1, 0)
	87	+
	88	+/* 0140h */
	89	+#define AUD_RX_EN BIT(0)
	90	+
	91	+/* 0170h */
	92	+#define SPI_EN BIT(0)
	93	+
	94	+/* 01e5h */
	95	+#define PATGEN_MODE GENMASK(1, 0)
	96	+
	97	+/* 02beh */
	98	+#define RES_CFG BIT(7)
	99	+#define TX_PRIO BIT(6)
	100	+#define TX_COMP_EN BIT(5)
	101	+#define GPIO_OUT BIT(4)
	102	+#define GPIO_IN BIT(3)
	103	+#define GPIO_RX_EN BIT(2)
	104	+#define GPIO_TX_EN BIT(1)
	105	+#define GPIO_OUT_DIS BIT(0)
	106	+
	107	+/* 02bfh */
	108	+#define PULL_UPDN_SEL GENMASK(7, 6)
	109	+#define OUT_TYPE BIT(5)
	110	+#define GPIO_TX_ID GENMASK(4, 0)
	111	+
	112	+/* 02c0h */
	113	+#define OVR_RES_CFG BIT(7)
	114	+#define GPIO_RX_ID GENMASK(4, 0)
	115	+
	116	+/* 0311h */
	117	+#define START_PORTBU BIT(7)
	118	+#define START_PORTBZ BIT(6)
	119	+#define START_PORTBY BIT(5)
	120	+#define START_PORTBX BIT(4)
	121	+#define START_PORTAU BIT(3)
	122	+#define START_PORTAZ BIT(2)
	123	+#define START_PORTAY BIT(1)
	124	+#define START_PORTAX BIT(0)
	125	+
	126	+/* 032ah */
	127	+#define DV_LOCK BIT(7)
	128	+#define DV_SWP_AB BIT(6)
	129	+#define LINE_ALT BIT(5)
	130	+#define DV_CONV BIT(2)
	131	+#define DV_SPL BIT(1)
	132	+#define DV_EN BIT(0)
	133	+
	134	+/* 0330h */
	135	+#define PHY_CONFIG GENMASK(2, 0)
	136	+#define MIPI_RX_RESET BIT(3)
	137	+
	138	+/* 0331h */
	139	+#define NUM_LANES GENMASK(1, 0)
	140	+
	141	+/* 0385h */
	142	+#define DPI_HSYNC_WIDTH_L GENMASK(7, 0)
	143	+
	144	+/* 0386h */
	145	+#define DPI_VYSNC_WIDTH_L GENMASK(7, 0)
	146	+
	147	+/* 0387h */
	148	+#define DPI_HSYNC_WIDTH_H GENMASK(3, 0)
	149	+#define DPI_VSYNC_WIDTH_H GENMASK(7, 4)
	150	+
	151	+/* 03a4h */
	152	+#define DPI_DE_SKEW_SEL BIT(1)
	153	+#define DPI_DESKEW_EN BIT(0)
	154	+
	155	+/* 03a5h */
	156	+#define DPI_VFP_L GENMASK(7, 0)
	157	+
	158	+/* 03a6h */
	159	+#define DPI_VFP_H GENMASK(3, 0)
	160	+#define DPI_VBP_L GENMASK(7, 4)
	161	+
	162	+/* 03a7h */
	163	+#define DPI_VBP_H GENMASK(7, 0)
	164	+
	165	+/* 03a8h */
	166	+#define DPI_VACT_L GENMASK(7, 0)
	167	+
	168	+/* 03a9h */
	169	+#define DPI_VACT_H GENMASK(3, 0)
	170	+
	171	+/* 03aah */
	172	+#define DPI_HFP_L GENMASK(7, 0)
	173	+
	174	+/* 03abh */
	175	+#define DPI_HFP_H GENMASK(3, 0)
	176	+#define DPI_HBP_L GENMASK(7, 4)
	177	+
	178	+/* 03ach */
	179	+#define DPI_HBP_H GENMASK(7, 0)
	180	+
	181	+/* 03adh */
	182	+#define DPI_HACT_L GENMASK(7, 0)
	183	+
	184	+/* 03aeh */
	185	+#define DPI_HACT_H GENMASK(4, 0)
	186	+
	187	+/* 055dh */
	188	+#define VS_DET BIT(5)
	189	+#define HS_DET BIT(4)
	190	+
	191	+enum link_mode {
	192	+ DUAL_LINK,
	193	+ LINKA,
	194	+ LINKB,
	195	+ SPLITTER_MODE,
	196	+};
	197	+
14	198	#endif