update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/mfd/display-serdes/maxim/maxim-max96789.c
..
..
@@ -13,13 +13,17 @@
13
13
 static bool max96789_volatile_reg(struct device *dev, unsigned int reg)
14
14
 {
15
15
 	switch (reg) {
16
-	case 0x0076:
17
-	case 0x0086:
18
-	case 0x0100:
19
-	case 0x0200 ... 0x02ce:
20
-	case 0x7000:
21
-	case 0x7070:
22
-	case 0x7074:
16
+	case 0x0002:
17
+	case 0x0010:
18
+	case 0x0013:
19
+	case 0x0053:
20
+	case 0x0057:
21
+	case 0x02be ... 0x02fc:
22
+	case 0x0311:
23
+	case 0x032a:
24
+	case 0x0330 ... 0x0331:
25
+	case 0x0385 ... 0x0387:
26
+	case 0x03a4 ... 0x03ae:
23
27
 		return false;
24
28
 	default:
25
29
 		return true;
..
..
@@ -30,9 +34,28 @@
30
34
 	.name = "max96789",
31
35
 	.reg_bits = 16,
32
36
 	.val_bits = 8,
33
-	.max_register = 0x8000,
37
+	.max_register = 0x2000,
34
38
 	.volatile_reg = max96789_volatile_reg,
35
39
 	.cache_type = REGCACHE_RBTREE,
40
+};
41
+
42
+struct serdes_function_data {
43
+	u8 gpio_out_dis:1;
44
+	u8 gpio_tx_en:1;
45
+	u8 gpio_rx_en:1;
46
+	u8 gpio_tx_id;
47
+	u8 gpio_rx_id;
48
+};
49
+
50
+struct config_desc {
51
+	u16 reg;
52
+	u8 mask;
53
+	u8 val;
54
+};
55
+
56
+struct serdes_group_data {
57
+	const struct config_desc *configs;
58
+	int num_configs;
36
59
 };
37
60
 
38
61
 static int MAX96789_MFP0_pins[] = {0};
..
..
@@ -58,6 +81,8 @@
58
81
 static int MAX96789_MFP18_pins[] = {18};
59
82
 static int MAX96789_MFP19_pins[] = {19};
60
83
 static int MAX96789_MFP20_pins[] = {20};
84
+static int MAX96789_I2C_pins[] = {19, 20};
85
+static int MAX96789_UART_pins[] = {19, 20};
61
86
 
62
87
 #define GROUP_DESC(nm) \
63
88
 { \
..
..
@@ -66,12 +91,91 @@
66
91
 	.num_pins = ARRAY_SIZE(nm ## _pins), \
67
92
 }
68
93
 
69
-struct serdes_function_data {
70
-	u8 gpio_out_dis:1;
71
-	u8 gpio_tx_en:1;
72
-	u8 gpio_rx_en:1;
73
-	u8 gpio_tx_id;
74
-	u8 gpio_rx_id;
94
+#define GROUP_DESC_CONFIG(nm) \
95
+{ \
96
+	.name = #nm, \
97
+	.pins = nm ## _pins, \
98
+	.num_pins = ARRAY_SIZE(nm ## _pins), \
99
+	.data = (void *)(const struct serdes_group_data []) { \
100
+		{ \
101
+			.configs = nm ## _configs, \
102
+			.num_configs = ARRAY_SIZE(nm ## _configs), \
103
+		} \
104
+	}, \
105
+}
106
+
107
+static const struct config_desc MAX96789_MFP0_configs[] = {
108
+	{ 0x0005, LOCK_EN, 0 },
109
+	{ 0x0048, LOC_MS_EN, 0 },
110
+};
111
+
112
+static const struct config_desc MAX96789_MFP1_configs[] = {
113
+	{ 0x0005, ERRB_EN, 0 },
114
+};
115
+
116
+static const struct config_desc MAX96789_MFP4_configs[] = {
117
+	{ 0x070, SPI_EN, 0 },
118
+};
119
+
120
+static const struct config_desc MAX96789_MFP5_configs[] = {
121
+	{ 0x006, RCLKEN, 0 },
122
+};
123
+
124
+static const struct config_desc MAX96789_MFP7_configs[] = {
125
+	{ 0x0002, AUD_TX_EN_X, 0 },
126
+	{ 0x0002, AUD_TX_EN_Y, 0 }
127
+};
128
+
129
+static const struct config_desc MAX96789_MFP8_configs[] = {
130
+	{ 0x0002, AUD_TX_EN_X, 0 },
131
+	{ 0x0002, AUD_TX_EN_Y, 0 }
132
+};
133
+
134
+static const struct config_desc MAX96789_MFP9_configs[] = {
135
+	{ 0x0002, AUD_TX_EN_X, 0 },
136
+	{ 0x0002, AUD_TX_EN_Y, 0 }
137
+};
138
+
139
+static const struct config_desc MAX96789_MFP10_configs[] = {
140
+	{ 0x0001, IIC_2_EN, 0 },
141
+	{ 0x0003, UART_2_EN, 0 },
142
+	{ 0x0140, AUD_RX_EN, 0 },
143
+};
144
+
145
+static const struct config_desc MAX96789_MFP11_configs[] = {
146
+	{ 0x0001, IIC_2_EN, 0 },
147
+	{ 0x0003, UART_2_EN, 0 },
148
+	{ 0x0140, AUD_RX_EN, 0 },
149
+};
150
+
151
+static const struct config_desc MAX96789_MFP12_configs[] = {
152
+	{ 0x0140, AUD_RX_EN, 0 },
153
+};
154
+
155
+static const struct config_desc MAX96789_MFP13_configs[] = {
156
+	{ 0x0005, PU_LF0, 0 },
157
+};
158
+
159
+static const struct config_desc MAX96789_MFP14_configs[] = {
160
+	{ 0x0005, PU_LF1, 0 },
161
+};
162
+
163
+static const struct config_desc MAX96789_MFP15_configs[] = {
164
+	{ 0x0005, PU_LF2, 0 },
165
+};
166
+
167
+static const struct config_desc MAX96789_MFP16_configs[] = {
168
+	{ 0x0005, PU_LF3, 0 },
169
+};
170
+
171
+static const struct config_desc MAX96789_MFP17_configs[] = {
172
+	{ 0x0001, IIC_1_EN, 0 },
173
+	{ 0x0003, UART_1_EN, 0 },
174
+};
175
+
176
+static const struct config_desc MAX96789_MFP18_configs[] = {
177
+	{ 0x0001, IIC_1_EN, 0 },
178
+	{ 0x0003, UART_1_EN, 0 },
75
179
 };
76
180
 
77
181
 static const char *serdes_gpio_groups[] = {
..
..
@@ -85,19 +189,29 @@
85
189
 	"MAX96789_MFP20",
86
190
 };
87
191
 
192
+static const char *MAX96789_I2C_groups[] = { "MAX96789_I2C" };
193
+static const char *MAX96789_UART_groups[] = { "MAX96789_UART" };
194
+
195
+#define FUNCTION_DESC(nm) \
196
+{ \
197
+	.name = #nm, \
198
+	.group_names = nm##_groups, \
199
+	.num_group_names = ARRAY_SIZE(nm##_groups), \
200
+} \
201
+
88
202
 #define FUNCTION_DESC_GPIO_INPUT(id) \
89
203
 { \
90
-	.name = "DES_GPIO"#id"_INPUT", \
204
+	.name = "DES_RXID"#id"_TO_SER", \
91
205
 	.group_names = serdes_gpio_groups, \
92
206
 	.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
93
207
 	.data = (void *)(const struct serdes_function_data []) { \
94
-		{ .gpio_rx_en = 1, .gpio_rx_id = id } \
208
+		{ .gpio_out_dis = 0, .gpio_rx_en = 1, .gpio_rx_id = id } \
95
209
 	}, \
96
210
 } \
97
211
 
98
212
 #define FUNCTION_DESC_GPIO_OUTPUT(id) \
99
213
 { \
100
-	.name = "DES_GPIO"#id"_OUTPUT", \
214
+	.name = "SER_TXID"#id"_TO_DES", \
101
215
 	.group_names = serdes_gpio_groups, \
102
216
 	.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
103
217
 	.data = (void *)(const struct serdes_function_data []) { \
..
..
@@ -132,29 +246,31 @@
132
246
 };
133
247
 
134
248
 static struct group_desc max96789_groups_desc[] = {
135
-	GROUP_DESC(MAX96789_MFP0),
136
-	GROUP_DESC(MAX96789_MFP1),
249
+	GROUP_DESC_CONFIG(MAX96789_MFP0),
250
+	GROUP_DESC_CONFIG(MAX96789_MFP1),
137
251
 	GROUP_DESC(MAX96789_MFP2),
138
252
 	GROUP_DESC(MAX96789_MFP3),
139
-	GROUP_DESC(MAX96789_MFP4),
140
-	GROUP_DESC(MAX96789_MFP5),
253
+	GROUP_DESC_CONFIG(MAX96789_MFP4),
254
+	GROUP_DESC_CONFIG(MAX96789_MFP5),
141
255
 	GROUP_DESC(MAX96789_MFP6),
142
-	GROUP_DESC(MAX96789_MFP7),
256
+	GROUP_DESC_CONFIG(MAX96789_MFP7),
143
257
 
144
-	GROUP_DESC(MAX96789_MFP8),
145
-	GROUP_DESC(MAX96789_MFP9),
146
-	GROUP_DESC(MAX96789_MFP10),
147
-	GROUP_DESC(MAX96789_MFP11),
148
-	GROUP_DESC(MAX96789_MFP12),
149
-	GROUP_DESC(MAX96789_MFP13),
150
-	GROUP_DESC(MAX96789_MFP14),
151
-	GROUP_DESC(MAX96789_MFP15),
258
+	GROUP_DESC_CONFIG(MAX96789_MFP8),
259
+	GROUP_DESC_CONFIG(MAX96789_MFP9),
260
+	GROUP_DESC_CONFIG(MAX96789_MFP10),
261
+	GROUP_DESC_CONFIG(MAX96789_MFP11),
262
+	GROUP_DESC_CONFIG(MAX96789_MFP12),
263
+	GROUP_DESC_CONFIG(MAX96789_MFP13),
264
+	GROUP_DESC_CONFIG(MAX96789_MFP14),
265
+	GROUP_DESC_CONFIG(MAX96789_MFP15),
152
266
 
153
-	GROUP_DESC(MAX96789_MFP16),
154
-	GROUP_DESC(MAX96789_MFP17),
155
-	GROUP_DESC(MAX96789_MFP18),
267
+	GROUP_DESC_CONFIG(MAX96789_MFP16),
268
+	GROUP_DESC_CONFIG(MAX96789_MFP17),
269
+	GROUP_DESC_CONFIG(MAX96789_MFP18),
156
270
 	GROUP_DESC(MAX96789_MFP19),
157
271
 	GROUP_DESC(MAX96789_MFP20),
272
+	GROUP_DESC(MAX96789_I2C),
273
+	GROUP_DESC(MAX96789_UART),
158
274
 };
159
275
 
160
276
 static struct function_desc max96789_functions_desc[] = {
..
..
@@ -206,6 +322,8 @@
206
322
 	FUNCTION_DESC_GPIO_OUTPUT(19),
207
323
 	FUNCTION_DESC_GPIO_OUTPUT(20),
208
324
 
325
+	FUNCTION_DESC(MAX96789_I2C),
326
+	FUNCTION_DESC(MAX96789_UART),
209
327
 };
210
328
 
211
329
 static struct serdes_chip_pinctrl_info max96789_pinctrl_info = {
..
..
@@ -222,40 +340,297 @@
222
340
 	return 0;
223
341
 }
224
342
 
343
+static bool max96789_bridge_link_locked(struct serdes *serdes)
344
+{
345
+	u32 val;
346
+
347
+	if (serdes->lock_gpio) {
348
+		val = gpiod_get_value_cansleep(serdes->lock_gpio);
349
+		SERDES_DBG_CHIP("%s: lock_gpio val=%d\n", __func__, val);
350
+		return val;
351
+	}
352
+
353
+	if (serdes_reg_read(serdes, 0x0013, &val)) {
354
+		SERDES_DBG_CHIP("%s: false val=%d\n", __func__, val);
355
+		return false;
356
+	}
357
+
358
+	if (!FIELD_GET(LOCKED, val)) {
359
+		SERDES_DBG_CHIP("%s: false val=%d\n", __func__, val);
360
+		return false;
361
+	}
362
+
363
+	SERDES_DBG_CHIP("%s: return true\n", __func__);
364
+
365
+	return true;
366
+}
367
+
368
+static int max96789_bridge_attach(struct serdes *serdes)
369
+{
370
+	if (max96789_bridge_link_locked(serdes))
371
+		serdes->serdes_bridge->status = connector_status_connected;
372
+	else
373
+		serdes->serdes_bridge->status = connector_status_disconnected;
374
+
375
+	return 0;
376
+}
377
+
378
+static enum drm_connector_status
379
+max96789_bridge_detect(struct serdes *serdes)
380
+{
381
+	struct serdes_bridge *serdes_bridge = serdes->serdes_bridge;
382
+	enum drm_connector_status status = connector_status_connected;
383
+
384
+	if (!drm_kms_helper_is_poll_worker())
385
+		return serdes_bridge->status;
386
+
387
+	if (!max96789_bridge_link_locked(serdes)) {
388
+		status = connector_status_disconnected;
389
+		goto out;
390
+	}
391
+
392
+	if (extcon_get_state(serdes->extcon, EXTCON_JACK_VIDEO_OUT)) {
393
+		if (atomic_cmpxchg(&serdes_bridge->triggered, 1, 0)) {
394
+			status = connector_status_disconnected;
395
+			goto out;
396
+		}
397
+
398
+	} else {
399
+		atomic_set(&serdes_bridge->triggered, 0);
400
+	}
401
+
402
+	if (serdes_bridge->next_bridge && (serdes_bridge->next_bridge->ops & DRM_BRIDGE_OP_DETECT))
403
+		return drm_bridge_detect(serdes_bridge->next_bridge);
404
+
405
+out:
406
+	serdes_bridge->status = status;
407
+	SERDES_DBG_CHIP("%s: status=%d\n", __func__, status);
408
+	return status;
409
+}
410
+
225
411
 static int max96789_bridge_enable(struct serdes *serdes)
226
412
 {
227
-	return 0;
413
+	int ret = 0;
414
+
415
+	SERDES_DBG_CHIP("%s: serdes chip %s ret=%d\n", __func__, serdes->chip_data->name, ret);
416
+	return ret;
228
417
 }
229
418
 
230
419
 static int max96789_bridge_disable(struct serdes *serdes)
231
420
 {
232
-	return 0;
421
+	int ret = 0;
422
+
423
+	return ret;
233
424
 }
234
425
 
235
426
 static struct serdes_chip_bridge_ops max96789_bridge_ops = {
236
427
 	.init = max96789_bridge_init,
428
+	.attach = max96789_bridge_attach,
429
+	.detect = max96789_bridge_detect,
237
430
 	.enable = max96789_bridge_enable,
238
431
 	.disable = max96789_bridge_disable,
239
432
 };
240
433
 
241
-static int max96789_pinctrl_config_get(struct serdes *serdes,
242
-				       unsigned int pin,
243
-				       unsigned long *config)
434
+static int max96789_pinctrl_set_mux(struct serdes *serdes,
435
+				    unsigned int function, unsigned int group)
244
436
 {
437
+	struct serdes_pinctrl *pinctrl = serdes->pinctrl;
438
+	struct function_desc *func;
439
+	struct group_desc *grp;
440
+	int i;
441
+
442
+	func = pinmux_generic_get_function(pinctrl->pctl, function);
443
+	if (!func)
444
+		return -EINVAL;
445
+
446
+	grp = pinctrl_generic_get_group(pinctrl->pctl, group);
447
+	if (!grp)
448
+		return -EINVAL;
449
+
450
+	SERDES_DBG_CHIP("%s: serdes chip %s func=%s data=%p group=%s data=%p, num_pin=%d\n",
451
+			__func__, serdes->chip_data->name, func->name,
452
+			func->data, grp->name, grp->data, grp->num_pins);
453
+
454
+	if (func->data) {
455
+		struct serdes_function_data *fdata = func->data;
456
+
457
+		for (i = 0; i < grp->num_pins; i++) {
458
+			serdes_set_bits(serdes, GPIO_A_REG(grp->pins[i] - pinctrl->pin_base),
459
+					GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
460
+					FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
461
+					FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
462
+					FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en));
463
+
464
+			if (fdata->gpio_tx_en)
465
+				serdes_set_bits(serdes,
466
+						GPIO_B_REG(grp->pins[i] - pinctrl->pin_base),
467
+						GPIO_TX_ID,
468
+						FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
469
+
470
+			if (fdata->gpio_rx_en)
471
+				serdes_set_bits(serdes,
472
+						GPIO_C_REG(grp->pins[i] - pinctrl->pin_base),
473
+						GPIO_RX_ID,
474
+						FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
475
+		}
476
+	}
477
+
478
+	if (grp->data) {
479
+		struct serdes_group_data *gdata = grp->data;
480
+
481
+		for (i = 0; i < gdata->num_configs; i++) {
482
+			const struct config_desc *config = &gdata->configs[i];
483
+
484
+			serdes_set_bits(serdes, config->reg,
485
+					config->mask, config->val);
486
+		}
487
+	}
488
+
489
+	return 0;
490
+}
491
+
492
+static int max96789_pinctrl_config_get(struct serdes *serdes,
493
+				       unsigned int pin, unsigned long *config)
494
+{
495
+	enum pin_config_param param = pinconf_to_config_param(*config);
496
+	unsigned int gpio_a_reg, gpio_b_reg;
497
+	u16 arg = 0;
498
+
499
+	serdes_reg_read(serdes, GPIO_A_REG(pin), &gpio_a_reg);
500
+	serdes_reg_read(serdes, GPIO_B_REG(pin), &gpio_b_reg);
501
+
502
+	SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
503
+			serdes->chip_data->name, pin, param);
504
+
505
+	switch (param) {
506
+	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
507
+		if (FIELD_GET(OUT_TYPE, gpio_b_reg))
508
+			return -EINVAL;
509
+		break;
510
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
511
+		if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
512
+			return -EINVAL;
513
+		break;
514
+	case PIN_CONFIG_BIAS_DISABLE:
515
+		if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
516
+			return -EINVAL;
517
+		break;
518
+	case PIN_CONFIG_BIAS_PULL_UP:
519
+		if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
520
+			return -EINVAL;
521
+		switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
522
+		case 0:
523
+			arg = 40000;
524
+			break;
525
+		case 1:
526
+			arg = 10000;
527
+			break;
528
+		}
529
+		break;
530
+	case PIN_CONFIG_BIAS_PULL_DOWN:
531
+		if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
532
+			return -EINVAL;
533
+		switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
534
+		case 0:
535
+			arg = 40000;
536
+			break;
537
+		case 1:
538
+			arg = 10000;
539
+			break;
540
+		}
541
+		break;
542
+	case PIN_CONFIG_OUTPUT:
543
+		if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
544
+			return -EINVAL;
545
+
546
+		arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
547
+		break;
548
+	default:
549
+		return -EOPNOTSUPP;
550
+	}
551
+
552
+	*config = pinconf_to_config_packed(param, arg);
553
+
245
554
 	return 0;
246
555
 }
247
556
 
248
557
 static int max96789_pinctrl_config_set(struct serdes *serdes,
249
-				       unsigned int pin,
250
-				       unsigned long *configs,
558
+				       unsigned int pin, unsigned long *configs,
251
559
 				       unsigned int num_configs)
252
560
 {
253
-	return 0;
254
-}
561
+	enum pin_config_param param;
562
+	u32 arg;
563
+	u8 res_cfg;
564
+	int i;
255
565
 
256
-static int max96789_pinctrl_set_mux(struct serdes *serdes, unsigned int func_selector,
257
-				    unsigned int group_selector)
258
-{
566
+	for (i = 0; i < num_configs; i++) {
567
+		param = pinconf_to_config_param(configs[i]);
568
+		arg = pinconf_to_config_argument(configs[i]);
569
+
570
+		SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
571
+				serdes->chip_data->name, pin, param);
572
+
573
+		switch (param) {
574
+		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
575
+			serdes_set_bits(serdes, GPIO_B_REG(pin),
576
+					OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
577
+			break;
578
+		case PIN_CONFIG_DRIVE_PUSH_PULL:
579
+			serdes_set_bits(serdes, GPIO_B_REG(pin),
580
+					OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
581
+			break;
582
+		case PIN_CONFIG_BIAS_DISABLE:
583
+			serdes_set_bits(serdes, GPIO_C_REG(pin),
584
+					PULL_UPDN_SEL,
585
+					FIELD_PREP(PULL_UPDN_SEL, 0));
586
+			break;
587
+		case PIN_CONFIG_BIAS_PULL_UP:
588
+			switch (arg) {
589
+			case 40000:
590
+				res_cfg = 0;
591
+				break;
592
+			case 1000000:
593
+				res_cfg = 1;
594
+				break;
595
+			default:
596
+				return -EINVAL;
597
+			}
598
+
599
+			serdes_set_bits(serdes, GPIO_A_REG(pin),
600
+					RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
601
+			serdes_set_bits(serdes, GPIO_C_REG(pin),
602
+					PULL_UPDN_SEL,
603
+					FIELD_PREP(PULL_UPDN_SEL, 1));
604
+			break;
605
+		case PIN_CONFIG_BIAS_PULL_DOWN:
606
+			switch (arg) {
607
+			case 40000:
608
+				res_cfg = 0;
609
+				break;
610
+			case 1000000:
611
+				res_cfg = 1;
612
+				break;
613
+			default:
614
+				return -EINVAL;
615
+			}
616
+
617
+			serdes_set_bits(serdes, GPIO_A_REG(pin),
618
+					RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
619
+			serdes_set_bits(serdes, GPIO_C_REG(pin),
620
+					PULL_UPDN_SEL,
621
+					FIELD_PREP(PULL_UPDN_SEL, 2));
622
+			break;
623
+		case PIN_CONFIG_OUTPUT:
624
+			serdes_set_bits(serdes, GPIO_A_REG(pin),
625
+					GPIO_OUT_DIS | GPIO_OUT,
626
+					FIELD_PREP(GPIO_OUT_DIS, 0) |
627
+					FIELD_PREP(GPIO_OUT, arg));
628
+			break;
629
+		default:
630
+			return -EOPNOTSUPP;
631
+		}
632
+	}
633
+
259
634
 	return 0;
260
635
 }
261
636
 
..
..
@@ -304,6 +679,89 @@
304
679
 	.to_irq = max96789_gpio_to_irq,
305
680
 };
306
681
 
682
+static int max96789_select(struct serdes *serdes, int chan)
683
+{
684
+	u32 link_cfg, val;
685
+	int ret;
686
+
687
+	serdes_set_bits(serdes, 0x0001, DIS_REM_CC,
688
+			   FIELD_PREP(DIS_REM_CC, 0));
689
+
690
+	serdes_reg_read(serdes, 0x0010, &link_cfg);
691
+	if ((link_cfg & LINK_CFG) == SPLITTER_MODE)
692
+		SERDES_DBG_CHIP("%s: serdes chip %s already split mode cfg=0x%x\n", __func__,
693
+				serdes->chip_data->name, link_cfg);
694
+
695
+	if (chan == 0 && (link_cfg & LINK_CFG) != DUAL_LINK) {
696
+		serdes_set_bits(serdes, 0x0004,
697
+				   LINK_EN_B | LINK_EN_A,
698
+				   FIELD_PREP(LINK_EN_A, 1) |
699
+				   FIELD_PREP(LINK_EN_B, 1));
700
+		serdes_set_bits(serdes, 0x0010,
701
+				   RESET_ONESHOT | AUTO_LINK | LINK_CFG,
702
+				   FIELD_PREP(RESET_ONESHOT, 1) |
703
+				   FIELD_PREP(AUTO_LINK, 0) |
704
+				   FIELD_PREP(LINK_CFG, DUAL_LINK));
705
+		SERDES_DBG_CHIP("%s: change to use dual link\n", __func__);
706
+	} else if (chan == 1 && (link_cfg & LINK_CFG) != LINKA) {
707
+		serdes_set_bits(serdes, 0x0004,
708
+				   LINK_EN_B | LINK_EN_A,
709
+				   FIELD_PREP(LINK_EN_A, 1) |
710
+				   FIELD_PREP(LINK_EN_B, 0));
711
+		serdes_set_bits(serdes, 0x0010,
712
+				   RESET_ONESHOT | AUTO_LINK | LINK_CFG,
713
+				   FIELD_PREP(RESET_ONESHOT, 1) |
714
+				   FIELD_PREP(AUTO_LINK, 0) |
715
+				   FIELD_PREP(LINK_CFG, LINKA));
716
+		SERDES_DBG_CHIP("%s: change to use linkA\n", __func__);
717
+	} else if (chan == 2 && (link_cfg & LINK_CFG) != LINKB) {
718
+		serdes_set_bits(serdes, 0x0004,
719
+				   LINK_EN_B | LINK_EN_A,
720
+				   FIELD_PREP(LINK_EN_A, 0) |
721
+				   FIELD_PREP(LINK_EN_B, 1));
722
+		serdes_set_bits(serdes, 0x0010,
723
+				   RESET_ONESHOT | AUTO_LINK | LINK_CFG,
724
+				   FIELD_PREP(RESET_ONESHOT, 1) |
725
+				   FIELD_PREP(AUTO_LINK, 0) |
726
+				   FIELD_PREP(LINK_CFG, LINKB));
727
+		SERDES_DBG_CHIP("%s: change to use linkB\n", __func__);
728
+	} else if (chan == 3 && (link_cfg & LINK_CFG) != SPLITTER_MODE) {
729
+		serdes_set_bits(serdes, 0x0004,
730
+				   LINK_EN_B | LINK_EN_A,
731
+				   FIELD_PREP(LINK_EN_A, 1) |
732
+				   FIELD_PREP(LINK_EN_B, 1));
733
+		serdes_set_bits(serdes, 0x0010,
734
+				   RESET_ONESHOT | AUTO_LINK | LINK_CFG,
735
+				   FIELD_PREP(RESET_ONESHOT, 1) |
736
+				   FIELD_PREP(AUTO_LINK, 0) |
737
+				   FIELD_PREP(LINK_CFG, SPLITTER_MODE));
738
+		SERDES_DBG_CHIP("%s: change to use split mode\n", __func__);
739
+	}
740
+
741
+	ret = regmap_read_poll_timeout(serdes->regmap, 0x0013, val,
742
+				       val & LOCKED, 100,
743
+				       50 * USEC_PER_MSEC);
744
+	if (ret < 0) {
745
+		dev_err(serdes->dev, "GMSL2 link lock timeout\n");
746
+		return ret;
747
+	}
748
+
749
+	return 0;
750
+}
751
+
752
+static int max96789_deselect(struct serdes *serdes, int chan)
753
+{
754
+	//serdes_set_bits(serdes, 0x0001, DIS_REM_CC,
755
+	//		   FIELD_PREP(DIS_REM_CC, 1));
756
+
757
+	return 0;
758
+}
759
+
760
+static struct serdes_chip_split_ops max96789_split_ops = {
761
+	.select = max96789_select,
762
+	.deselect = max96789_deselect,
763
+};
764
+
307
765
 static int max96789_pm_suspend(struct serdes *serdes)
308
766
 {
309
767
 	return 0;
..
..
@@ -344,6 +802,7 @@
344
802
 	.bridge_ops	= &max96789_bridge_ops,
345
803
 	.pinctrl_ops	= &max96789_pinctrl_ops,
346
804
 	.gpio_ops	= &max96789_gpio_ops,
805
+	.split_ops	= &max96789_split_ops,
347
806
 	.pm_ops		= &max96789_pm_ops,
348
807
 	.irq_ops	= &max96789_irq_ops,
349
808
 };