~hc/RK356X_SDK_RELEASE.git

..	..	@@ -32,23 +32,34 @@
32	32	.rd_table = &max96772_readable_table,
33	33	};
34	34
35		-static int MAX96772_MFP0_pins[] = {0};
36		-static int MAX96772_MFP1_pins[] = {1};
37		-static int MAX96772_MFP2_pins[] = {2};
38		-static int MAX96772_MFP3_pins[] = {3};
39		-static int MAX96772_MFP4_pins[] = {4};
40		-static int MAX96772_MFP5_pins[] = {5};
41		-static int MAX96772_MFP6_pins[] = {6};
42		-static int MAX96772_MFP7_pins[] = {7};
	35	+struct config_desc {
	36	+ u16 reg;
	37	+ u8 mask;
	38	+ u8 val;
	39	+};
43	40
44		-static int MAX96772_MFP8_pins[] = {8};
45		-static int MAX96772_MFP9_pins[] = {9};
46		-static int MAX96772_MFP10_pins[] = {10};
47		-static int MAX96772_MFP11_pins[] = {11};
48		-static int MAX96772_MFP12_pins[] = {12};
49		-static int MAX96772_MFP13_pins[] = {13};
50		-static int MAX96772_MFP14_pins[] = {14};
51		-static int MAX96772_MFP15_pins[] = {15};
	41	+struct serdes_group_data {
	42	+ const struct config_desc *configs;
	43	+ int num_configs;
	44	+};
	45	+
	46	+static int MAX96772_GPIO0_pins[] = {0};
	47	+static int MAX96772_GPIO1_pins[] = {1};
	48	+static int MAX96772_GPIO2_pins[] = {2};
	49	+static int MAX96772_GPIO3_pins[] = {3};
	50	+static int MAX96772_GPIO4_pins[] = {4};
	51	+static int MAX96772_GPIO5_pins[] = {5};
	52	+static int MAX96772_GPIO6_pins[] = {6};
	53	+static int MAX96772_GPIO7_pins[] = {7};
	54	+
	55	+static int MAX96772_GPIO8_pins[] = {8};
	56	+static int MAX96772_GPIO9_pins[] = {9};
	57	+static int MAX96772_GPIO10_pins[] = {10};
	58	+static int MAX96772_GPIO11_pins[] = {11};
	59	+static int MAX96772_GPIO12_pins[] = {12};
	60	+static int MAX96772_GPIO13_pins[] = {13};
	61	+static int MAX96772_GPIO14_pins[] = {14};
	62	+static int MAX96772_GPIO15_pins[] = {15};
52	63
53	64	#define GROUP_DESC(nm) \
54	65	{ \
..	..	@@ -61,21 +72,24 @@
61	72	u8 gpio_out_dis:1;
62	73	u8 gpio_tx_en:1;
63	74	u8 gpio_rx_en:1;
	75	+ u8 gpio_in_level:1;
	76	+ u8 gpio_out_level:1;
64	77	u8 gpio_tx_id;
65	78	u8 gpio_rx_id;
	79	+ u16 mdelay;
66	80	};
67	81
68	82	static const char *serdes_gpio_groups[] = {
69		- "MAX96772_MFP0", "MAX96772_MFP1", "MAX96772_MFP2", "MAX96772_MFP3",
70		- "MAX96772_MFP4", "MAX96772_MFP5", "MAX96772_MFP6", "MAX96772_MFP7",
	83	+ "MAX96772_GPIO0", "MAX96772_GPIO1", "MAX96772_GPIO2", "MAX96772_GPIO3",
	84	+ "MAX96772_GPIO4", "MAX96772_GPIO5", "MAX96772_GPIO6", "MAX96772_GPIO7",
71	85
72		- "MAX96772_MFP8", "MAX96772_MFP9", "MAX96772_MFP10", "MAX96772_MFP11",
73		- "MAX96772_MFP12", "MAX96772_MFP13", "MAX96772_MFP14", "MAX96772_MFP15",
	86	+ "MAX96772_GPIO8", "MAX96772_GPIO9", "MAX96772_GPIO10", "MAX96772_GPIO11",
	87	+ "MAX96772_GPIO12", "MAX96772_GPIO13", "MAX96772_GPIO14", "MAX96772_GPIO15",
74	88	};
75	89
76		-#define FUNCTION_DESC_GPIO_INPUT(id) \
	90	+#define FUNCTION_DESC_GPIO_INPUT_BYPASS(id) \
77	91	{ \
78		- .name = "MFP"#id"_INPUT", \
	92	+ .name = "SER_TO_DES_RXID"#id, \
79	93	.group_names = serdes_gpio_groups, \
80	94	.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
81	95	.data = (void *)(const struct serdes_function_data []) { \
..	..	@@ -83,9 +97,9 @@
83	97	}, \
84	98	} \
85	99
86		-#define FUNCTION_DESC_GPIO_OUTPUT(id) \
	100	+#define FUNCTION_DESC_GPIO_OUTPUT_BYPASS(id) \
87	101	{ \
88		- .name = "MFP"#id"_OUTPUT", \
	102	+ .name = "DES_TXID"#id"_TO_SER", \
89	103	.group_names = serdes_gpio_groups, \
90	104	.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
91	105	.data = (void *)(const struct serdes_function_data []) { \
..	..	@@ -93,83 +107,156 @@
93	107	}, \
94	108	} \
95	109
96		-static struct pinctrl_pin_desc max96772_pins_desc[] = {
97		- PINCTRL_PIN(MAXIM_MAX96772_MFP0, "MAX96772_MFP0"),
98		- PINCTRL_PIN(MAXIM_MAX96772_MFP1, "MAX96772_MFP1"),
99		- PINCTRL_PIN(MAXIM_MAX96772_MFP2, "MAX96772_MFP2"),
100		- PINCTRL_PIN(MAXIM_MAX96772_MFP3, "MAX96772_MFP3"),
101		- PINCTRL_PIN(MAXIM_MAX96772_MFP4, "MAX96772_MFP4"),
102		- PINCTRL_PIN(MAXIM_MAX96772_MFP5, "MAX96772_MFP5"),
103		- PINCTRL_PIN(MAXIM_MAX96772_MFP6, "MAX96772_MFP6"),
104		- PINCTRL_PIN(MAXIM_MAX96772_MFP7, "MAX96772_MFP7"),
	110	+#define FUNCTION_DESC_GPIO_OUTPUT_LOW(id) \
	111	+{ \
	112	+ .name = "DES_TXID"#id"_OUTPUT_LOW", \
	113	+ .group_names = serdes_gpio_groups, \
	114	+ .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
	115	+ .data = (void *)(const struct serdes_function_data []) { \
	116	+ { .gpio_out_dis = 0, .gpio_tx_en = 0, \
	117	+ .gpio_rx_en = 0, .gpio_out_level = 0, .gpio_tx_id = id } \
	118	+ }, \
	119	+} \
105	120
106		- PINCTRL_PIN(MAXIM_MAX96772_MFP8, "MAX96772_MFP8"),
107		- PINCTRL_PIN(MAXIM_MAX96772_MFP9, "MAX96772_MFP9"),
108		- PINCTRL_PIN(MAXIM_MAX96772_MFP10, "MAX96772_MFP10"),
109		- PINCTRL_PIN(MAXIM_MAX96772_MFP11, "MAX96772_MFP11"),
110		- PINCTRL_PIN(MAXIM_MAX96772_MFP12, "MAX96772_MFP12"),
111		- PINCTRL_PIN(MAXIM_MAX96772_MFP13, "MAX96772_MFP13"),
112		- PINCTRL_PIN(MAXIM_MAX96772_MFP14, "MAX96772_MFP14"),
113		- PINCTRL_PIN(MAXIM_MAX96772_MFP15, "MAX96772_MFP15"),
	121	+#define FUNCTION_DESC_GPIO_OUTPUT_HIGH(id) \
	122	+{ \
	123	+ .name = "DES_TXID"#id"_OUTPUT_HIGH", \
	124	+ .group_names = serdes_gpio_groups, \
	125	+ .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
	126	+ .data = (void *)(const struct serdes_function_data []) { \
	127	+ { .gpio_out_dis = 0, .gpio_tx_en = 0, \
	128	+ .gpio_rx_en = 0, .gpio_out_level = 1, .gpio_tx_id = id } \
	129	+ }, \
	130	+} \
	131	+
	132	+#define FUNCTION_DES_DELAY_MS(ms) \
	133	+{ \
	134	+ .name = "DELAY_"#ms"MS", \
	135	+ .group_names = serdes_gpio_groups, \
	136	+ .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
	137	+ .data = (void *)(const struct serdes_function_data []) { \
	138	+ { .mdelay = ms, } \
	139	+ }, \
	140	+} \
	141	+
	142	+static struct pinctrl_pin_desc max96772_pins_desc[] = {
	143	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO0, "MAX96772_GPIO0"),
	144	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO1, "MAX96772_GPIO1"),
	145	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO2, "MAX96772_GPIO2"),
	146	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO3, "MAX96772_GPIO3"),
	147	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO4, "MAX96772_GPIO4"),
	148	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO5, "MAX96772_GPIO5"),
	149	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO6, "MAX96772_GPIO6"),
	150	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO7, "MAX96772_GPIO7"),
	151	+
	152	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO8, "MAX96772_GPIO8"),
	153	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO9, "MAX96772_GPIO9"),
	154	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO10, "MAX96772_GPIO10"),
	155	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO11, "MAX96772_GPIO11"),
	156	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO12, "MAX96772_GPIO12"),
	157	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO13, "MAX96772_GPIO13"),
	158	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO14, "MAX96772_GPIO14"),
	159	+ PINCTRL_PIN(MAXIM_MAX96772_GPIO15, "MAX96772_GPIO15"),
114	160	};
115	161
116	162	static struct group_desc max96772_groups_desc[] = {
117		- GROUP_DESC(MAX96772_MFP0),
118		- GROUP_DESC(MAX96772_MFP1),
119		- GROUP_DESC(MAX96772_MFP2),
120		- GROUP_DESC(MAX96772_MFP3),
121		- GROUP_DESC(MAX96772_MFP4),
122		- GROUP_DESC(MAX96772_MFP5),
123		- GROUP_DESC(MAX96772_MFP6),
124		- GROUP_DESC(MAX96772_MFP7),
	163	+ GROUP_DESC(MAX96772_GPIO0),
	164	+ GROUP_DESC(MAX96772_GPIO1),
	165	+ GROUP_DESC(MAX96772_GPIO2),
	166	+ GROUP_DESC(MAX96772_GPIO3),
	167	+ GROUP_DESC(MAX96772_GPIO4),
	168	+ GROUP_DESC(MAX96772_GPIO5),
	169	+ GROUP_DESC(MAX96772_GPIO6),
	170	+ GROUP_DESC(MAX96772_GPIO7),
125	171
126		- GROUP_DESC(MAX96772_MFP8),
127		- GROUP_DESC(MAX96772_MFP9),
128		- GROUP_DESC(MAX96772_MFP10),
129		- GROUP_DESC(MAX96772_MFP11),
130		- GROUP_DESC(MAX96772_MFP12),
131		- GROUP_DESC(MAX96772_MFP13),
132		- GROUP_DESC(MAX96772_MFP14),
133		- GROUP_DESC(MAX96772_MFP15),
	172	+ GROUP_DESC(MAX96772_GPIO8),
	173	+ GROUP_DESC(MAX96772_GPIO9),
	174	+ GROUP_DESC(MAX96772_GPIO10),
	175	+ GROUP_DESC(MAX96772_GPIO11),
	176	+ GROUP_DESC(MAX96772_GPIO12),
	177	+ GROUP_DESC(MAX96772_GPIO13),
	178	+ GROUP_DESC(MAX96772_GPIO14),
	179	+ GROUP_DESC(MAX96772_GPIO15),
134	180	};
135	181
136	182	static struct function_desc max96772_functions_desc[] = {
137		- FUNCTION_DESC_GPIO_INPUT(0),
138		- FUNCTION_DESC_GPIO_INPUT(1),
139		- FUNCTION_DESC_GPIO_INPUT(2),
140		- FUNCTION_DESC_GPIO_INPUT(3),
141		- FUNCTION_DESC_GPIO_INPUT(4),
142		- FUNCTION_DESC_GPIO_INPUT(5),
143		- FUNCTION_DESC_GPIO_INPUT(6),
144		- FUNCTION_DESC_GPIO_INPUT(7),
	183	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(0),
	184	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(1),
	185	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(2),
	186	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(3),
	187	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(4),
	188	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(5),
	189	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(6),
	190	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(7),
145	191
146		- FUNCTION_DESC_GPIO_INPUT(8),
147		- FUNCTION_DESC_GPIO_INPUT(9),
148		- FUNCTION_DESC_GPIO_INPUT(10),
149		- FUNCTION_DESC_GPIO_INPUT(11),
150		- FUNCTION_DESC_GPIO_INPUT(12),
151		- FUNCTION_DESC_GPIO_INPUT(13),
152		- FUNCTION_DESC_GPIO_INPUT(14),
153		- FUNCTION_DESC_GPIO_INPUT(15),
	192	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(8),
	193	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(9),
	194	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(10),
	195	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(11),
	196	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(12),
	197	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(13),
	198	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(14),
	199	+ FUNCTION_DESC_GPIO_INPUT_BYPASS(15),
154	200
155		- FUNCTION_DESC_GPIO_OUTPUT(0),
156		- FUNCTION_DESC_GPIO_OUTPUT(1),
157		- FUNCTION_DESC_GPIO_OUTPUT(2),
158		- FUNCTION_DESC_GPIO_OUTPUT(3),
159		- FUNCTION_DESC_GPIO_OUTPUT(4),
160		- FUNCTION_DESC_GPIO_OUTPUT(5),
161		- FUNCTION_DESC_GPIO_OUTPUT(6),
162		- FUNCTION_DESC_GPIO_OUTPUT(7),
	201	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(0),
	202	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(1),
	203	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(2),
	204	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(3),
	205	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(4),
	206	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(5),
	207	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(6),
	208	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(7),
163	209
164		- FUNCTION_DESC_GPIO_OUTPUT(8),
165		- FUNCTION_DESC_GPIO_OUTPUT(9),
166		- FUNCTION_DESC_GPIO_OUTPUT(10),
167		- FUNCTION_DESC_GPIO_OUTPUT(11),
168		- FUNCTION_DESC_GPIO_OUTPUT(12),
169		- FUNCTION_DESC_GPIO_OUTPUT(13),
170		- FUNCTION_DESC_GPIO_OUTPUT(14),
171		- FUNCTION_DESC_GPIO_OUTPUT(15),
	210	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(8),
	211	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(9),
	212	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(10),
	213	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(11),
	214	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(12),
	215	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(13),
	216	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(14),
	217	+ FUNCTION_DESC_GPIO_OUTPUT_BYPASS(15),
172	218
	219	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(0),
	220	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(1),
	221	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(2),
	222	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(3),
	223	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(4),
	224	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(5),
	225	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(6),
	226	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(7),
	227	+
	228	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(8),
	229	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(9),
	230	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(10),
	231	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(11),
	232	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(12),
	233	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(13),
	234	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(14),
	235	+ FUNCTION_DESC_GPIO_OUTPUT_LOW(15),
	236	+
	237	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(0),
	238	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(1),
	239	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(2),
	240	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(3),
	241	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(4),
	242	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(5),
	243	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(6),
	244	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(7),
	245	+
	246	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(8),
	247	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(9),
	248	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(10),
	249	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(11),
	250	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(12),
	251	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(13),
	252	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(14),
	253	+ FUNCTION_DESC_GPIO_OUTPUT_HIGH(15),
	254	+
	255	+ FUNCTION_DES_DELAY_MS(10),
	256	+ FUNCTION_DES_DELAY_MS(50),
	257	+ FUNCTION_DES_DELAY_MS(100),
	258	+ FUNCTION_DES_DELAY_MS(200),
	259	+ FUNCTION_DES_DELAY_MS(500),
173	260	};
174	261
175	262	static struct serdes_chip_pinctrl_info max96772_pinctrl_info = {
..	..	@@ -181,6 +268,69 @@
181	268	.num_functions = ARRAY_SIZE(max96772_functions_desc),
182	269	};
183	270
	271	+static const struct reg_sequence max96772_clk_ref[3][14] = {
	272	+ {
	273	+ { 0xe7b2, 0x50 },
	274	+ { 0xe7b3, 0x00 },
	275	+ { 0xe7b4, 0xcc },
	276	+ { 0xe7b5, 0x44 },
	277	+ { 0xe7b6, 0x81 },
	278	+ { 0xe7b7, 0x30 },
	279	+ { 0xe7b8, 0x07 },
	280	+ { 0xe7b9, 0x10 },
	281	+ { 0xe7ba, 0x01 },
	282	+ { 0xe7bb, 0x00 },
	283	+ { 0xe7bc, 0x00 },
	284	+ { 0xe7bd, 0x00 },
	285	+ { 0xe7be, 0x52 },
	286	+ { 0xe7bf, 0x00 },
	287	+ }, {
	288	+ { 0xe7b2, 0x50 },
	289	+ { 0xe7b3, 0x00 },
	290	+ { 0xe7b4, 0x00 },
	291	+ { 0xe7b5, 0x40 },
	292	+ { 0xe7b6, 0x6c },
	293	+ { 0xe7b7, 0x20 },
	294	+ { 0xe7b8, 0x07 },
	295	+ { 0xe7b9, 0x00 },
	296	+ { 0xe7ba, 0x01 },
	297	+ { 0xe7bb, 0x00 },
	298	+ { 0xe7bc, 0x00 },
	299	+ { 0xe7bd, 0x00 },
	300	+ { 0xe7be, 0x52 },
	301	+ { 0xe7bf, 0x00 },
	302	+ }, {
	303	+ { 0xe7b2, 0x30 },
	304	+ { 0xe7b3, 0x00 },
	305	+ { 0xe7b4, 0x00 },
	306	+ { 0xe7b5, 0x40 },
	307	+ { 0xe7b6, 0x6c },
	308	+ { 0xe7b7, 0x20 },
	309	+ { 0xe7b8, 0x14 },
	310	+ { 0xe7b9, 0x00 },
	311	+ { 0xe7ba, 0x2e },
	312	+ { 0xe7bb, 0x00 },
	313	+ { 0xe7bc, 0x00 },
	314	+ { 0xe7bd, 0x01 },
	315	+ { 0xe7be, 0x32 },
	316	+ { 0xe7bf, 0x00 },
	317	+ }
	318	+};
	319	+
	320	+static int max96772_aux_dpcd_read(struct serdes serdes, unsigned int reg, unsigned int value)
	321	+{
	322	+ serdes_reg_write(serdes, 0xe778, reg & 0xff);
	323	+ serdes_reg_write(serdes, 0xe779, (reg >> 8) & 0xff);
	324	+ serdes_reg_write(serdes, 0xe77c, (reg >> 16) & 0xff);
	325	+ serdes_reg_write(serdes, 0xe776, 0x10);
	326	+ serdes_reg_write(serdes, 0xe777, 0x80);
	327	+ /* FIXME */
	328	+ msleep(50);
	329	+ serdes_reg_read(serdes, 0xe77a, value);
	330	+
	331	+ return 0;
	332	+}
	333	+
184	334	static int max96772_panel_init(struct serdes *serdes)
185	335	{
186	336	return 0;
..	..	@@ -188,6 +338,86 @@
188	338
189	339	static int max96772_panel_prepare(struct serdes *serdes)
190	340	{
	341	+ const struct drm_display_mode *mode = &serdes->serdes_panel->mode;
	342	+ u32 hfp, hsa, hbp, hact;
	343	+ u32 vact, vsa, vfp, vbp;
	344	+ u64 hwords, mvid;
	345	+ bool hsync_pol, vsync_pol;
	346	+
	347	+ serdes_reg_write(serdes, 0xe790, serdes->serdes_panel->link_rate);
	348	+ serdes_reg_write(serdes, 0xe792, serdes->serdes_panel->lane_count);
	349	+
	350	+ if (serdes->serdes_panel->ssc) {
	351	+ serdes_reg_write(serdes, 0xe7b0, 0x01);
	352	+ serdes_reg_write(serdes, 0xe7b1, 0x10);
	353	+ } else {
	354	+ serdes_reg_write(serdes, 0xe7b1, 0x00);
	355	+ }
	356	+
	357	+ switch (serdes->serdes_panel->link_rate) {
	358	+ case DP_LINK_BW_5_4:
	359	+ serdes_multi_reg_write(serdes, max96772_clk_ref[2],
	360	+ ARRAY_SIZE(max96772_clk_ref[2]));
	361	+ break;
	362	+ case DP_LINK_BW_2_7:
	363	+ serdes_multi_reg_write(serdes, max96772_clk_ref[1],
	364	+ ARRAY_SIZE(max96772_clk_ref[1]));
	365	+ break;
	366	+ case DP_LINK_BW_1_62:
	367	+ default:
	368	+ serdes_multi_reg_write(serdes, max96772_clk_ref[0],
	369	+ ARRAY_SIZE(max96772_clk_ref[0]));
	370	+ break;
	371	+ }
	372	+
	373	+ vact = mode->vdisplay;
	374	+ vsa = mode->vsync_end - mode->vsync_start;
	375	+ vfp = mode->vsync_start - mode->vdisplay;
	376	+ vbp = mode->vtotal - mode->vsync_end;
	377	+ hact = mode->hdisplay;
	378	+ hsa = mode->hsync_end - mode->hsync_start;
	379	+ hfp = mode->hsync_start - mode->hdisplay;
	380	+ hbp = mode->htotal - mode->hsync_end;
	381	+
	382	+ serdes_reg_write(serdes, 0xe794, hact & 0xff);
	383	+ serdes_reg_write(serdes, 0xe795, (hact >> 8) & 0xff);
	384	+ serdes_reg_write(serdes, 0xe796, hfp & 0xff);
	385	+ serdes_reg_write(serdes, 0xe797, (hfp >> 8) & 0xff);
	386	+ serdes_reg_write(serdes, 0xe798, hsa & 0xff);
	387	+ serdes_reg_write(serdes, 0xe799, (hsa >> 8) & 0xff);
	388	+ serdes_reg_write(serdes, 0xe79a, hbp & 0xff);
	389	+ serdes_reg_write(serdes, 0xe79b, (hbp >> 8) & 0xff);
	390	+ serdes_reg_write(serdes, 0xe79c, vact & 0xff);
	391	+ serdes_reg_write(serdes, 0xe79d, (vact >> 8) & 0xff);
	392	+ serdes_reg_write(serdes, 0xe79e, vfp & 0xff);
	393	+ serdes_reg_write(serdes, 0xe79f, (vfp >> 8) & 0xff);
	394	+ serdes_reg_write(serdes, 0xe7a0, vsa & 0xff);
	395	+ serdes_reg_write(serdes, 0xe7a1, (vsa >> 8) & 0xff);
	396	+ serdes_reg_write(serdes, 0xe7a2, vbp & 0xff);
	397	+ serdes_reg_write(serdes, 0xe7a3, (vbp >> 8) & 0xff);
	398	+
	399	+ hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
	400	+ vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
	401	+ serdes_reg_write(serdes, 0xe7ac, hsync_pol \| (vsync_pol << 1));
	402	+
	403	+ /* NVID should always be set to 0x8000 */
	404	+ serdes_reg_write(serdes, 0xe7a8, 0);
	405	+ serdes_reg_write(serdes, 0xe7a9, 0x80);
	406	+
	407	+ /* HWORDS = ((HRES x bits / pixel) / 16) - LANE_COUNT */
	408	+ hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - serdes->serdes_panel->lane_count;
	409	+ serdes_reg_write(serdes, 0xe7a4, hwords);
	410	+ serdes_reg_write(serdes, 0xe7a5, hwords >> 8);
	411	+
	412	+ /* MVID = (PCLK x NVID) x 10 / Link Rate */
	413	+ mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768,
	414	+ drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate));
	415	+ serdes_reg_write(serdes, 0xe7a6, mvid & 0xff);
	416	+ serdes_reg_write(serdes, 0xe7a7, (mvid >> 8) & 0xff);
	417	+
	418	+ serdes_reg_write(serdes, 0xe7aa, 0x40);
	419	+ serdes_reg_write(serdes, 0xe7ab, 0x00);
	420	+
191	421	return 0;
192	422	}
193	423
..	..	@@ -198,6 +428,31 @@
198	428
199	429	static int max96772_panel_enable(struct serdes *serdes)
200	430	{
	431	+ u32 status[2];
	432	+ u32 val;
	433	+ int ret;
	434	+
	435	+ /* Run link training */
	436	+ serdes_reg_write(serdes, 0xe776, 0x02);
	437	+ serdes_reg_write(serdes, 0xe777, 0x80);
	438	+
	439	+ ret = regmap_read_poll_timeout(serdes->regmap, 0x07f0, val,
	440	+ val & 0x01, MSEC_PER_SEC,
	441	+ 500 * MSEC_PER_SEC);
	442	+ if (!ret)
	443	+ return 0;
	444	+
	445	+ ret = max96772_aux_dpcd_read(serdes, DP_LANE0_1_STATUS, &status[0]);
	446	+ if (ret)
	447	+ return ret;
	448	+
	449	+ ret = max96772_aux_dpcd_read(serdes, DP_LANE2_3_STATUS, &status[1]);
	450	+ if (ret)
	451	+ return ret;
	452	+
	453	+ dev_err(serdes->dev, "Link Training failed: LANE0_1_STATUS=0x%02x, LANE2_3_STATUS=0x%02x\n",
	454	+ status[0], status[1]);
	455	+
201	456	return 0;
202	457	}
203	458
..	..	@@ -214,24 +469,213 @@
214	469	.disable = max96772_panel_disable,
215	470	};
216	471
217		-static int max96772_pinctrl_config_get(struct serdes *serdes,
218		- unsigned int pin,
219		- unsigned long *config)
	472	+static int max96772_pinctrl_set_mux(struct serdes *serdes,
	473	+ unsigned int function, unsigned int group)
220	474	{
	475	+ struct serdes_pinctrl *pinctrl = serdes->pinctrl;
	476	+ struct function_desc *func;
	477	+ struct group_desc *grp;
	478	+ int i;
	479	+ u16 ms;
	480	+
	481	+ func = pinmux_generic_get_function(pinctrl->pctl, function);
	482	+ if (!func)
	483	+ return -EINVAL;
	484	+
	485	+ grp = pinctrl_generic_get_group(pinctrl->pctl, group);
	486	+ if (!grp)
	487	+ return -EINVAL;
	488	+
	489	+ SERDES_DBG_CHIP("%s: serdes chip %s func=%s data=%p group=%s data=%p, num_pin=%d\n",
	490	+ __func__, serdes->chip_data->name, func->name,
	491	+ func->data, grp->name, grp->data, grp->num_pins);
	492	+
	493	+ if (func->data) {
	494	+ struct serdes_function_data *fdata = func->data;
	495	+
	496	+ ms = fdata->mdelay;
	497	+ for (i = 0; i < grp->num_pins; i++) {
	498	+ if (!ms) {
	499	+ serdes_set_bits(serdes, GPIO_A_REG(grp->pins[i] - pinctrl->pin_base),
	500	+ GPIO_OUT_DIS \| GPIO_RX_EN \| GPIO_TX_EN \| GPIO_OUT,
	501	+ FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) \|
	502	+ FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) \|
	503	+ FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en) \|
	504	+ FIELD_PREP(GPIO_OUT, fdata->gpio_out_level));
	505	+ if (fdata->gpio_tx_en)
	506	+ serdes_set_bits(serdes,
	507	+ GPIO_B_REG(grp->pins[i] - pinctrl->pin_base),
	508	+ GPIO_TX_ID,
	509	+ FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
	510	+ if (fdata->gpio_rx_en)
	511	+ serdes_set_bits(serdes,
	512	+ GPIO_C_REG(grp->pins[i] - pinctrl->pin_base),
	513	+ GPIO_RX_ID,
	514	+ FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
	515	+ } else {
	516	+ mdelay(ms);
	517	+ SERDES_DBG_CHIP("%s: delay %d ms\n",
	518	+ __func__, ms);
	519	+ }
	520	+ }
	521	+ }
	522	+
	523	+ if (grp->data) {
	524	+ struct serdes_group_data *gdata = grp->data;
	525	+
	526	+ for (i = 0; i < gdata->num_configs; i++) {
	527	+ const struct config_desc *config = &gdata->configs[i];
	528	+
	529	+ serdes_set_bits(serdes, config->reg,
	530	+ config->mask, config->val);
	531	+ }
	532	+ }
	533	+
	534	+ return 0;
	535	+}
	536	+
	537	+static int max96772_pinctrl_config_get(struct serdes *serdes,
	538	+ unsigned int pin, unsigned long *config)
	539	+{
	540	+ enum pin_config_param param = pinconf_to_config_param(*config);
	541	+ unsigned int gpio_a_reg, gpio_b_reg;
	542	+ u16 arg = 0;
	543	+
	544	+ serdes_reg_read(serdes, GPIO_A_REG(pin), &gpio_a_reg);
	545	+ serdes_reg_read(serdes, GPIO_B_REG(pin), &gpio_b_reg);
	546	+
	547	+ SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
	548	+ serdes->chip_data->name, pin, param);
	549	+
	550	+ switch (param) {
	551	+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
	552	+ if (FIELD_GET(OUT_TYPE, gpio_b_reg))
	553	+ return -EINVAL;
	554	+ break;
	555	+ case PIN_CONFIG_DRIVE_PUSH_PULL:
	556	+ if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
	557	+ return -EINVAL;
	558	+ break;
	559	+ case PIN_CONFIG_BIAS_DISABLE:
	560	+ if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
	561	+ return -EINVAL;
	562	+ break;
	563	+ case PIN_CONFIG_BIAS_PULL_UP:
	564	+ if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
	565	+ return -EINVAL;
	566	+ switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
	567	+ case 0:
	568	+ arg = 40000;
	569	+ break;
	570	+ case 1:
	571	+ arg = 10000;
	572	+ break;
	573	+ }
	574	+ break;
	575	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	576	+ if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
	577	+ return -EINVAL;
	578	+ switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
	579	+ case 0:
	580	+ arg = 40000;
	581	+ break;
	582	+ case 1:
	583	+ arg = 10000;
	584	+ break;
	585	+ }
	586	+ break;
	587	+ case PIN_CONFIG_OUTPUT:
	588	+ if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
	589	+ return -EINVAL;
	590	+
	591	+ arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
	592	+ break;
	593	+ default:
	594	+ return -EOPNOTSUPP;
	595	+ }
	596	+
	597	+ *config = pinconf_to_config_packed(param, arg);
	598	+
221	599	return 0;
222	600	}
223	601
224	602	static int max96772_pinctrl_config_set(struct serdes *serdes,
225		- unsigned int pin,
226		- unsigned long *configs,
	603	+ unsigned int pin, unsigned long *configs,
227	604	unsigned int num_configs)
228	605	{
229		- return 0;
230		-}
	606	+ enum pin_config_param param;
	607	+ u32 arg;
	608	+ u8 res_cfg;
	609	+ int i;
231	610
232		-static int max96772_pinctrl_set_mux(struct serdes *serdes, unsigned int func_selector,
233		- unsigned int group_selector)
234		-{
	611	+ for (i = 0; i < num_configs; i++) {
	612	+ param = pinconf_to_config_param(configs[i]);
	613	+ arg = pinconf_to_config_argument(configs[i]);
	614	+
	615	+ SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
	616	+ serdes->chip_data->name, pin, param);
	617	+
	618	+ switch (param) {
	619	+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
	620	+ serdes_set_bits(serdes, GPIO_B_REG(pin),
	621	+ OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
	622	+ break;
	623	+ case PIN_CONFIG_DRIVE_PUSH_PULL:
	624	+ serdes_set_bits(serdes, GPIO_B_REG(pin),
	625	+ OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
	626	+ break;
	627	+ case PIN_CONFIG_BIAS_DISABLE:
	628	+ serdes_set_bits(serdes, GPIO_C_REG(pin),
	629	+ PULL_UPDN_SEL,
	630	+ FIELD_PREP(PULL_UPDN_SEL, 0));
	631	+ break;
	632	+ case PIN_CONFIG_BIAS_PULL_UP:
	633	+ switch (arg) {
	634	+ case 40000:
	635	+ res_cfg = 0;
	636	+ break;
	637	+ case 1000000:
	638	+ res_cfg = 1;
	639	+ break;
	640	+ default:
	641	+ return -EINVAL;
	642	+ }
	643	+
	644	+ serdes_set_bits(serdes, GPIO_A_REG(pin),
	645	+ RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
	646	+ serdes_set_bits(serdes, GPIO_C_REG(pin),
	647	+ PULL_UPDN_SEL,
	648	+ FIELD_PREP(PULL_UPDN_SEL, 1));
	649	+ break;
	650	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	651	+ switch (arg) {
	652	+ case 40000:
	653	+ res_cfg = 0;
	654	+ break;
	655	+ case 1000000:
	656	+ res_cfg = 1;
	657	+ break;
	658	+ default:
	659	+ return -EINVAL;
	660	+ }
	661	+
	662	+ serdes_set_bits(serdes, GPIO_A_REG(pin),
	663	+ RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
	664	+ serdes_set_bits(serdes, GPIO_C_REG(pin),
	665	+ PULL_UPDN_SEL,
	666	+ FIELD_PREP(PULL_UPDN_SEL, 2));
	667	+ break;
	668	+ case PIN_CONFIG_OUTPUT:
	669	+ serdes_set_bits(serdes, GPIO_A_REG(pin),
	670	+ GPIO_OUT_DIS \| GPIO_OUT,
	671	+ FIELD_PREP(GPIO_OUT_DIS, 0) \|
	672	+ FIELD_PREP(GPIO_OUT, arg));
	673	+ break;
	674	+ default:
	675	+ return -EOPNOTSUPP;
	676	+ }
	677	+ }
	678	+
235	679	return 0;
236	680	}
237	681