update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/platform/rockchip/ispp/hw.c
..
..
@@ -14,7 +14,7 @@
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 #include <linux/pinctrl/consumer.h>
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 #include <linux/pm_runtime.h>
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 #include <linux/reset.h>
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-#include <media/videobuf2-dma-contig.h>
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+#include <media/videobuf2-cma-sg.h>
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 #include <media/videobuf2-dma-sg.h>
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 #include <soc/rockchip/rockchip_iommu.h>
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20
 
..
..
@@ -43,6 +43,7 @@
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 {
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 	writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
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 	udelay(10);
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+	writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
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 	if (hw->reset) {
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 		reset_control_assert(hw->reset);
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 		udelay(20);
..
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@@ -55,43 +56,63 @@
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 		rockchip_iommu_disable(hw->dev);
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 		rockchip_iommu_enable(hw->dev);
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 	}
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-
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-	writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
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-	writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
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-	writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
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-	writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
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-	writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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-	writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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-	writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
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+	if (hw->ispp_ver == ISPP_V10) {
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+		writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
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+		writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
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+		writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
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+		writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
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+		writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+		writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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+		writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
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 		FBCH_EMPTY_TNR | FBCD_DEC_ERR_NR | FBCD_DEC_ERR_TNR |
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 		BUS_ERR_NR | BUS_ERR_TNR | SCL2_INT | SCL1_INT |
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 		SCL0_INT | FEC_INT | ORB_INT | SHP_INT | NR_INT | TNR_INT,
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 		hw->base_addr + RKISPP_CTRL_INT_MSK);
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-	writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+		writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+	} else if (hw->ispp_ver == ISPP_V20) {
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+		writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+		writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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+		writel(FEC_INT, hw->base_addr + RKISPP_CTRL_INT_MSK);
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+		writel(GATE_DIS_FEC, hw->base_addr + RKISPP_CTRL_CLKGATE);
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+	}
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+
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 }
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 /* using default value if reg no write for multi device */
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 static void default_sw_reg_flag(struct rkispp_device *dev)
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 {
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-	u32 reg[] = {
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-		RKISPP_TNR_CTRL,
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-		RKISPP_TNR_CORE_CTRL,
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-		RKISPP_NR_CTRL,
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-		RKISPP_NR_UVNR_CTRL_PARA,
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-		RKISPP_SHARP_CTRL,
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-		RKISPP_SHARP_CORE_CTRL,
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-		RKISPP_SCL0_CTRL,
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-		RKISPP_SCL1_CTRL,
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-		RKISPP_SCL2_CTRL,
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-		RKISPP_ORB_CORE_CTRL,
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-		RKISPP_FEC_CTRL,
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-		RKISPP_FEC_CORE_CTRL
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-	};
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-	u32 i, *flag;
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+	if (dev->hw_dev->ispp_ver == ISPP_V10) {
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+		u32 reg[] = {
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+			RKISPP_TNR_CTRL,
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+			RKISPP_TNR_CORE_CTRL,
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+			RKISPP_NR_CTRL,
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+			RKISPP_NR_UVNR_CTRL_PARA,
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+			RKISPP_SHARP_CTRL,
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+			RKISPP_SHARP_CORE_CTRL,
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+			RKISPP_SCL0_CTRL,
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+			RKISPP_SCL1_CTRL,
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+			RKISPP_SCL2_CTRL,
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+			RKISPP_ORB_CORE_CTRL,
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+			RKISPP_FEC_CTRL,
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+			RKISPP_FEC_CORE_CTRL
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+		};
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+		u32 i, *flag;
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-	for (i = 0; i < ARRAY_SIZE(reg); i++) {
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-		flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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-		*flag = 0xffffffff;
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+		for (i = 0; i < ARRAY_SIZE(reg); i++) {
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+			flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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+			*flag = 0xffffffff;
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+		}
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+	} else if (dev->hw_dev->ispp_ver == ISPP_V20) {
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+		u32 reg[] = {
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+			RKISPP_FEC_CTRL,
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+			RKISPP_FEC_CORE_CTRL
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+		};
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+		u32 i, *flag;
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+
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+		for (i = 0; i < ARRAY_SIZE(reg); i++) {
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+			flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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+			*flag = 0xffffffff;
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+		}
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 	}
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 }
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..
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@@ -124,14 +145,18 @@
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 static int enable_sys_clk(struct rkispp_hw_dev *dev)
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 {
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 	struct rkispp_device *ispp = dev->ispp[dev->cur_dev_id];
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-	u32 w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
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-	int i, ret = -EINVAL;
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+	int w, i, ret = -EINVAL;
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 	for (i = 0; i < dev->clks_num; i++) {
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 		ret = clk_prepare_enable(dev->clks[i]);
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 		if (ret < 0)
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 			goto err;
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 	}
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+
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+	if (!ispp)
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+		return ret;
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+
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+	w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
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 	for (i = 0; i < dev->clk_rate_tbl_num; i++)
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 		if (w <= dev->clk_rate_tbl[i].refer_data)
..
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@@ -181,6 +206,12 @@
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 	"hclk_ispp",
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 };
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+static const char * const rk3588_ispp_clks[] = {
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+	"clk_ispp",
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+	"aclk_ispp",
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+	"hclk_ispp",
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+};
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+
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 static const struct ispp_clk_info rv1126_ispp_clk_rate[] = {
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 	{
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 		.clk_rate = 150,
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@@ -200,8 +231,31 @@
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 	}
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 };
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+static const struct ispp_clk_info rk3588_ispp_clk_rate[] = {
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+	{
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+		.clk_rate = 300,
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+		.refer_data = 1920, //width
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+	}, {
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+		.clk_rate = 400,
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+		.refer_data = 2688,
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+	}, {
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+		.clk_rate = 500,
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+		.refer_data = 3072,
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+	}, {
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+		.clk_rate = 600,
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+		.refer_data = 3840,
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+	}, {
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+		.clk_rate = 702,
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+		.refer_data = 4672,
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+	}
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+};
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+
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 static struct irqs_data rv1126_ispp_irqs[] = {
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 	{"ispp_irq", irq_hdl},
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+	{"fec_irq", irq_hdl},
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+};
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+
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+static struct irqs_data rk3588_ispp_irqs[] = {
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 	{"fec_irq", irq_hdl},
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 };
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..
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@@ -215,10 +269,23 @@
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 	.ispp_ver = ISPP_V10,
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 };
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+static const struct ispp_match_data rk3588_ispp_match_data = {
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+	.clks = rk3588_ispp_clks,
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+	.clks_num = ARRAY_SIZE(rk3588_ispp_clks),
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+	.clk_rate_tbl = rk3588_ispp_clk_rate,
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+	.clk_rate_tbl_num = ARRAY_SIZE(rk3588_ispp_clk_rate),
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+	.irqs = rk3588_ispp_irqs,
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+	.num_irqs = ARRAY_SIZE(rk3588_ispp_irqs),
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+	.ispp_ver = ISPP_V20,
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+};
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+
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 static const struct of_device_id rkispp_hw_of_match[] = {
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 	{
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 		.compatible = "rockchip,rv1126-rkispp",
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 		.data = &rv1126_ispp_match_data,
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+	}, {
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+		.compatible = "rockchip,rk3588-rkispp",
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+		.data = &rk3588_ispp_match_data,
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 	},
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 	{},
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 };
..
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@@ -328,10 +395,13 @@
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 	atomic_set(&hw_dev->refcnt, 0);
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 	INIT_LIST_HEAD(&hw_dev->list);
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 	hw_dev->is_idle = true;
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-	hw_dev->is_single = false;
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+	hw_dev->is_single = true;
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+	/* for frame end reset and config reg */
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+	if (hw_dev->ispp_ver == ISPP_V10)
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+		hw_dev->is_single = false;
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 	hw_dev->is_fec_ext = false;
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 	hw_dev->is_dma_contig = true;
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-	hw_dev->is_dma_sg_ops = false;
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+	hw_dev->is_dma_sg_ops = true;
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 	hw_dev->is_shutdown = false;
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 	hw_dev->is_first = true;
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 	hw_dev->is_mmu = is_iommu_enable(dev);
..
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@@ -340,19 +410,10 @@
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 		is_mem_reserved = false;
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 		if (!hw_dev->is_mmu)
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 			dev_info(dev, "No reserved memory region. default cma area!\n");
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-		else
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-			hw_dev->is_dma_contig = false;
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 	}
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-	if (is_mem_reserved) {
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-		/* reserved memory using rdma_sg */
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-		hw_dev->mem_ops = &vb2_rdma_sg_memops;
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-		hw_dev->is_dma_sg_ops = true;
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-	} else if (hw_dev->is_mmu) {
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-		hw_dev->mem_ops = &vb2_dma_sg_memops;
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-		hw_dev->is_dma_sg_ops = true;
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-	} else {
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-		hw_dev->mem_ops = &vb2_dma_contig_memops;
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-	}
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+	if (hw_dev->is_mmu && !is_mem_reserved)
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+		hw_dev->is_dma_contig = false;
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+	hw_dev->mem_ops = &vb2_cma_sg_memops;
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417
 
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 	rkispp_register_fec(hw_dev);
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 	pm_runtime_enable(&pdev->dev);
..
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@@ -380,6 +441,7 @@
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 	if (pm_runtime_active(&pdev->dev)) {
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 		writel(0, hw_dev->base_addr + RKISPP_CTRL_INT_MSK);
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 		writel(GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
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+		writel(~GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
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 	}
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 	dev_info(&pdev->dev, "%s\n", __func__);
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 }
..
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@@ -414,8 +476,6 @@
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 }
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477
 
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 static const struct dev_pm_ops rkispp_hw_pm_ops = {
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-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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-				pm_runtime_force_resume)
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 	SET_RUNTIME_PM_OPS(rkispp_runtime_suspend,
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 			   rkispp_runtime_resume, NULL)
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 };