forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/media/platform/rockchip/isp/rkisp.c
....@@ -87,12 +87,6 @@
8787 
8888 static void rkisp_config_cmsk(struct rkisp_device *dev);
8989 
90
-struct backup_reg {
91
-	const u32 base;
92
-	const u32 shd;
93
-	u32 val;
94
-};
95
-
9690 static inline struct rkisp_device *sd_to_isp_dev(struct v4l2_subdev *sd)
9791 {
9892 	return container_of(sd->v4l2_dev, struct rkisp_device, v4l2_dev);
....@@ -730,7 +724,7 @@
730724 		params_vdev->rdbk_times = dma2frm + 1;
731725 
732726 run_next:
733
-	rkisp_params_cfgsram(params_vdev);
727
+	rkisp_params_cfgsram(params_vdev, true);
734728 	stats_vdev->rdbk_drop = false;
735729 	if (dev->is_frame_double) {
736730 		is_upd = true;
....@@ -753,6 +747,16 @@
753747 			writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
754748 			if (hw->unite == ISP_UNITE_TWO)
755749 				writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
750
+			val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
751
+			writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
752
+			if (hw->unite == ISP_UNITE_TWO)
753
+				writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
754
+			if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) {
755
+				val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
756
+				writel(val, hw->base_addr + ISP3X_CNR_CTRL);
757
+				if (hw->unite == ISP_UNITE_TWO)
758
+					writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
759
+			}
756760 		} else {
757761 			/* the frame first running to off mi to save bandwidth */
758762 			rkisp_multi_overflow_hdl(dev, false);
....@@ -869,6 +873,9 @@
869873 	struct rkisp_buffer *buf;
870874 	u32 i, val;
871875 
876
+	if (!dev->is_rtt_first)
877
+		return;
878
+
872879 	for (i = RKISP_STREAM_RAWRD0; i < RKISP_MAX_DMARX_STREAM; i++) {
873880 		stream = &dev->dmarx_dev.stream[i];
874881 		if (!stream->ops)
....@@ -933,11 +940,16 @@
933940 		goto end;
934941 	if (!IS_HDR_RDBK(dev->rd_mode))
935942 		goto end;
943
+	if (dev->is_suspend) {
944
+		if (dev->suspend_sync)
945
+			complete(&dev->pm_cmpl);
946
+		goto end;
947
+	}
936948 
937949 	for (i = 0; i < hw->dev_num; i++) {
938950 		isp = hw->isp[i];
939951 		if (!isp ||
940
-		    (isp && !(isp->isp_state & ISP_START)))
952
+		    (isp && (!(isp->isp_state & ISP_START) || isp->is_suspend)))
941953 			continue;
942954 		rkisp_rdbk_trigger_event(isp, T_CMD_LEN, &len[i]);
943955 		if (max < len[i]) {
....@@ -947,7 +959,7 @@
947959 	}
948960 
949961 	/* wait 2 frame to start isp for fast */
950
-	if (dev->is_pre_on && max == 1 && !atomic_read(&dev->isp_sdev.frm_sync_seq))
962
+	if (dev->is_rtt_first && max == 1 && !atomic_read(&dev->isp_sdev.frm_sync_seq))
951963 		goto end;
952964 
953965 	if (max) {
....@@ -993,7 +1005,7 @@
9931005 		/* first frame handle twice for thunderboot
9941006 		 * first output stats to AIQ and wait new params to run second
9951007 		 */
996
-		if (isp->is_pre_on && t.frame_id == 0) {
1008
+		if (isp->is_rtt_first && t.frame_id == 0) {
9971009 			isp->is_first_double = true;
9981010 			isp->skip_frame = 1;
9991011 			if (hw->unite != ISP_UNITE_ONE) {
....@@ -1001,6 +1013,8 @@
10011013 				isp->is_frame_double = false;
10021014 			}
10031015 			rkisp_fast_switch_rx_buf(isp, false);
1016
+		} else {
1017
+			isp->is_rtt_first = false;
10041018 		}
10051019 		isp->params_vdev.rdbk_times = isp->sw_rd_cnt + 1;
10061020 	}
....@@ -1079,6 +1093,7 @@
10791093 
10801094 	if (dev->is_first_double) {
10811095 		rkisp_fast_switch_rx_buf(dev, true);
1096
+		dev->is_rtt_first = false;
10821097 		dev->skip_frame = 0;
10831098 		dev->irq_ends = 0;
10841099 		return;
....@@ -1170,86 +1185,19 @@
11701185 	rkisp_write(dev, CIF_ISP_IS_CTRL, 1, false);
11711186 }
11721187 
1173
-static int rkisp_reset_handle_v2x(struct rkisp_device *dev)
1188
+static int rkisp_reset_handle(struct rkisp_device *dev)
11741189 {
1175
-	void __iomem *base = dev->base_addr;
1176
-	void *reg_buf = NULL;
1177
-	u32 *reg, *reg1, i;
1178
-	struct backup_reg backup[] = {
1179
-		{
1180
-			.base = MI_MP_WR_Y_BASE,
1181
-			.shd = MI_MP_WR_Y_BASE_SHD,
1182
-		}, {
1183
-			.base = MI_MP_WR_CB_BASE,
1184
-			.shd = MI_MP_WR_CB_BASE_SHD,
1185
-		}, {
1186
-			.base = MI_MP_WR_CR_BASE,
1187
-			.shd = MI_MP_WR_CR_BASE_SHD,
1188
-		}, {
1189
-			.base = MI_SP_WR_Y_BASE,
1190
-			.shd = MI_SP_WR_Y_BASE_SHD,
1191
-		}, {
1192
-			.base = MI_SP_WR_CB_BASE,
1193
-			.shd = MI_SP_WR_CB_BASE_AD_SHD,
1194
-		}, {
1195
-			.base = MI_SP_WR_CR_BASE,
1196
-			.shd = MI_SP_WR_CR_BASE_AD_SHD,
1197
-		}, {
1198
-			.base = MI_RAW0_WR_BASE,
1199
-			.shd = MI_RAW0_WR_BASE_SHD,
1200
-		}, {
1201
-			.base = MI_RAW1_WR_BASE,
1202
-			.shd = MI_RAW1_WR_BASE_SHD,
1203
-		}, {
1204
-			.base = MI_RAW2_WR_BASE,
1205
-			.shd = MI_RAW2_WR_BASE_SHD,
1206
-		}, {
1207
-			.base = MI_RAW3_WR_BASE,
1208
-			.shd = MI_RAW3_WR_BASE_SHD,
1209
-		}, {
1210
-			.base = MI_RAW0_RD_BASE,
1211
-			.shd = MI_RAW0_RD_BASE_SHD,
1212
-		}, {
1213
-			.base = MI_RAW1_RD_BASE,
1214
-			.shd = MI_RAW1_RD_BASE_SHD,
1215
-		}, {
1216
-			.base = MI_RAW2_RD_BASE,
1217
-			.shd = MI_RAW2_RD_BASE_SHD,
1218
-		}, {
1219
-			.base = MI_GAIN_WR_BASE,
1220
-			.shd = MI_GAIN_WR_BASE_SHD,
1221
-		}
1222
-	};
1223
-
1224
-	reg_buf = kzalloc(RKISP_ISP_SW_REG_SIZE, GFP_KERNEL);
1225
-	if (!reg_buf)
1226
-		return -ENOMEM;
1190
+	u32 val;
12271191 
12281192 	dev_info(dev->dev, "%s enter\n", __func__);
1193
+	rkisp_hw_reg_save(dev->hw_dev);
12291194 
1230
-	memcpy_fromio(reg_buf, base, RKISP_ISP_SW_REG_SIZE);
12311195 	rkisp_soft_reset(dev->hw_dev, true);
12321196 
1233
-	/* process special reg */
1234
-	reg = reg_buf + ISP_CTRL;
1235
-	*reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
1236
-		  CIF_ISP_CTRL_ISP_INFORM_ENABLE |
1237
-		  CIF_ISP_CTRL_ISP_CFG_UPD);
1238
-	reg = reg_buf + MI_WR_INIT;
1239
-	*reg = 0;
1240
-	reg = reg_buf + CSI2RX_CTRL0;
1241
-	*reg &= ~SW_CSI2RX_EN;
1242
-	/* skip mmu range */
1243
-	memcpy_toio(base, reg_buf, ISP21_MI_BAY3D_RD_BASE_SHD);
1244
-	memcpy_toio(base + CSI2RX_CTRL0, reg_buf + CSI2RX_CTRL0,
1245
-		    RKISP_ISP_SW_REG_SIZE - CSI2RX_CTRL0);
1246
-	/* config shd_reg to base_reg */
1247
-	for (i = 0; i < ARRAY_SIZE(backup); i++) {
1248
-		reg = reg_buf + backup[i].base;
1249
-		reg1 = reg_buf + backup[i].shd;
1250
-		backup[i].val = *reg;
1251
-		writel(*reg1, base + backup[i].base);
1252
-	}
1197
+	rkisp_hw_reg_restore(dev->hw_dev);
1198
+
1199
+	val = CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR;
1200
+	rkisp_unite_set_bits(dev, CIF_ISP_IMSC, 0, val, true);
12531201 
12541202 	/* clear state */
12551203 	dev->isp_err_cnt = 0;
....@@ -1257,40 +1205,12 @@
12571205 	rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
12581206 	dev->hw_dev->monitor.state = ISP_FRAME_END;
12591207 
1260
-	/* update module */
1261
-	reg = reg_buf + DUAL_CROP_CTRL;
1262
-	if (*reg & 0xf)
1263
-		writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
1264
-	reg = reg_buf + SELF_RESIZE_CTRL;
1265
-	if (*reg & 0xf)
1266
-		writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
1267
-	reg = reg_buf + MAIN_RESIZE_CTRL;
1268
-	if (*reg & 0xf)
1269
-		writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
1270
-
1271
-	/* update mi and isp, base_reg will update to shd_reg */
1272
-	force_cfg_update(dev);
1273
-	reg = reg_buf + ISP_CTRL;
1274
-	*reg |= CIF_ISP_CTRL_ISP_ENABLE |
1275
-		CIF_ISP_CTRL_ISP_INFORM_ENABLE |
1276
-		CIF_ISP_CTRL_ISP_CFG_UPD;
1277
-	writel(*reg, base + ISP_CTRL);
1278
-	udelay(50);
1279
-	/* config base_reg */
1280
-	for (i = 0; i < ARRAY_SIZE(backup); i++)
1281
-		writel(backup[i].val, base + backup[i].base);
1282
-	/* mpfbc base_reg = shd_reg, write is base but read is shd */
1283
-	if (dev->isp_ver == ISP_V20)
1284
-		writel(rkisp_read_reg_cache(dev, ISP_MPFBC_HEAD_PTR),
1285
-		       base + ISP_MPFBC_HEAD_PTR);
1286
-	rkisp_set_bits(dev, CIF_ISP_IMSC, 0, CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR, true);
12871208 	if (IS_HDR_RDBK(dev->hdr.op_mode)) {
12881209 		if (!dev->hw_dev->is_idle)
12891210 			rkisp_trigger_read_back(dev, 1, 0, true);
12901211 		else
12911212 			rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
12921213 	}
1293
-	kfree(reg_buf);
12941214 	dev_info(dev->dev, "%s exit\n", __func__);
12951215 	return 0;
12961216 }
....@@ -1304,11 +1224,6 @@
13041224 	struct rkisp_pipeline *p;
13051225 	int ret, i, j, timeout = 5, mipi_irq_cnt = 0;
13061226 
1307
-	if (!monitor->reset_handle) {
1308
-		monitor->is_en = false;
1309
-		return;
1310
-	}
1311
-
13121227 	dev_info(hw->dev, "%s enter\n", __func__);
13131228 	while (!(monitor->state & ISP_STOP) && monitor->is_en) {
13141229 		ret = wait_for_completion_timeout(&monitor->cmpl,
....@@ -1316,8 +1231,11 @@
13161231 		/* isp stop to exit
13171232 		 * isp err to reset
13181233 		 * mipi err wait isp idle, then reset
1234
+		 * online vicap if isp err, notify vicap reset, then vicap notify isp reset
1235
+		 * by ioctl RKISP_VICAP_CMD_SET_STREAM
13191236 		 */
13201237 		if (monitor->state & ISP_STOP ||
1238
+		    monitor->state & ISP_CIF_RESET ||
13211239 		    (ret && !(monitor->state & ISP_ERROR)) ||
13221240 		    (!ret &&
13231241 		     monitor->state & ISP_FRAME_END &&
....@@ -1366,10 +1284,22 @@
13661284 
13671285 		/* restart isp */
13681286 		isp = hw->isp[hw->cur_dev_id];
1369
-		ret = monitor->reset_handle(isp);
1370
-		if (ret) {
1371
-			monitor->is_en = false;
1372
-			break;
1287
+		if (!IS_HDR_RDBK(isp->hdr.op_mode) && isp->isp_ver >= ISP_V30) {
1288
+			struct v4l2_subdev *remote = NULL;
1289
+			struct v4l2_subdev *isp_subdev = NULL;
1290
+
1291
+			isp_subdev = &(isp->isp_sdev.sd);
1292
+			remote = get_remote_sensor(isp_subdev);
1293
+			v4l2_subdev_call(remote, core, ioctl,
1294
+				RKISP_VICAP_CMD_SET_RESET, NULL);
1295
+			monitor->state |= ISP_CIF_RESET;
1296
+			continue;
1297
+		} else {
1298
+			ret = rkisp_reset_handle(isp);
1299
+			if (ret) {
1300
+				monitor->is_en = false;
1301
+				break;
1302
+			}
13731303 		}
13741304 
13751305 		for (i = 0; i < hw->dev_num; i++) {
....@@ -1403,9 +1333,6 @@
14031333 	struct rkisp_monitor *monitor = &dev->hw_dev->monitor;
14041334 
14051335 	monitor->dev = dev->hw_dev;
1406
-	monitor->reset_handle = NULL;
1407
-	if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21)
1408
-		monitor->reset_handle = rkisp_reset_handle_v2x;
14091336 
14101337 	init_completion(&monitor->cmpl);
14111338 	INIT_WORK(&monitor->work, rkisp_restart_monitor);
....@@ -1570,6 +1497,7 @@
15701497 			left.win[0].win_en &= ~BIT(i);
15711498 			left.win[1].win_en &= ~BIT(i);
15721499 			left.win[2].win_en &= ~BIT(i);
1500
+			right.win[i].h_offs = h_offs - w + RKMOUDLE_UNITE_EXTEND_PIXEL;
15731501 		} else {
15741502 			/* cmsk window at dual isp */
15751503 			left.win[i].h_size = ALIGN(w - h_offs, 8);
....@@ -2927,6 +2855,7 @@
29272855 {
29282856 	struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
29292857 	struct rkisp_hw_dev *hw_dev = isp_dev->hw_dev;
2858
+	int ret;
29302859 
29312860 	if (!on) {
29322861 		if (IS_HDR_RDBK(isp_dev->rd_mode)) {
....@@ -2939,10 +2868,13 @@
29392868 					wake_up(&s->done);
29402869 			}
29412870 		}
2942
-		wait_event_timeout(isp_dev->sync_onoff,
2943
-				   isp_dev->isp_state & ISP_STOP ||
2944
-				   !IS_HDR_RDBK(isp_dev->rd_mode),
2945
-				   msecs_to_jiffies(50));
2871
+		ret = wait_event_timeout(isp_dev->sync_onoff,
2872
+					 isp_dev->isp_state & ISP_STOP ||
2873
+					 !IS_HDR_RDBK(isp_dev->rd_mode),
2874
+					 msecs_to_jiffies(500));
2875
+		if (!ret)
2876
+			v4l2_warn(&isp_dev->v4l2_dev, "%s wait timeout, mode:%d state:0x%x\n",
2877
+				  __func__, isp_dev->rd_mode, isp_dev->isp_state);
29462878 		rkisp_isp_stop(isp_dev);
29472879 		atomic_dec(&hw_dev->refcnt);
29482880 		rkisp_params_stream_stop(&isp_dev->params_vdev);
....@@ -3117,7 +3049,8 @@
31173049 
31183050 	pool->dbufs = dbufs;
31193051 	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
3120
-		 "%s type:0x%x dbufs[%d]:%p", __func__, dbufs->type, i, dbufs);
3052
+		 "%s type:0x%x first:%d dbufs[%d]:%p", __func__,
3053
+		 dbufs->type, dbufs->is_first, i, dbufs);
31213054 
31223055 	if (dbufs->is_resmem) {
31233056 		dma = dbufs->dma;
....@@ -3483,6 +3416,59 @@
34833416 	return 0;
34843417 }
34853418 
3419
+static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
3420
+					struct rkisp_vicap_mode *vicap_mode)
3421
+{
3422
+	struct rkisp_hw_dev *hw = isp_dev->hw_dev;
3423
+	int rd_mode = isp_dev->rd_mode;
3424
+
3425
+	isp_dev->is_suspend_one_frame = false;
3426
+	if (vicap_mode->rdbk_mode == RKISP_VICAP_ONLINE) {
3427
+		if (!hw->is_single)
3428
+			return -EINVAL;
3429
+		/* switch to online mode for single sensor */
3430
+		switch (rd_mode) {
3431
+		case HDR_RDBK_FRAME3:
3432
+			isp_dev->rd_mode = HDR_LINEX3_DDR;
3433
+			break;
3434
+		case HDR_RDBK_FRAME2:
3435
+			isp_dev->rd_mode = HDR_LINEX2_DDR;
3436
+			break;
3437
+		default:
3438
+			isp_dev->rd_mode = HDR_NORMAL;
3439
+		}
3440
+	} else if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO ||
3441
+		   vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME) {
3442
+		/* switch to readback mode */
3443
+		switch (rd_mode) {
3444
+		case HDR_LINEX3_DDR:
3445
+			isp_dev->rd_mode = HDR_RDBK_FRAME3;
3446
+			break;
3447
+		case HDR_LINEX2_DDR:
3448
+			isp_dev->rd_mode = HDR_RDBK_FRAME2;
3449
+			break;
3450
+		default:
3451
+			isp_dev->rd_mode = HDR_RDBK_FRAME1;
3452
+		}
3453
+		if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)
3454
+			isp_dev->is_suspend_one_frame = true;
3455
+	} else {
3456
+		return -EINVAL;
3457
+	}
3458
+	isp_dev->hdr.op_mode = isp_dev->rd_mode;
3459
+	if (rd_mode != isp_dev->rd_mode && hw->cur_dev_id == isp_dev->dev_id) {
3460
+		rkisp_unite_write(isp_dev, CSI2RX_CTRL0,
3461
+				  SW_IBUF_OP_MODE(isp_dev->rd_mode), true);
3462
+		if (IS_HDR_RDBK(isp_dev->rd_mode))
3463
+			rkisp_unite_set_bits(isp_dev, CTRL_SWS_CFG, 0,
3464
+					     SW_MPIP_DROP_FRM_DIS, true);
3465
+		else
3466
+			rkisp_unite_clear_bits(isp_dev, CTRL_SWS_CFG,
3467
+					       SW_MPIP_DROP_FRM_DIS, true);
3468
+	}
3469
+	return 0;
3470
+}
3471
+
34863472 static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
34873473 {
34883474 	struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
....@@ -3508,7 +3494,7 @@
35083494 		rkisp_get_info(isp_dev, arg);
35093495 		break;
35103496 	case RKISP_CMD_GET_TB_HEAD_V32:
3511
-		if (isp_dev->tb_head.complete != RKISP_TB_OK || !isp_dev->is_pre_on) {
3497
+		if (isp_dev->tb_head.complete != RKISP_TB_OK) {
35123498 			ret = -EINVAL;
35133499 			break;
35143500 		}
....@@ -3606,6 +3592,16 @@
36063592 			isp_dev->hw_dev->is_multi_overflow = false;
36073593 			rkisp_hw_enum_isp_size(isp_dev->hw_dev);
36083594 		}
3595
+		break;
3596
+	case RKISP_VICAP_CMD_SET_STREAM:
3597
+		ret = rkisp_reset_handle(isp_dev);
3598
+		if (!ret) {
3599
+			if (isp_dev->hw_dev->monitor.state & ISP_CIF_RESET)
3600
+				isp_dev->hw_dev->monitor.state &= ~ISP_CIF_RESET;
3601
+		}
3602
+		break;
3603
+	case RKISP_VICAP_CMD_MODE:
3604
+		ret = rkisp_set_work_mode_by_vicap(isp_dev, arg);
36093605 		break;
36103606 	default:
36113607 		ret = -ENOIOCTLCMD;
....@@ -3707,6 +3703,9 @@
37073703 		ret = rkisp_ioctl(sd, cmd, &module_id);
37083704 		break;
37093705 	case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
3706
+		ret = rkisp_ioctl(sd, cmd, NULL);
3707
+		break;
3708
+	case RKISP_VICAP_CMD_SET_STREAM:
37103709 		ret = rkisp_ioctl(sd, cmd, NULL);
37113710 		break;
37123711 	default:
....@@ -3828,6 +3827,7 @@
38283827 	atomic_set(&isp_sdev->frm_sync_seq, 0);
38293828 	rkisp_monitor_init(isp_dev);
38303829 	INIT_WORK(&isp_dev->rdbk_work, rkisp_rdbk_work);
3830
+	init_completion(&isp_dev->pm_cmpl);
38313831 	return 0;
38323832 err_cleanup_media_entity:
38333833 	media_entity_cleanup(&sd->entity);
....@@ -3867,8 +3867,7 @@
38673867 	(cond) ? 0 : -ETIMEDOUT; \
38683868 })
38693869 
3870
-#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
3871
-static void rkisp_save_tb_info(struct rkisp_device *isp_dev)
3870
+void rkisp_save_tb_info(struct rkisp_device *isp_dev)
38723871 {
38733872 	struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
38743873 	void *resmem_va = phys_to_virt(isp_dev->resmem_pa);
....@@ -3888,7 +3887,8 @@
38883887 	if (size && size < isp_dev->resmem_size) {
38893888 		dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
38903889 					size, DMA_FROM_DEVICE);
3891
-		params_vdev->is_first_cfg = true;
3890
+		if (isp_dev->is_rtt_first)
3891
+			params_vdev->is_first_cfg = true;
38923892 		if (isp_dev->isp_ver == ISP_V32) {
38933893 			struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
38943894 
....@@ -3900,7 +3900,7 @@
39003900 				  tmp->cfg.module_ens,
39013901 				  tmp->cfg.module_cfg_update);
39023902 		}
3903
-		if (param)
3903
+		if (param && (isp_dev->isp_state & ISP_STOP))
39043904 			params_vdev->ops->save_first_param(params_vdev, param);
39053905 	} else if (size > isp_dev->resmem_size) {
39063906 		v4l2_err(&isp_dev->v4l2_dev,
....@@ -3911,6 +3911,7 @@
39113911 	memcpy(&isp_dev->tb_head, head, sizeof(*head));
39123912 }
39133913 
3914
+#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
39143915 void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
39153916 {
39163917 	struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
....@@ -3958,11 +3959,10 @@
39583959 end:
39593960 	head = &isp_dev->tb_head;
39603961 	v4l2_info(&isp_dev->v4l2_dev,
3961
-		  "thunderboot info: %d, %d, %d, %d, %d, %d | %d %d\n",
3962
+		  "tb info en:%d comp:%d cnt:%d w:%d h:%d cam:%d idx:%d\n",
39623963 		  head->enable,
39633964 		  head->complete,
39643965 		  head->frm_total,
3965
-		  head->hdr_mode,
39663966 		  head->width,
39673967 		  head->height,
39683968 		  head->camera_num,
....@@ -4176,7 +4176,7 @@
41764176 		if (isp_mis & CIF_ISP_FRAME)
41774177 			sof_event_later = true;
41784178 		if (dev->vs_irq < 0 && !sof_event_later) {
4179
-			dev->isp_sdev.frm_timestamp = ktime_get_ns();
4179
+			dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
41804180 			rkisp_isp_queue_event_sof(&dev->isp_sdev);
41814181 			rkisp_stream_frame_start(dev, isp_mis);
41824182 		}
....@@ -4244,7 +4244,7 @@
42444244 	/* sampled input frame is complete */
42454245 	if (isp_mis & CIF_ISP_FRAME_IN) {
42464246 		dev->isp_sdev.dbg.interval =
4247
-			ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
4247
+			rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
42484248 		rkisp_set_state(&dev->isp_state, ISP_FRAME_IN);
42494249 		writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
42504250 		isp_mis_tmp = readl(base + CIF_ISP_MIS);
....@@ -4258,7 +4258,7 @@
42584258 		dev->rawaf_irq_cnt = 0;
42594259 		if (!dev->is_pre_on || !IS_HDR_RDBK(dev->rd_mode))
42604260 			dev->isp_sdev.dbg.interval =
4261
-				ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
4261
+				rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
42624262 		/* Clear Frame In (ISP) */
42634263 		rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
42644264 		writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
....@@ -4278,7 +4278,7 @@
42784278 			u64 tmp = dev->isp_sdev.dbg.interval +
42794279 					dev->isp_sdev.dbg.timestamp;
42804280 
4281
-			dev->isp_sdev.dbg.timestamp = ktime_get_ns();
4281
+			dev->isp_sdev.dbg.timestamp = rkisp_time_get_ns(dev);
42824282 			/* v-blank: frame(N)start - frame(N-1)end */
42834283 			dev->isp_sdev.dbg.delay = dev->isp_sdev.dbg.timestamp - tmp;
42844284 		}
....@@ -4330,7 +4330,7 @@
43304330 
43314331 	/* cur frame end and next frame start irq togeter */
43324332 	if (dev->vs_irq < 0 && sof_event_later) {
4333
-		dev->isp_sdev.frm_timestamp = ktime_get_ns();
4333
+		dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
43344334 		rkisp_isp_queue_event_sof(&dev->isp_sdev);
43354335 		rkisp_stream_frame_start(dev, isp_mis);
43364336 	}