~hc/RK356X_SDK_RELEASE.git

..	..	@@ -15,9 +15,337 @@
15	15
16	16	#define CIF_ISP_REQ_BUFS_MIN 0
17	17
18		-static int mi_frame_end(struct rkisp_stream *stream);
	18	+static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19	19	static void rkisp_buf_queue(struct vb2_buffer *vb);
20	20
	21	+static const struct capture_fmt mp_fmts[] = {
	22	+ /* yuv422 */
	23	+ {
	24	+ .fourcc = V4L2_PIX_FMT_UYVY,
	25	+ .fmt_type = FMT_YUV,
	26	+ .bpp = { 16 },
	27	+ .cplanes = 1,
	28	+ .mplanes = 1,
	29	+ .uv_swap = 0,
	30	+ .write_format = MI_CTRL_MP_WRITE_YUVINT,
	31	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	32	+ }, {
	33	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	34	+ .fmt_type = FMT_YUV,
	35	+ .bpp = { 8, 4, 4 },
	36	+ .cplanes = 3,
	37	+ .mplanes = 1,
	38	+ .uv_swap = 0,
	39	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	40	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	41	+ }, {
	42	+ .fourcc = V4L2_PIX_FMT_NV16,
	43	+ .fmt_type = FMT_YUV,
	44	+ .bpp = { 8, 16 },
	45	+ .cplanes = 2,
	46	+ .mplanes = 1,
	47	+ .uv_swap = 0,
	48	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	49	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	50	+ }, {
	51	+ .fourcc = V4L2_PIX_FMT_NV61,
	52	+ .fmt_type = FMT_YUV,
	53	+ .bpp = { 8, 16 },
	54	+ .cplanes = 2,
	55	+ .mplanes = 1,
	56	+ .uv_swap = 1,
	57	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	58	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	59	+ }, {
	60	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	61	+ .fmt_type = FMT_YUV,
	62	+ .bpp = { 8, 8, 8 },
	63	+ .cplanes = 3,
	64	+ .mplanes = 3,
	65	+ .uv_swap = 0,
	66	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	67	+ .output_format = ISP32_MI_OUTPUT_YUV422,
	68	+ },
	69	+ /* yuv420 */
	70	+ {
	71	+ .fourcc = V4L2_PIX_FMT_NV21,
	72	+ .fmt_type = FMT_YUV,
	73	+ .bpp = { 8, 16 },
	74	+ .cplanes = 2,
	75	+ .mplanes = 1,
	76	+ .uv_swap = 1,
	77	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	78	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	79	+ }, {
	80	+ .fourcc = V4L2_PIX_FMT_NV12,
	81	+ .fmt_type = FMT_YUV,
	82	+ .bpp = { 8, 16 },
	83	+ .cplanes = 2,
	84	+ .mplanes = 1,
	85	+ .uv_swap = 0,
	86	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	87	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	88	+ }, {
	89	+ .fourcc = V4L2_PIX_FMT_NV21M,
	90	+ .fmt_type = FMT_YUV,
	91	+ .bpp = { 8, 16 },
	92	+ .cplanes = 2,
	93	+ .mplanes = 2,
	94	+ .uv_swap = 1,
	95	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	96	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	97	+ }, {
	98	+ .fourcc = V4L2_PIX_FMT_NV12M,
	99	+ .fmt_type = FMT_YUV,
	100	+ .bpp = { 8, 16 },
	101	+ .cplanes = 2,
	102	+ .mplanes = 2,
	103	+ .uv_swap = 0,
	104	+ .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
	105	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	106	+ }, {
	107	+ .fourcc = V4L2_PIX_FMT_YUV420,
	108	+ .fmt_type = FMT_YUV,
	109	+ .bpp = { 8, 8, 8 },
	110	+ .cplanes = 3,
	111	+ .mplanes = 1,
	112	+ .uv_swap = 0,
	113	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	114	+ .output_format = ISP32_MI_OUTPUT_YUV420,
	115	+ },
	116	+ /* yuv444 */
	117	+ {
	118	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	119	+ .fmt_type = FMT_YUV,
	120	+ .bpp = { 8, 8, 8 },
	121	+ .cplanes = 3,
	122	+ .mplanes = 3,
	123	+ .uv_swap = 0,
	124	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	125	+ .output_format = 0,
	126	+ },
	127	+ /* raw */
	128	+ {
	129	+ .fourcc = V4L2_PIX_FMT_SRGGB8,
	130	+ .fmt_type = FMT_BAYER,
	131	+ .bpp = { 8 },
	132	+ .mplanes = 1,
	133	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	134	+ .output_format = 0,
	135	+ }, {
	136	+ .fourcc = V4L2_PIX_FMT_SGRBG8,
	137	+ .fmt_type = FMT_BAYER,
	138	+ .bpp = { 8 },
	139	+ .mplanes = 1,
	140	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	141	+ .output_format = 0,
	142	+ }, {
	143	+ .fourcc = V4L2_PIX_FMT_SGBRG8,
	144	+ .fmt_type = FMT_BAYER,
	145	+ .bpp = { 8 },
	146	+ .mplanes = 1,
	147	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	148	+ .output_format = 0,
	149	+ }, {
	150	+ .fourcc = V4L2_PIX_FMT_SBGGR8,
	151	+ .fmt_type = FMT_BAYER,
	152	+ .bpp = { 8 },
	153	+ .mplanes = 1,
	154	+ .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
	155	+ .output_format = 0,
	156	+ }, {
	157	+ .fourcc = V4L2_PIX_FMT_SRGGB10,
	158	+ .fmt_type = FMT_BAYER,
	159	+ .bpp = { 10 },
	160	+ .mplanes = 1,
	161	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	162	+ .output_format = 0,
	163	+ }, {
	164	+ .fourcc = V4L2_PIX_FMT_SGRBG10,
	165	+ .fmt_type = FMT_BAYER,
	166	+ .bpp = { 10 },
	167	+ .mplanes = 1,
	168	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	169	+ .output_format = 0,
	170	+ }, {
	171	+ .fourcc = V4L2_PIX_FMT_SGBRG10,
	172	+ .fmt_type = FMT_BAYER,
	173	+ .bpp = { 10 },
	174	+ .mplanes = 1,
	175	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	176	+ .output_format = 0,
	177	+ }, {
	178	+ .fourcc = V4L2_PIX_FMT_SBGGR10,
	179	+ .fmt_type = FMT_BAYER,
	180	+ .bpp = { 10 },
	181	+ .mplanes = 1,
	182	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	183	+ .output_format = 0,
	184	+ }, {
	185	+ .fourcc = V4L2_PIX_FMT_SRGGB12,
	186	+ .fmt_type = FMT_BAYER,
	187	+ .bpp = { 12 },
	188	+ .mplanes = 1,
	189	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	190	+ .output_format = 0,
	191	+ }, {
	192	+ .fourcc = V4L2_PIX_FMT_SGRBG12,
	193	+ .fmt_type = FMT_BAYER,
	194	+ .bpp = { 12 },
	195	+ .mplanes = 1,
	196	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	197	+ .output_format = 0,
	198	+ }, {
	199	+ .fourcc = V4L2_PIX_FMT_SGBRG12,
	200	+ .fmt_type = FMT_BAYER,
	201	+ .bpp = { 12 },
	202	+ .mplanes = 1,
	203	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	204	+ .output_format = 0,
	205	+ }, {
	206	+ .fourcc = V4L2_PIX_FMT_SBGGR12,
	207	+ .fmt_type = FMT_BAYER,
	208	+ .bpp = { 12 },
	209	+ .mplanes = 1,
	210	+ .write_format = MI_CTRL_MP_WRITE_RAW12,
	211	+ .output_format = 0,
	212	+ },
	213	+};
	214	+
	215	+static const struct capture_fmt sp_fmts[] = {
	216	+ /* yuv422 */
	217	+ {
	218	+ .fourcc = V4L2_PIX_FMT_UYVY,
	219	+ .fmt_type = FMT_YUV,
	220	+ .bpp = { 16 },
	221	+ .cplanes = 1,
	222	+ .mplanes = 1,
	223	+ .uv_swap = 0,
	224	+ .write_format = MI_CTRL_SP_WRITE_INT,
	225	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	226	+ }, {
	227	+ .fourcc = V4L2_PIX_FMT_YUV422P,
	228	+ .fmt_type = FMT_YUV,
	229	+ .bpp = { 8, 8, 8 },
	230	+ .cplanes = 3,
	231	+ .mplanes = 1,
	232	+ .uv_swap = 0,
	233	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	234	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	235	+ }, {
	236	+ .fourcc = V4L2_PIX_FMT_NV16,
	237	+ .fmt_type = FMT_YUV,
	238	+ .bpp = { 8, 16 },
	239	+ .cplanes = 2,
	240	+ .mplanes = 1,
	241	+ .uv_swap = 0,
	242	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	243	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	244	+ }, {
	245	+ .fourcc = V4L2_PIX_FMT_NV61,
	246	+ .fmt_type = FMT_YUV,
	247	+ .bpp = { 8, 16 },
	248	+ .cplanes = 2,
	249	+ .mplanes = 1,
	250	+ .uv_swap = 1,
	251	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	252	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	253	+ }, {
	254	+ .fourcc = V4L2_PIX_FMT_YUV422M,
	255	+ .fmt_type = FMT_YUV,
	256	+ .bpp = { 8, 8, 8 },
	257	+ .cplanes = 3,
	258	+ .mplanes = 3,
	259	+ .uv_swap = 0,
	260	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	261	+ .output_format = MI_CTRL_SP_OUTPUT_YUV422,
	262	+ },
	263	+ /* yuv420 */
	264	+ {
	265	+ .fourcc = V4L2_PIX_FMT_NV21,
	266	+ .fmt_type = FMT_YUV,
	267	+ .bpp = { 8, 16 },
	268	+ .cplanes = 2,
	269	+ .mplanes = 1,
	270	+ .uv_swap = 1,
	271	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	272	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	273	+ }, {
	274	+ .fourcc = V4L2_PIX_FMT_NV12,
	275	+ .fmt_type = FMT_YUV,
	276	+ .bpp = { 8, 16 },
	277	+ .cplanes = 2,
	278	+ .mplanes = 1,
	279	+ .uv_swap = 0,
	280	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	281	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	282	+ }, {
	283	+ .fourcc = V4L2_PIX_FMT_NV21M,
	284	+ .fmt_type = FMT_YUV,
	285	+ .bpp = { 8, 16 },
	286	+ .cplanes = 2,
	287	+ .mplanes = 2,
	288	+ .uv_swap = 1,
	289	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	290	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	291	+ }, {
	292	+ .fourcc = V4L2_PIX_FMT_NV12M,
	293	+ .fmt_type = FMT_YUV,
	294	+ .bpp = { 8, 16 },
	295	+ .cplanes = 2,
	296	+ .mplanes = 2,
	297	+ .uv_swap = 0,
	298	+ .write_format = MI_CTRL_SP_WRITE_SPLA,
	299	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	300	+ }, {
	301	+ .fourcc = V4L2_PIX_FMT_YUV420,
	302	+ .fmt_type = FMT_YUV,
	303	+ .bpp = { 8, 8, 8 },
	304	+ .cplanes = 3,
	305	+ .mplanes = 1,
	306	+ .uv_swap = 0,
	307	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	308	+ .output_format = MI_CTRL_SP_OUTPUT_YUV420,
	309	+ },
	310	+ /* yuv444 */
	311	+ {
	312	+ .fourcc = V4L2_PIX_FMT_YUV444M,
	313	+ .fmt_type = FMT_YUV,
	314	+ .bpp = { 8, 8, 8 },
	315	+ .cplanes = 3,
	316	+ .mplanes = 3,
	317	+ .uv_swap = 0,
	318	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	319	+ .output_format = MI_CTRL_SP_OUTPUT_YUV444,
	320	+ },
	321	+ /* yuv400 */
	322	+ {
	323	+ .fourcc = V4L2_PIX_FMT_GREY,
	324	+ .fmt_type = FMT_YUV,
	325	+ .bpp = { 8 },
	326	+ .cplanes = 1,
	327	+ .mplanes = 1,
	328	+ .uv_swap = 0,
	329	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	330	+ .output_format = MI_CTRL_SP_OUTPUT_YUV400,
	331	+ },
	332	+ /* rgb */
	333	+ {
	334	+ .fourcc = V4L2_PIX_FMT_XBGR32,
	335	+ .fmt_type = FMT_RGB,
	336	+ .bpp = { 32 },
	337	+ .mplanes = 1,
	338	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	339	+ .output_format = MI_CTRL_SP_OUTPUT_RGB888,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_RGB565,
	342	+ .fmt_type = FMT_RGB,
	343	+ .bpp = { 16 },
	344	+ .mplanes = 1,
	345	+ .write_format = MI_CTRL_SP_WRITE_PLA,
	346	+ .output_format = MI_CTRL_SP_OUTPUT_RGB565,
	347	+ },
	348	+};
21	349	static const struct capture_fmt dmatx_fmts[] = {
22	350	/* raw */
23	351	{
..	..	@@ -392,7 +720,7 @@
392	720	stream->out_isp_fmt.write_format, false);
393	721	mi_frame_end_int_enable(stream);
394	722	/* set up first buffer */
395		- mi_frame_end(stream);
	723	+ mi_frame_end(stream, FRAME_INIT);
396	724	return 0;
397	725	}
398	726
..	..	@@ -466,7 +794,7 @@
466	794	CIF_MI_SP_AUTOUPDATE_ENABLE, false);
467	795	mi_frame_end_int_enable(stream);
468	796	/* set up first buffer */
469		- mi_frame_end(stream);
	797	+ mi_frame_end(stream, FRAME_INIT);
470	798	return 0;
471	799	}
472	800
..	..	@@ -483,7 +811,7 @@
483	811
484	812	if (!dev->active_sensor \|\|
485	813	(dev->active_sensor &&
486		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	814	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
487	815	v4l2_err(&dev->v4l2_dev,
488	816	"only mipi sensor support rawwr3\n");
489	817	return -EINVAL;
..	..	@@ -495,7 +823,7 @@
495	823	stream->out_fmt.height);
496	824	raw_wr_set_pic_offs(stream, 0);
497	825	mi_set_y_size(stream, in_size);
498		- mi_frame_end(stream);
	826	+ mi_frame_end(stream, FRAME_INIT);
499	827	mi_frame_end_int_enable(stream);
500	828	mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD);
501	829	mi_raw_length(stream);
..	..	@@ -526,7 +854,7 @@
526	854
527	855	if (!dev->active_sensor \|\|
528	856	(dev->active_sensor &&
529		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	857	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
530	858	v4l2_err(&dev->v4l2_dev,
531	859	"only mipi sensor support rawwr2 path\n");
532	860	return -EINVAL;
..	..	@@ -541,7 +869,7 @@
541	869	stream->out_fmt.height);
542	870	raw_wr_set_pic_offs(stream, 0);
543	871	mi_set_y_size(stream, in_size);
544		- mi_frame_end(stream);
	872	+ mi_frame_end(stream, FRAME_INIT);
545	873	mi_frame_end_int_enable(stream);
546	874	mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD);
547	875	mi_raw_length(stream);
..	..	@@ -571,7 +899,7 @@
571	899
572	900	if (!dev->active_sensor \|\|
573	901	(dev->active_sensor &&
574		- dev->active_sensor->mbus.type != V4L2_MBUS_CSI2)) {
	902	+ dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
575	903	if (stream->id == RKISP_STREAM_DMATX0)
576	904	v4l2_err(&dev->v4l2_dev,
577	905	"only mipi sensor support rawwr0 path\n");
..	..	@@ -587,7 +915,7 @@
587	915	stream->out_fmt.height);
588	916	raw_wr_set_pic_offs(stream, 0);
589	917	mi_set_y_size(stream, in_size);
590		- mi_frame_end(stream);
	918	+ mi_frame_end(stream, FRAME_INIT);
591	919	mi_frame_end_int_enable(stream);
592	920	mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD);
593	921	mi_raw_length(stream);
..	..	@@ -618,8 +946,15 @@
618	946
619	947	static void sp_enable_mi(struct rkisp_stream *stream)
620	948	{
621		- rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, 0,
622		- CIF_MI_CTRL_SP_ENABLE, false);
	949	+ struct rkisp_device *dev = stream->ispdev;
	950	+ struct capture_fmt *fmt = &stream->out_isp_fmt;
	951	+ u32 val = CIF_MI_CTRL_SP_ENABLE;
	952	+ u32 mask = CIF_MI_SP_Y_FULL_YUV2RGB \| CIF_MI_SP_CBCR_FULL_YUV2RGB;
	953	+
	954	+ if (fmt->fmt_type == FMT_RGB &&
	955	+ dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
	956	+ val \|= mask;
	957	+ rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, mask, val, false);
623	958	}
624	959
625	960	static void dmatx_enable_mi(struct rkisp_stream *stream)
..	..	@@ -739,7 +1074,7 @@
739	1074	.enable_mi = mp_enable_mi,
740	1075	.disable_mi = mp_disable_mi,
741	1076	.stop_mi = mp_stop_mi,
742		- .set_data_path = mp_set_data_path,
	1077	+ .set_data_path = stream_data_path,
743	1078	.is_stream_stopped = mp_is_stream_stopped,
744	1079	.update_mi = update_mi,
745	1080	.frame_end = mi_frame_end,
..	..	@@ -750,7 +1085,7 @@
750	1085	.enable_mi = sp_enable_mi,
751	1086	.disable_mi = sp_disable_mi,
752	1087	.stop_mi = sp_stop_mi,
753		- .set_data_path = sp_set_data_path,
	1088	+ .set_data_path = stream_data_path,
754	1089	.is_stream_stopped = sp_is_stream_stopped,
755	1090	.update_mi = update_mi,
756	1091	.frame_end = mi_frame_end,
..	..	@@ -797,7 +1132,7 @@
797	1132	return;
798	1133
799	1134	if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME1) {
800		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1135	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
801	1136	cap->rdbk_buf[RDBK_S] = NULL;
802	1137	return;
803	1138	}
..	..	@@ -815,7 +1150,8 @@
815	1150	if (!ret) {
816	1151	denominator = sensor->fi.interval.denominator;
817	1152	numerator = sensor->fi.interval.numerator;
818		- time = numerator * 1000 / denominator * 1000 * 1000;
	1153	+ if (denominator)
	1154	+ time = numerator * 1000 / denominator * 1000 * 1000;
819	1155	if (numerator)
820	1156	fps = denominator / numerator;
821	1157	}
..	..	@@ -834,12 +1170,9 @@
834	1170	goto RDBK_FRM_UNMATCH;
835	1171	}
836	1172
837		- cap->rdbk_buf[RDBK_S]->vb.sequence =
838		- cap->rdbk_buf[RDBK_L]->vb.sequence;
839		- vb2_buffer_done(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf,
840		- VB2_BUF_STATE_DONE);
841		- vb2_buffer_done(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf,
842		- VB2_BUF_STATE_DONE);
	1173	+ cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
	1174	+ rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
	1175	+ rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
843	1176	} else {
844	1177	v4l2_err(&isp_dev->v4l2_dev, "lost long frames\n");
845	1178	goto RDBK_FRM_UNMATCH;
..	..	@@ -865,7 +1198,7 @@
865	1198	* is processing and we should set up buffer for next-next frame,
866	1199	* otherwise it will overflow.
867	1200	*/
868		-static int mi_frame_end(struct rkisp_stream *stream)
	1201	+static int mi_frame_end(struct rkisp_stream *stream, u32 state)
869	1202	{
870	1203	struct rkisp_device *dev = stream->ispdev;
871	1204	struct rkisp_capture_device *cap = &dev->cap_dev;
..	..	@@ -873,6 +1206,9 @@
873	1206	bool interlaced = stream->interlaced;
874	1207	unsigned long lock_flags = 0;
875	1208	int i = 0;
	1209	+
	1210	+ if (stream->id == RKISP_STREAM_VIR)
	1211	+ return 0;
876	1212
877	1213	if (!stream->next_buf && stream->streaming &&
878	1214	dev->dmarx_dev.trigger == T_MANUAL &&
..	..	@@ -886,8 +1222,18 @@
886	1222	(!interlaced \|\|
887	1223	(stream->u.sp.field_rec == RKISP_FIELD_ODD &&
888	1224	stream->u.sp.field == RKISP_FIELD_EVEN))) {
	1225	+ struct rkisp_stream *vir = &dev->cap_dev.stream[RKISP_STREAM_VIR];
889	1226	struct vb2_buffer *vb2_buf = &stream->curr_buf->vb.vb2_buf;
890	1227	u64 ns = 0;
	1228	+
	1229	+ if (stream->skip_frame) {
	1230	+ spin_lock_irqsave(&stream->vbq_lock, lock_flags);
	1231	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
	1232	+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
	1233	+ if (stream->skip_frame)
	1234	+ stream->skip_frame--;
	1235	+ goto end;
	1236	+ }
891	1237
892	1238	/* Dequeue a filled buffer */
893	1239	for (i = 0; i < isp_fmt->mplanes; i++) {
..	..	@@ -905,10 +1251,10 @@
905	1251	atomic_read(&stream->sequence) - 1;
906	1252	}
907	1253	if (!ns)
908		- ns = ktime_get_ns();
	1254	+ ns = rkisp_time_get_ns(dev);
909	1255	vb2_buf->timestamp = ns;
910	1256
911		- ns = ktime_get_ns();
	1257	+ ns = rkisp_time_get_ns(dev);
912	1258	stream->dbg.interval = ns - stream->dbg.timestamp;
913	1259	stream->dbg.timestamp = ns;
914	1260	stream->dbg.id = stream->curr_buf->vb.sequence;
..	..	@@ -936,12 +1282,22 @@
936	1282	rdbk_frame_end(stream);
937	1283	}
938	1284	} else {
939		- vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
	1285	+ if (vir->streaming && vir->conn_id == stream->id) {
	1286	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1287	+ list_add_tail(&stream->curr_buf->queue,
	1288	+ &dev->cap_dev.vir_cpy.queue);
	1289	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1290	+ if (!completion_done(&dev->cap_dev.vir_cpy.cmpl))
	1291	+ complete(&dev->cap_dev.vir_cpy.cmpl);
	1292	+ } else {
	1293	+ rkisp_stream_buf_done(stream, stream->curr_buf);
	1294	+ }
940	1295	}
941	1296
942	1297	stream->curr_buf = NULL;
943	1298	}
944	1299
	1300	+end:
945	1301	if (!interlaced \|\|
946	1302	(stream->curr_buf == stream->next_buf &&
947	1303	stream->u.sp.field == RKISP_FIELD_ODD)) {
..	..	@@ -993,7 +1349,9 @@
993	1349	{
994	1350	struct rkisp_device *dev = stream->ispdev;
995	1351	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
	1352	+ unsigned long lock_flags = 0;
996	1353	int ret = 0;
	1354	+ bool is_wait = dev->hw_dev->is_shutdown ? false : true;
997	1355
998	1356	if (!dev->dmarx_dev.trigger &&
999	1357	(is_rdbk_stream(stream) \|\| is_hdr_stream(stream))) {
..	..	@@ -1006,11 +1364,20 @@
1006	1364	stream->id != RKISP_STREAM_SP) \|\| dev->hw_dev->is_single)
1007	1365	stream->ops->stop_mi(stream);
1008	1366
1009		- if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP)
	1367	+ if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP) {
1010	1368	hdr_stop_dmatx(dev);
1011		-
1012		- if (dev->isp_state & ISP_START &&
1013		- !stream->ops->is_stream_stopped(dev->base_addr)) {
	1369	+ if (IS_HDR_RDBK(dev->rd_mode) && !dev->hw_dev->is_single) {
	1370	+ spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
	1371	+ if (dev->hw_dev->cur_dev_id != dev->dev_id \|\| dev->hw_dev->is_idle) {
	1372	+ is_wait = false;
	1373	+ stream->ops->disable_mi(stream);
	1374	+ }
	1375	+ if (atomic_read(&dev->cap_dev.refcnt) == 1 && !is_wait)
	1376	+ dev->isp_state = ISP_STOP;
	1377	+ spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
	1378	+ }
	1379	+ }
	1380	+ if (is_wait && !stream->ops->is_stream_stopped(stream)) {
1014	1381	ret = wait_event_timeout(stream->done,
1015	1382	!stream->streaming,
1016	1383	msecs_to_jiffies(500));
..	..	@@ -1036,6 +1403,98 @@
1036	1403	stream->interlaced = false;
1037	1404	}
1038	1405
	1406	+static void vir_cpy_image(struct work_struct *work)
	1407	+{
	1408	+ struct rkisp_vir_cpy *cpy =
	1409	+ container_of(work, struct rkisp_vir_cpy, work);
	1410	+ struct rkisp_stream *vir = cpy->stream;
	1411	+ struct rkisp_buffer *src_buf = NULL;
	1412	+ unsigned long lock_flags = 0;
	1413	+ u32 i;
	1414	+
	1415	+ v4l2_dbg(1, rkisp_debug, &vir->ispdev->v4l2_dev,
	1416	+ "%s enter\n", __func__);
	1417	+
	1418	+ vir->streaming = true;
	1419	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1420	+ if (!list_empty(&cpy->queue)) {
	1421	+ src_buf = list_first_entry(&cpy->queue,
	1422	+ struct rkisp_buffer, queue);
	1423	+ list_del(&src_buf->queue);
	1424	+ }
	1425	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1426	+
	1427	+ while (src_buf \|\| vir->streaming) {
	1428	+ if (vir->stopping \|\| !vir->streaming)
	1429	+ goto end;
	1430	+
	1431	+ if (!src_buf)
	1432	+ wait_for_completion(&cpy->cmpl);
	1433	+
	1434	+ vir->frame_end = false;
	1435	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1436	+
	1437	+ if (!src_buf && !list_empty(&cpy->queue)) {
	1438	+ src_buf = list_first_entry(&cpy->queue,
	1439	+ struct rkisp_buffer, queue);
	1440	+ list_del(&src_buf->queue);
	1441	+ }
	1442	+
	1443	+ if (src_buf && !vir->curr_buf && !list_empty(&vir->buf_queue)) {
	1444	+ vir->curr_buf = list_first_entry(&vir->buf_queue,
	1445	+ struct rkisp_buffer, queue);
	1446	+ list_del(&vir->curr_buf->queue);
	1447	+ }
	1448	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1449	+
	1450	+ if (!vir->curr_buf \|\| !src_buf)
	1451	+ goto end;
	1452	+
	1453	+ for (i = 0; i < vir->out_isp_fmt.mplanes; i++) {
	1454	+ u32 payload_size = vir->out_fmt.plane_fmt[i].sizeimage;
	1455	+ void *src = vb2_plane_vaddr(&src_buf->vb.vb2_buf, i);
	1456	+ void *dst = vb2_plane_vaddr(&vir->curr_buf->vb.vb2_buf, i);
	1457	+
	1458	+ if (!src \|\| !dst)
	1459	+ break;
	1460	+ vb2_set_plane_payload(&vir->curr_buf->vb.vb2_buf, i, payload_size);
	1461	+ memcpy(dst, src, payload_size);
	1462	+ }
	1463	+
	1464	+ vir->curr_buf->vb.sequence = src_buf->vb.sequence;
	1465	+ vir->curr_buf->vb.vb2_buf.timestamp = src_buf->vb.vb2_buf.timestamp;
	1466	+ vb2_buffer_done(&vir->curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1467	+ vir->curr_buf = NULL;
	1468	+end:
	1469	+ if (src_buf)
	1470	+ vb2_buffer_done(&src_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
	1471	+ src_buf = NULL;
	1472	+ spin_lock_irqsave(&vir->vbq_lock, lock_flags);
	1473	+
	1474	+ if (!list_empty(&cpy->queue)) {
	1475	+ src_buf = list_first_entry(&cpy->queue,
	1476	+ struct rkisp_buffer, queue);
	1477	+ list_del(&src_buf->queue);
	1478	+ } else if (vir->stopping) {
	1479	+ vir->streaming = false;
	1480	+ }
	1481	+
	1482	+ spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
	1483	+ }
	1484	+
	1485	+ vir->frame_end = true;
	1486	+
	1487	+ if (vir->stopping) {
	1488	+ vir->stopping = false;
	1489	+ vir->streaming = false;
	1490	+ wake_up(&vir->done);
	1491	+ }
	1492	+
	1493	+ v4l2_dbg(1, rkisp_debug, &vir->ispdev->v4l2_dev,
	1494	+ "%s exit\n", __func__);
	1495	+}
	1496	+
	1497	+
1039	1498	/*
1040	1499	* Most of registers inside rockchip isp1 have shadow register since
1041	1500	* they must be not changed during processing a frame.
..	..	@@ -1044,19 +1503,11 @@
1044	1503	*/
1045	1504	static int rkisp_start(struct rkisp_stream *stream)
1046	1505	{
1047		- void __iomem *base = stream->ispdev->base_addr;
1048	1506	struct rkisp_device *dev = stream->ispdev;
1049		- bool is_update = false;
1050	1507	int ret;
1051	1508
1052		- if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP) {
1053		- is_update = (stream->id == RKISP_STREAM_MP) ?
1054		- !dev->cap_dev.stream[RKISP_STREAM_SP].streaming :
1055		- !dev->cap_dev.stream[RKISP_STREAM_MP].streaming;
1056		- }
1057		-
1058	1509	if (stream->ops->set_data_path)
1059		- stream->ops->set_data_path(base);
	1510	+ stream->ops->set_data_path(stream);
1060	1511	ret = stream->ops->config_mi(stream);
1061	1512	if (ret)
1062	1513	return ret;
..	..	@@ -1064,11 +1515,8 @@
1064	1515	stream->ops->enable_mi(stream);
1065	1516	if (stream->id == RKISP_STREAM_MP \|\| stream->id == RKISP_STREAM_SP)
1066	1517	hdr_config_dmatx(dev);
1067		- if (is_update)
1068		- dev->irq_ends_mask \|=
1069		- (stream->id == RKISP_STREAM_MP) ? ISP_FRAME_MP : ISP_FRAME_SP;
1070	1518	stream->streaming = true;
1071		-
	1519	+ stream->skip_frame = 0;
1072	1520	return 0;
1073	1521	}
1074	1522
..	..	@@ -1214,6 +1662,12 @@
1214	1662	list_del(&buf->queue);
1215	1663	vb2_buffer_done(&buf->vb.vb2_buf, state);
1216	1664	}
	1665	+ while (!list_empty(&stream->buf_done_list)) {
	1666	+ buf = list_first_entry(&stream->buf_done_list,
	1667	+ struct rkisp_buffer, queue);
	1668	+ list_del(&buf->queue);
	1669	+ vb2_buffer_done(&buf->vb.vb2_buf, state);
	1670	+ }
1217	1671	spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1218	1672	}
1219	1673
..	..	@@ -1232,6 +1686,21 @@
1232	1686
1233	1687	if (!stream->streaming)
1234	1688	goto end;
	1689	+
	1690	+ if (stream->id == RKISP_STREAM_VIR) {
	1691	+ stream->stopping = true;
	1692	+ wait_event_timeout(stream->done,
	1693	+ stream->frame_end,
	1694	+ msecs_to_jiffies(500));
	1695	+ stream->streaming = false;
	1696	+ stream->stopping = false;
	1697	+ destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
	1698	+
	1699	+ if (!completion_done(&dev->cap_dev.vir_cpy.cmpl))
	1700	+ complete(&dev->cap_dev.vir_cpy.cmpl);
	1701	+ stream->conn_id = -1;
	1702	+ goto end;
	1703	+ }
1235	1704
1236	1705	rkisp_stream_stop(stream);
1237	1706	if (stream->id == RKISP_STREAM_MP \|\|
..	..	@@ -1252,7 +1721,7 @@
1252	1721	v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
1253	1722	rkisp_destroy_dummy_buf(stream);
1254	1723	atomic_dec(&dev->cap_dev.refcnt);
1255		-
	1724	+ tasklet_disable(&stream->buf_done_tasklet);
1256	1725	end:
1257	1726	mutex_unlock(&dev->hw_dev->dev_lock);
1258	1727	}
..	..	@@ -1312,6 +1781,28 @@
1312	1781	if (WARN_ON(stream->streaming)) {
1313	1782	mutex_unlock(&dev->hw_dev->dev_lock);
1314	1783	return -EBUSY;
	1784	+ }
	1785	+
	1786	+ if (stream->id == RKISP_STREAM_VIR) {
	1787	+ struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
	1788	+
	1789	+ if (t->streaming) {
	1790	+ INIT_WORK(&dev->cap_dev.vir_cpy.work, vir_cpy_image);
	1791	+ init_completion(&dev->cap_dev.vir_cpy.cmpl);
	1792	+ INIT_LIST_HEAD(&dev->cap_dev.vir_cpy.queue);
	1793	+ dev->cap_dev.vir_cpy.stream = stream;
	1794	+ schedule_work(&dev->cap_dev.vir_cpy.work);
	1795	+ ret = 0;
	1796	+ } else {
	1797	+ v4l2_err(&dev->v4l2_dev,
	1798	+ "no stream enable for iqtool\n");
	1799	+ destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
	1800	+ ret = -EINVAL;
	1801	+ }
	1802	+
	1803	+ mutex_unlock(&dev->hw_dev->dev_lock);
	1804	+
	1805	+ return ret;
1315	1806	}
1316	1807
1317	1808	memset(&stream->dbg, 0, sizeof(stream->dbg));
..	..	@@ -1378,7 +1869,7 @@
1378	1869	goto pipe_stream_off;
1379	1870	}
1380	1871	}
1381		-
	1872	+ tasklet_enable(&stream->buf_done_tasklet);
1382	1873	mutex_unlock(&dev->hw_dev->dev_lock);
1383	1874	return 0;
1384	1875
..	..	@@ -1445,38 +1936,49 @@
1445	1936	INIT_LIST_HEAD(&stream->buf_queue);
1446	1937	init_waitqueue_head(&stream->done);
1447	1938	spin_lock_init(&stream->vbq_lock);
1448		- stream->linked = MEDIA_LNK_FL_ENABLED;
	1939	+ stream->linked = true;
1449	1940
1450	1941	switch (id) {
1451	1942	case RKISP_STREAM_SP:
1452		- strlcpy(vdev->name, SP_VDEV_NAME,
	1943	+ strscpy(vdev->name, SP_VDEV_NAME,
1453	1944	sizeof(vdev->name));
1454	1945	stream->ops = &rkisp_sp_streams_ops;
1455	1946	stream->config = &rkisp_sp_stream_config;
	1947	+ stream->config->fmts = sp_fmts;
	1948	+ stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
1456	1949	break;
1457	1950	case RKISP_STREAM_DMATX0:
1458		- strlcpy(vdev->name, DMATX0_VDEV_NAME,
	1951	+ strscpy(vdev->name, DMATX0_VDEV_NAME,
1459	1952	sizeof(vdev->name));
1460	1953	stream->ops = &rkisp2_dmatx0_streams_ops;
1461	1954	stream->config = &rkisp2_dmatx0_stream_config;
1462	1955	break;
1463	1956	case RKISP_STREAM_DMATX2:
1464		- strlcpy(vdev->name, DMATX2_VDEV_NAME,
	1957	+ strscpy(vdev->name, DMATX2_VDEV_NAME,
1465	1958	sizeof(vdev->name));
1466	1959	stream->ops = &rkisp2_dmatx2_streams_ops;
1467	1960	stream->config = &rkisp2_dmatx1_stream_config;
1468	1961	break;
1469	1962	case RKISP_STREAM_DMATX3:
1470		- strlcpy(vdev->name, DMATX3_VDEV_NAME,
	1963	+ strscpy(vdev->name, DMATX3_VDEV_NAME,
1471	1964	sizeof(vdev->name));
1472	1965	stream->ops = &rkisp2_dmatx3_streams_ops;
1473	1966	stream->config = &rkisp2_dmatx3_stream_config;
1474	1967	break;
	1968	+ case RKISP_STREAM_VIR:
	1969	+ strscpy(vdev->name, VIR_VDEV_NAME,
	1970	+ sizeof(vdev->name));
	1971	+ stream->ops = NULL;
	1972	+ stream->config = &rkisp_mp_stream_config;
	1973	+ stream->conn_id = -1;
	1974	+ break;
1475	1975	default:
1476		- strlcpy(vdev->name, MP_VDEV_NAME,
	1976	+ strscpy(vdev->name, MP_VDEV_NAME,
1477	1977	sizeof(vdev->name));
1478	1978	stream->ops = &rkisp_mp_streams_ops;
1479	1979	stream->config = &rkisp_mp_stream_config;
	1980	+ stream->config->fmts = mp_fmts;
	1981	+ stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
1480	1982	}
1481	1983
1482	1984	node = vdev_to_node(vdev);
..	..	@@ -1515,8 +2017,13 @@
1515	2017	ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX3);
1516	2018	if (ret < 0)
1517	2019	goto err_free_tx2;
	2020	+ ret = rkisp_stream_init(dev, RKISP_STREAM_VIR);
	2021	+ if (ret < 0)
	2022	+ goto err_free_tx3;
1518	2023
1519	2024	return 0;
	2025	+err_free_tx3:
	2026	+ rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX3]);
1520	2027	err_free_tx2:
1521	2028	rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX2]);
1522	2029	err_free_tx0:
..	..	@@ -1544,6 +2051,8 @@
1544	2051	rkisp_unregister_stream_vdev(stream);
1545	2052	stream = &cap_dev->stream[RKISP_STREAM_DMATX3];
1546	2053	rkisp_unregister_stream_vdev(stream);
	2054	+ stream = &cap_dev->stream[RKISP_STREAM_VIR];
	2055	+ rkisp_unregister_stream_vdev(stream);
1547	2056	}
1548	2057
1549	2058	/************** Interrupter Handler **************/
..	..	@@ -1563,7 +2072,7 @@
1563	2072	for (i = 0; i < RKISP_MAX_STREAM; ++i) {
1564	2073	stream = &dev->cap_dev.stream[i];
1565	2074
1566		- if (!(mis_val & CIF_MI_FRAME(stream)))
	2075	+ if (!(mis_val & CIF_MI_FRAME(stream)) \|\| stream->id == RKISP_STREAM_VIR)
1567	2076	continue;
1568	2077
1569	2078	if (i == RKISP_STREAM_DMATX0)
..	..	@@ -1588,7 +2097,7 @@
1588	2097	stream->streaming = false;
1589	2098	stream->ops->disable_mi(stream);
1590	2099	wake_up(&stream->done);
1591		- } else if (stream->ops->is_stream_stopped(dev->base_addr)) {
	2100	+ } else if (stream->ops->is_stream_stopped(stream)) {
1592	2101	stream->stopping = false;
1593	2102	stream->streaming = false;
1594	2103	wake_up(&stream->done);
..	..	@@ -1598,7 +2107,7 @@
1598	2107	end_tx2 = false;
1599	2108	}
1600	2109	} else {
1601		- mi_frame_end(stream);
	2110	+ mi_frame_end(stream, FRAME_IRQ);
1602	2111	if (dev->dmarx_dev.trigger == T_AUTO &&
1603	2112	((dev->hdr.op_mode == HDR_RDBK_FRAME1 && end_tx2) \|\|
1604	2113	(dev->hdr.op_mode == HDR_RDBK_FRAME2 && end_tx2 && end_tx0))) {
..	..	@@ -1613,16 +2122,12 @@
1613	2122	stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
1614	2123	if (!stream->streaming)
1615	2124	dev->irq_ends_mask &= ~ISP_FRAME_MP;
1616		- else
1617		- dev->irq_ends_mask \|= ISP_FRAME_MP;
1618	2125	rkisp_check_idle(dev, ISP_FRAME_MP);
1619	2126	}
1620	2127	if (mis_val & CIF_MI_SP_FRAME) {
1621	2128	stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
1622	2129	if (!stream->streaming)
1623	2130	dev->irq_ends_mask &= ~ISP_FRAME_SP;
1624		- else
1625		- dev->irq_ends_mask \|= ISP_FRAME_SP;
1626	2131	rkisp_check_idle(dev, ISP_FRAME_SP);
1627	2132	}
1628	2133	}