update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/platform/rockchip/cif/hw.c
..
..
@@ -23,7 +23,6 @@
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 #include <media/videobuf2-dma-sg.h>
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 #include <media/v4l2-fwnode.h>
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 #include <linux/iommu.h>
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-#include <dt-bindings/soc/rockchip-system-status.h>
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 #include <soc/rockchip/rockchip-system-status.h>
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 #include <linux/io.h>
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 #include <linux/mfd/syscon.h>
..
..
@@ -699,6 +698,10 @@
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 	[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
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 	[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
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 	[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3),
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 	[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
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 	[CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
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@@ -823,6 +826,10 @@
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 	[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
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 	[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
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 	[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3),
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 	[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
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 	[CIF_REG_LVDS_ID0_CTRL0] = CIF_REG(CIF_LVDS0_ID0_CTRL0),
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 	[CIF_REG_LVDS_ID1_CTRL0] = CIF_REG(CIF_LVDS0_ID1_CTRL0),
..
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@@ -942,6 +949,10 @@
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 	[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
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 	[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
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 	[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2),
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+	[CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3),
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 	[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
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 	[CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
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@@ -1538,7 +1549,38 @@
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 	return 0;
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 }
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+static int __maybe_unused rkcif_sleep_suspend(struct device *dev)
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+{
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+	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
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+
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+	if (atomic_read(&cif_hw->power_cnt) == 0)
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+		return 0;
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+
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+	rkcif_disable_sys_clk(cif_hw);
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+
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+	return pinctrl_pm_select_sleep_state(dev);
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+}
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+
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+static int __maybe_unused rkcif_sleep_resume(struct device *dev)
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+{
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+	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
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+	int ret;
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+
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+	if (atomic_read(&cif_hw->power_cnt) == 0)
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+		return 0;
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+
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+	ret = pinctrl_pm_select_default_state(dev);
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+	if (ret < 0)
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+		return ret;
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+	rkcif_enable_sys_clk(cif_hw);
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+	rkcif_hw_soft_reset(cif_hw, true);
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+
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+	return 0;
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+}
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+
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 static const struct dev_pm_ops rkcif_plat_pm_ops = {
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+	SET_LATE_SYSTEM_SLEEP_PM_OPS(rkcif_sleep_suspend,
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+				rkcif_sleep_resume)
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 	SET_RUNTIME_PM_OPS(rkcif_runtime_suspend, rkcif_runtime_resume, NULL)
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 };
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