| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * SMI PCIe driver for DVBSky cards. |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2014 Max nibble <nibble.max@gmail.com> |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License as published by |
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| 8 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 9 | | - * (at your option) any later version. |
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| 10 | | - * |
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| 11 | | - * This program is distributed in the hope that it will be useful, |
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| 12 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 14 | | - * GNU General Public License for more details. |
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| 15 | 6 | */ |
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| 16 | 7 | |
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| 17 | 8 | #include "smipcie.h" |
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| 9 | + |
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| 10 | +#define SMI_SAMPLE_PERIOD 83 |
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| 11 | +#define SMI_SAMPLE_IDLEMIN (10000 / SMI_SAMPLE_PERIOD) |
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| 18 | 12 | |
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| 19 | 13 | static void smi_ir_enableInterrupt(struct smi_rc *ir) |
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| 20 | 14 | { |
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| .. | .. |
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| 42 | 36 | struct smi_dev *dev = ir->dev; |
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| 43 | 37 | |
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| 44 | 38 | smi_ir_disableInterrupt(ir); |
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| 45 | | - smi_clear(IR_Init_Reg, 0x80); |
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| 39 | + smi_clear(IR_Init_Reg, rbIRen); |
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| 46 | 40 | } |
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| 47 | 41 | |
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| 48 | | -#define BITS_PER_COMMAND 14 |
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| 49 | | -#define GROUPS_PER_BIT 2 |
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| 50 | | -#define IR_RC5_MIN_BIT 36 |
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| 51 | | -#define IR_RC5_MAX_BIT 52 |
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| 52 | | -static u32 smi_decode_rc5(u8 *pData, u8 size) |
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| 42 | +static void smi_raw_process(struct rc_dev *rc_dev, const u8 *buffer, |
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| 43 | + const u8 length) |
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| 53 | 44 | { |
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| 54 | | - u8 index, current_bit, bit_count; |
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| 55 | | - u8 group_array[BITS_PER_COMMAND * GROUPS_PER_BIT + 4]; |
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| 56 | | - u8 group_index = 0; |
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| 57 | | - u32 command = 0xFFFFFFFF; |
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| 45 | + struct ir_raw_event rawir = {}; |
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| 46 | + int cnt; |
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| 58 | 47 | |
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| 59 | | - group_array[group_index++] = 1; |
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| 60 | | - |
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| 61 | | - for (index = 0; index < size; index++) { |
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| 62 | | - |
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| 63 | | - current_bit = (pData[index] & 0x80) ? 1 : 0; |
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| 64 | | - bit_count = pData[index] & 0x7f; |
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| 65 | | - |
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| 66 | | - if ((current_bit == 1) && (bit_count >= 2*IR_RC5_MAX_BIT + 1)) { |
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| 67 | | - goto process_code; |
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| 68 | | - } else if ((bit_count >= IR_RC5_MIN_BIT) && |
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| 69 | | - (bit_count <= IR_RC5_MAX_BIT)) { |
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| 70 | | - group_array[group_index++] = current_bit; |
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| 71 | | - } else if ((bit_count > IR_RC5_MAX_BIT) && |
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| 72 | | - (bit_count <= 2*IR_RC5_MAX_BIT)) { |
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| 73 | | - group_array[group_index++] = current_bit; |
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| 74 | | - group_array[group_index++] = current_bit; |
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| 75 | | - } else { |
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| 76 | | - goto invalid_timing; |
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| 77 | | - } |
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| 78 | | - if (group_index >= BITS_PER_COMMAND*GROUPS_PER_BIT) |
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| 79 | | - goto process_code; |
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| 80 | | - |
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| 81 | | - if ((group_index == BITS_PER_COMMAND*GROUPS_PER_BIT - 1) |
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| 82 | | - && (group_array[group_index-1] == 0)) { |
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| 83 | | - group_array[group_index++] = 1; |
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| 84 | | - goto process_code; |
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| 48 | + for (cnt = 0; cnt < length; cnt++) { |
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| 49 | + if (buffer[cnt] & 0x7f) { |
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| 50 | + rawir.pulse = (buffer[cnt] & 0x80) == 0; |
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| 51 | + rawir.duration = ((buffer[cnt] & 0x7f) + |
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| 52 | + (rawir.pulse ? 0 : -1)) * |
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| 53 | + rc_dev->rx_resolution; |
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| 54 | + ir_raw_event_store_with_filter(rc_dev, &rawir); |
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| 85 | 55 | } |
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| 86 | 56 | } |
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| 87 | | - |
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| 88 | | -process_code: |
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| 89 | | - if (group_index == (BITS_PER_COMMAND*GROUPS_PER_BIT-1)) |
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| 90 | | - group_array[group_index++] = 1; |
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| 91 | | - |
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| 92 | | - if (group_index == BITS_PER_COMMAND*GROUPS_PER_BIT) { |
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| 93 | | - command = 0; |
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| 94 | | - for (index = 0; index < (BITS_PER_COMMAND*GROUPS_PER_BIT); |
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| 95 | | - index = index + 2) { |
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| 96 | | - if ((group_array[index] == 1) && |
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| 97 | | - (group_array[index+1] == 0)) { |
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| 98 | | - command |= (1 << (BITS_PER_COMMAND - |
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| 99 | | - (index/2) - 1)); |
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| 100 | | - } else if ((group_array[index] == 0) && |
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| 101 | | - (group_array[index+1] == 1)) { |
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| 102 | | - /* */ |
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| 103 | | - } else { |
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| 104 | | - command = 0xFFFFFFFF; |
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| 105 | | - goto invalid_timing; |
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| 106 | | - } |
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| 107 | | - } |
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| 108 | | - } |
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| 109 | | - |
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| 110 | | -invalid_timing: |
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| 111 | | - return command; |
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| 112 | 57 | } |
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| 113 | 58 | |
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| 114 | | -static void smi_ir_decode(struct work_struct *work) |
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| 59 | +static void smi_ir_decode(struct smi_rc *ir) |
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| 115 | 60 | { |
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| 116 | | - struct smi_rc *ir = container_of(work, struct smi_rc, work); |
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| 117 | 61 | struct smi_dev *dev = ir->dev; |
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| 118 | 62 | struct rc_dev *rc_dev = ir->rc_dev; |
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| 119 | | - u32 dwIRControl, dwIRData, dwIRCode, scancode; |
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| 120 | | - u8 index, ucIRCount, readLoop, rc5_command, rc5_system, toggle; |
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| 63 | + u32 control, data; |
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| 64 | + u8 index, ir_count, read_loop; |
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| 121 | 65 | |
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| 122 | | - dwIRControl = smi_read(IR_Init_Reg); |
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| 123 | | - if (dwIRControl & rbIRVld) { |
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| 124 | | - ucIRCount = (u8) smi_read(IR_Data_Cnt); |
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| 66 | + control = smi_read(IR_Init_Reg); |
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| 125 | 67 | |
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| 126 | | - if (ucIRCount < 4) |
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| 127 | | - goto end_ir_decode; |
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| 68 | + dev_dbg(&rc_dev->dev, "ircontrol: 0x%08x\n", control); |
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| 128 | 69 | |
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| 129 | | - readLoop = ucIRCount/4; |
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| 130 | | - if (ucIRCount % 4) |
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| 131 | | - readLoop += 1; |
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| 132 | | - for (index = 0; index < readLoop; index++) { |
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| 133 | | - dwIRData = smi_read(IR_DATA_BUFFER_BASE + (index*4)); |
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| 70 | + if (control & rbIRVld) { |
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| 71 | + ir_count = (u8)smi_read(IR_Data_Cnt); |
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| 134 | 72 | |
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| 135 | | - ir->irData[index*4 + 0] = (u8)(dwIRData); |
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| 136 | | - ir->irData[index*4 + 1] = (u8)(dwIRData >> 8); |
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| 137 | | - ir->irData[index*4 + 2] = (u8)(dwIRData >> 16); |
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| 138 | | - ir->irData[index*4 + 3] = (u8)(dwIRData >> 24); |
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| 73 | + dev_dbg(&rc_dev->dev, "ircount %d\n", ir_count); |
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| 74 | + |
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| 75 | + read_loop = ir_count / 4; |
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| 76 | + if (ir_count % 4) |
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| 77 | + read_loop += 1; |
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| 78 | + for (index = 0; index < read_loop; index++) { |
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| 79 | + data = smi_read(IR_DATA_BUFFER_BASE + (index * 4)); |
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| 80 | + dev_dbg(&rc_dev->dev, "IRData 0x%08x\n", data); |
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| 81 | + |
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| 82 | + ir->irData[index * 4 + 0] = (u8)(data); |
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| 83 | + ir->irData[index * 4 + 1] = (u8)(data >> 8); |
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| 84 | + ir->irData[index * 4 + 2] = (u8)(data >> 16); |
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| 85 | + ir->irData[index * 4 + 3] = (u8)(data >> 24); |
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| 139 | 86 | } |
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| 140 | | - dwIRCode = smi_decode_rc5(ir->irData, ucIRCount); |
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| 141 | | - |
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| 142 | | - if (dwIRCode != 0xFFFFFFFF) { |
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| 143 | | - rc5_command = dwIRCode & 0x3F; |
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| 144 | | - rc5_system = (dwIRCode & 0x7C0) >> 6; |
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| 145 | | - toggle = (dwIRCode & 0x800) ? 1 : 0; |
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| 146 | | - scancode = rc5_system << 8 | rc5_command; |
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| 147 | | - rc_keydown(rc_dev, RC_PROTO_RC5, scancode, toggle); |
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| 148 | | - } |
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| 87 | + smi_raw_process(rc_dev, ir->irData, ir_count); |
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| 149 | 88 | } |
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| 150 | | -end_ir_decode: |
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| 151 | | - smi_set(IR_Init_Reg, 0x04); |
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| 152 | | - smi_ir_enableInterrupt(ir); |
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| 89 | + |
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| 90 | + if (control & rbIRhighidle) { |
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| 91 | + struct ir_raw_event rawir = {}; |
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| 92 | + |
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| 93 | + dev_dbg(&rc_dev->dev, "high idle\n"); |
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| 94 | + |
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| 95 | + rawir.pulse = 0; |
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| 96 | + rawir.duration = SMI_SAMPLE_PERIOD * SMI_SAMPLE_IDLEMIN; |
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| 97 | + ir_raw_event_store_with_filter(rc_dev, &rawir); |
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| 98 | + } |
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| 99 | + |
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| 100 | + smi_set(IR_Init_Reg, rbIRVld); |
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| 101 | + ir_raw_event_handle(rc_dev); |
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| 153 | 102 | } |
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| 154 | 103 | |
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| 155 | 104 | /* ir functions call by main driver.*/ |
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| .. | .. |
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| 160 | 109 | if (int_status & IR_X_INT) { |
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| 161 | 110 | smi_ir_disableInterrupt(ir); |
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| 162 | 111 | smi_ir_clearInterrupt(ir); |
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| 163 | | - schedule_work(&ir->work); |
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| 112 | + smi_ir_decode(ir); |
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| 113 | + smi_ir_enableInterrupt(ir); |
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| 164 | 114 | handled = 1; |
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| 165 | 115 | } |
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| 166 | 116 | return handled; |
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| .. | .. |
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| 170 | 120 | { |
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| 171 | 121 | struct smi_dev *dev = ir->dev; |
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| 172 | 122 | |
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| 173 | | - smi_write(IR_Idle_Cnt_Low, 0x00140070); |
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| 123 | + smi_write(IR_Idle_Cnt_Low, |
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| 124 | + (((SMI_SAMPLE_PERIOD - 1) & 0xFFFF) << 16) | |
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| 125 | + (SMI_SAMPLE_IDLEMIN & 0xFFFF)); |
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| 174 | 126 | msleep(20); |
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| 175 | | - smi_set(IR_Init_Reg, 0x90); |
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| 127 | + smi_set(IR_Init_Reg, rbIRen | rbIRhighidle); |
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| 176 | 128 | |
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| 177 | 129 | smi_ir_enableInterrupt(ir); |
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| 178 | 130 | } |
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| .. | .. |
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| 183 | 135 | struct rc_dev *rc_dev; |
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| 184 | 136 | struct smi_rc *ir = &dev->ir; |
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| 185 | 137 | |
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| 186 | | - rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); |
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| 138 | + rc_dev = rc_allocate_device(RC_DRIVER_IR_RAW); |
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| 187 | 139 | if (!rc_dev) |
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| 188 | 140 | return -ENOMEM; |
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| 189 | 141 | |
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| .. | .. |
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| 193 | 145 | snprintf(ir->input_phys, sizeof(ir->input_phys), "pci-%s/ir0", |
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| 194 | 146 | pci_name(dev->pci_dev)); |
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| 195 | 147 | |
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| 148 | + rc_dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
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| 196 | 149 | rc_dev->driver_name = "SMI_PCIe"; |
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| 197 | 150 | rc_dev->input_phys = ir->input_phys; |
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| 198 | 151 | rc_dev->device_name = ir->device_name; |
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| .. | .. |
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| 203 | 156 | rc_dev->dev.parent = &dev->pci_dev->dev; |
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| 204 | 157 | |
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| 205 | 158 | rc_dev->map_name = dev->info->rc_map; |
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| 159 | + rc_dev->timeout = SMI_SAMPLE_PERIOD * SMI_SAMPLE_IDLEMIN; |
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| 160 | + rc_dev->rx_resolution = SMI_SAMPLE_PERIOD; |
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| 206 | 161 | |
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| 207 | 162 | ir->rc_dev = rc_dev; |
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| 208 | 163 | ir->dev = dev; |
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| 209 | 164 | |
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| 210 | | - INIT_WORK(&ir->work, smi_ir_decode); |
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| 211 | 165 | smi_ir_disableInterrupt(ir); |
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| 212 | 166 | |
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| 213 | 167 | ret = rc_register_device(rc_dev); |
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| .. | .. |
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| 225 | 179 | struct smi_rc *ir = &dev->ir; |
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| 226 | 180 | struct rc_dev *rc_dev = ir->rc_dev; |
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| 227 | 181 | |
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| 228 | | - smi_ir_stop(ir); |
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| 229 | 182 | rc_unregister_device(rc_dev); |
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| 183 | + smi_ir_stop(ir); |
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| 230 | 184 | ir->rc_dev = NULL; |
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| 231 | 185 | } |
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