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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * Driver for the Conexant CX23885/7/8 PCIe bridge |
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3 | 4 | * |
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4 | 5 | * CX23888 Integrated Consumer Infrared Controller |
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5 | 6 | * |
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6 | 7 | * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net> |
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7 | | - * |
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8 | | - * This program is free software; you can redistribute it and/or |
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9 | | - * modify it under the terms of the GNU General Public License |
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10 | | - * as published by the Free Software Foundation; either version 2 |
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11 | | - * of the License, or (at your option) any later version. |
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12 | | - * |
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13 | | - * This program is distributed in the hope that it will be useful, |
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14 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | | - * GNU General Public License for more details. |
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17 | 8 | */ |
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18 | 9 | |
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19 | 10 | #include "cx23885.h" |
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.. | .. |
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184 | 175 | return (u16) d; |
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185 | 176 | } |
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186 | 177 | |
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187 | | -static inline u16 ns_to_clock_divider(unsigned int ns) |
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188 | | -{ |
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189 | | - return count_to_clock_divider( |
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190 | | - DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); |
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191 | | -} |
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192 | | - |
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193 | | -static inline unsigned int clock_divider_to_ns(unsigned int divider) |
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194 | | -{ |
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195 | | - /* Period of the Rx or Tx clock in ns */ |
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196 | | - return DIV_ROUND_CLOSEST((divider + 1) * 1000, |
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197 | | - CX23888_IR_REFCLK_FREQ / 1000000); |
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198 | | -} |
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199 | | - |
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200 | 178 | static inline u16 carrier_freq_to_clock_divider(unsigned int freq) |
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201 | 179 | { |
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202 | 180 | return count_to_clock_divider( |
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.. | .. |
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206 | 184 | static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) |
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207 | 185 | { |
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208 | 186 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); |
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209 | | -} |
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210 | | - |
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211 | | -static inline u16 freq_to_clock_divider(unsigned int freq, |
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212 | | - unsigned int rollovers) |
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213 | | -{ |
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214 | | - return count_to_clock_divider( |
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215 | | - DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers)); |
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216 | 187 | } |
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217 | 188 | |
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218 | 189 | static inline unsigned int clock_divider_to_freq(unsigned int divider, |
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.. | .. |
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548 | 519 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ |
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549 | 520 | |
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550 | 521 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ |
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551 | | - rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ |
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| 522 | + rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */ |
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552 | 523 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ |
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553 | 524 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ |
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554 | 525 | |
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.. | .. |
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638 | 609 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; |
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639 | 610 | } |
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640 | 611 | if (v) { |
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641 | | - /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ |
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| 612 | + /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */ |
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642 | 613 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v); |
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643 | 614 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl); |
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644 | 615 | *handled = true; |
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.. | .. |
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692 | 663 | } |
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693 | 664 | |
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694 | 665 | v = (unsigned) pulse_width_count_to_ns( |
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695 | | - (u16) (p->hw_fifo_data & FIFO_RXTX), divider); |
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| 666 | + (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000; |
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696 | 667 | if (v > IR_MAX_DURATION) |
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697 | 668 | v = IR_MAX_DURATION; |
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698 | 669 | |
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699 | | - init_ir_raw_event(&p->ir_core_data); |
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700 | | - p->ir_core_data.pulse = u; |
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701 | | - p->ir_core_data.duration = v; |
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702 | | - p->ir_core_data.timeout = w; |
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| 670 | + p->ir_core_data = (struct ir_raw_event) |
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| 671 | + { .pulse = u, .duration = v, .timeout = w }; |
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703 | 672 | |
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704 | 673 | v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n", |
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705 | 674 | v, u ? "mark" : "space", w ? "(timed out)" : ""); |
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