update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/pci/cobalt/cobalt-driver.c
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@@ -186,20 +186,16 @@
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 {
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 	struct pci_dev *pci_dev = cobalt->pci_dev;
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 	struct pci_dev *pci_bus_dev = cobalt->pci_dev->bus->self;
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-	int offset;
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-	int bus_offset;
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 	u32 capa;
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 	u16 stat, ctrl;
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-	offset = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
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-	bus_offset = pci_find_capability(pci_bus_dev, PCI_CAP_ID_EXP);
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-	if (!offset || !bus_offset)
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+	if (!pci_is_pcie(pci_dev) || !pci_is_pcie(pci_bus_dev))
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 		return;
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 	/* Device */
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-	pci_read_config_dword(pci_dev, offset + PCI_EXP_DEVCAP, &capa);
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_DEVCTL, &ctrl);
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_DEVSTA, &stat);
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+	pcie_capability_read_dword(pci_dev, PCI_EXP_DEVCAP, &capa);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_DEVCTL, &ctrl);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_DEVSTA, &stat);
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 	cobalt_info("PCIe device capability 0x%08x: Max payload %d\n",
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 		    capa, get_payload_size(capa & PCI_EXP_DEVCAP_PAYLOAD));
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 	cobalt_info("PCIe device control 0x%04x: Max payload %d. Max read request %d\n",
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@@ -209,9 +205,9 @@
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 	cobalt_info("PCIe device status 0x%04x\n", stat);
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 	/* Link */
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-	pci_read_config_dword(pci_dev, offset + PCI_EXP_LNKCAP, &capa);
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_LNKCTL, &ctrl);
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_LNKSTA, &stat);
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+	pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &capa);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &ctrl);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &stat);
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 	cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n",
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 			capa, get_link_speed(capa),
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 			(capa & PCI_EXP_LNKCAP_MLW) >> 4);
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@@ -221,15 +217,15 @@
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 		    (stat & PCI_EXP_LNKSTA_NLW) >> 4);
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 	/* Bus */
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-	pci_read_config_dword(pci_bus_dev, bus_offset + PCI_EXP_LNKCAP, &capa);
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+	pcie_capability_read_dword(pci_bus_dev, PCI_EXP_LNKCAP, &capa);
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 	cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n",
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 			capa, get_link_speed(capa),
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 			(capa & PCI_EXP_LNKCAP_MLW) >> 4);
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 	/* Slot */
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-	pci_read_config_dword(pci_dev, offset + PCI_EXP_SLTCAP, &capa);
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_SLTCTL, &ctrl);
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_SLTSTA, &stat);
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+	pcie_capability_read_dword(pci_dev, PCI_EXP_SLTCAP, &capa);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_SLTCTL, &ctrl);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_SLTSTA, &stat);
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 	cobalt_info("PCIe slot capability 0x%08x\n", capa);
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 	cobalt_info("PCIe slot control 0x%04x\n", ctrl);
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 	cobalt_info("PCIe slot status 0x%04x\n", stat);
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@@ -238,26 +234,22 @@
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 static unsigned pcie_link_get_lanes(struct cobalt *cobalt)
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 {
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 	struct pci_dev *pci_dev = cobalt->pci_dev;
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-	unsigned offset;
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 	u16 link;
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-	offset = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
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-	if (!offset)
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+	if (!pci_is_pcie(pci_dev))
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 		return 0;
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-	pci_read_config_word(pci_dev, offset + PCI_EXP_LNKSTA, &link);
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+	pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &link);
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 	return (link & PCI_EXP_LNKSTA_NLW) >> 4;
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 }
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 static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt)
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 {
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 	struct pci_dev *pci_dev = cobalt->pci_dev->bus->self;
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-	unsigned offset;
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 	u32 link;
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-	offset = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
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-	if (!offset)
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+	if (!pci_is_pcie(pci_dev))
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 		return 0;
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-	pci_read_config_dword(pci_dev, offset + PCI_EXP_LNKCAP, &link);
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+	pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &link);
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 	return (link & PCI_EXP_LNKCAP_MLW) >> 4;
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 }
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..
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@@ -592,7 +584,7 @@
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 		.cec_clk = 12000000,
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 	};
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 	static struct i2c_board_info adv7511_info = {
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-		.type = "adv7511",
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+		.type = "adv7511-v4l2",
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 		.addr = 0x39, /* 0x39 or 0x3d */
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 		.platform_data = &adv7511_pdata,
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 	};