update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h
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@@ -18,6 +18,9 @@
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 /* Test Code: 0x44 (HS RX Control of Lane 0) */
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 #define HSFREQRANGE(x)			UPDATE(x, 6, 1)
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+#define HSTX(x)				UPDATE(x, 6, 0)
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+#define HSZERO(x)			UPDATE(x, 5, 0)
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+#define HSPOST(x)			UPDATE(x, 4, 0)
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 static inline void testif_testclk_assert(struct rk628 *rk628)
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 {
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@@ -189,6 +192,40 @@
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 	testif_write(rk628, 0x44, HSFREQRANGE(hsfreqrange));
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 }
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+static void __maybe_unused mipi_dphy_init_hsmanual(struct rk628 *rk628, bool manual)
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+{
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+	if (manual) {
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+		//config mipi timing when mipi freq is 1250Mbps
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+		testif_write(rk628, 0x71, HSTX(0x4a) | BIT(7));
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x72, HSZERO(0xf) | BIT(6));
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x73, HSTX(0x5d) | BIT(7));
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x61, HSTX(0x3a) | BIT(7));
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x62, HSZERO(0x3a) | BIT(6));
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x63, HSTX(0x5a) | BIT(7));
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x65, HSPOST(0x1f) | BIT(5));
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+	} else {
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+		testif_write(rk628, 0x71, 0);
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x72, 0);
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x73, 0);
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x61, 0);
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x62, 0);
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x63, 0);
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+		usleep_range(1500, 2000);
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+		testif_write(rk628, 0x65, 0);
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+	}
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+}
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+
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 static inline int mipi_dphy_reset(struct rk628 *rk628)
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 {
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 	u32 val, mask;