update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/i2c/ov7251.c
..
..
@@ -2,16 +2,12 @@
2
2
 /*
3
3
  * ov7251 driver
4
4
  *
5
- * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
5
+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6
6
  *
7
- * V0.0X01.0X01 add poweron function.
8
- * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9
- * V0.0X01.0X03 add enum_frame_interval function.
10
- * V0.0X01.0X04 add quick stream on/off
11
- * V0.0X01.0X05 add function g_mbus_config
12
- * V0.0X01.0X06 support 640x480@120fps mode
7
+ * V0.0X01.0X01 first version
13
8
  */
14
9
 
10
+//#define DEBUG
15
11
 #include <linux/clk.h>
16
12
 #include <linux/device.h>
17
13
 #include <linux/delay.h>
..
..
@@ -19,28 +15,33 @@
19
15
 #include <linux/i2c.h>
20
16
 #include <linux/module.h>
21
17
 #include <linux/pm_runtime.h>
22
-#include <linux/pinctrl/consumer.h>
23
18
 #include <linux/regulator/consumer.h>
24
19
 #include <linux/sysfs.h>
25
20
 #include <linux/slab.h>
26
21
 #include <linux/version.h>
27
22
 #include <linux/rk-camera-module.h>
23
+#include <linux/rk-preisp.h>
28
24
 #include <media/media-entity.h>
29
25
 #include <media/v4l2-async.h>
30
26
 #include <media/v4l2-ctrls.h>
31
27
 #include <media/v4l2-subdev.h>
28
+#include <linux/pinctrl/consumer.h>
32
29
 
33
-#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x06)
30
+#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x01)
34
31
 
35
32
 #ifndef V4L2_CID_DIGITAL_GAIN
36
33
 #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
37
34
 #endif
38
35
 
39
-/* 48Mhz */
40
-#define OV7251_PIXEL_RATE		(48 * 1000 * 1000)
36
+#define OV7251_LANES			1
37
+#define OV7251_BITS_PER_SAMPLE		10
38
+#define OV7251_LINK_FREQ_240		240000000
39
+
40
+#define PIXEL_RATE_WITH_240M_10BIT	(OV7251_LINK_FREQ_240 * 2 * \
41
+					OV7251_LANES / OV7251_BITS_PER_SAMPLE)
41
42
 #define OV7251_XVCLK_FREQ		24000000
42
43
 
43
-#define CHIP_ID				0x007750
44
+#define CHIP_ID				0x77
44
45
 #define OV7251_REG_CHIP_ID		0x300a
45
46
 #define OV7251_REG_MOD_VENDOR_ID	0x3d10
46
47
 #define OV7251_REG_OPT_LOAD_CTRL	0x3d81
..
..
@@ -53,7 +54,6 @@
53
54
 #define OV7251_EXPOSURE_MIN		4
54
55
 #define OV7251_EXPOSURE_STEP		0xf
55
56
 #define OV7251_VTS_MAX			0xffff
56
-#define OV7251_REG_VTS			0x380e
57
57
 
58
58
 #define OV7251_REG_ANALOG_GAIN		0x350a
59
59
 #define ANALOG_GAIN_MASK		0x3ff
..
..
@@ -66,23 +66,29 @@
66
66
 #define	OV7251_TEST_PATTERN_ENABLE	0x80
67
67
 #define	OV7251_TEST_PATTERN_DISABLE	0x0
68
68
 
69
+#define OV7251_REG_VTS			0x380e
70
+
71
+#define OV7251_MIRROR_REG		0x3821
72
+#define OV7251_FLIP_REG		0x3820
73
+
74
+#define OV7251_FETCH_MIRROR(VAL, ENABLE)	(ENABLE ? VAL | 0x01 : VAL & 0xf9)
75
+#define OV7251_FETCH_FLIP(VAL, ENABLE)		(ENABLE ? VAL | 0x01 : VAL & 0x9f)
76
+
77
+#define REG_DELAY			0xFFFE
69
78
 #define REG_NULL			0xFFFF
70
79
 
71
80
 #define OV7251_REG_VALUE_08BIT		1
72
81
 #define OV7251_REG_VALUE_16BIT		2
73
82
 #define OV7251_REG_VALUE_24BIT		3
74
83
 
75
-#define OV7251_NAME			"ov7251"
76
-#define OV7251_LANES			1
77
-#define PIX_FORMAT			MEDIA_BUS_FMT_Y10_1X10
78
-
79
84
 #define OF_CAMERA_PINCTRL_STATE_DEFAULT	"rockchip,camera_default"
80
85
 #define OF_CAMERA_PINCTRL_STATE_SLEEP	"rockchip,camera_sleep"
86
+#define OV7251_NAME			"ov7251"
81
87
 
82
88
 static const char * const ov7251_supply_names[] = {
83
89
 	"avdd",		/* Analog power */
84
90
 	"dovdd",	/* Digital I/O power */
85
-	"dvdd",		/* Digital core power  not needed*/
91
+	"dvdd",		/* Digital core power */
86
92
 };
87
93
 
88
94
 #define OV7251_NUM_SUPPLIES ARRAY_SIZE(ov7251_supply_names)
..
..
@@ -93,6 +99,7 @@
93
99
 };
94
100
 
95
101
 struct ov7251_mode {
102
+	u32 bus_fmt;
96
103
 	u32 width;
97
104
 	u32 height;
98
105
 	struct v4l2_fract max_fps;
..
..
@@ -101,6 +108,7 @@
101
108
 	u32 exp_def;
102
109
 	const struct regval *reg_list;
103
110
 	u32 hdr_mode;
111
+	u32 vc[PAD_MAX];
104
112
 };
105
113
 
106
114
 struct ov7251 {
..
..
@@ -109,9 +117,11 @@
109
117
 	struct gpio_desc	*reset_gpio;
110
118
 	struct gpio_desc	*pwdn_gpio;
111
119
 	struct regulator_bulk_data supplies[OV7251_NUM_SUPPLIES];
120
+
112
121
 	struct pinctrl		*pinctrl;
113
122
 	struct pinctrl_state	*pins_default;
114
123
 	struct pinctrl_state	*pins_sleep;
124
+
115
125
 	struct v4l2_subdev	subdev;
116
126
 	struct media_pad	pad;
117
127
 	struct v4l2_ctrl_handler ctrl_handler;
..
..
@@ -125,26 +135,25 @@
125
135
 	bool			streaming;
126
136
 	bool			power_on;
127
137
 	const struct ov7251_mode *cur_mode;
138
+	struct v4l2_fract	cur_fps;
128
139
 	u32			module_index;
129
140
 	const char		*module_facing;
130
141
 	const char		*module_name;
131
142
 	const char		*len_name;
143
+	u32			cur_vts;
132
144
 };
133
145
 
134
146
 #define to_ov7251(sd) container_of(sd, struct ov7251, subdev)
135
147
 
136
148
 /*
137
149
  * Xclk 24Mhz
138
- * Pclk 48Mhz
139
- * PCLK = HTS * VTS * FPS
140
- * linelength 775(0x302)
141
- * framelength 516(0x204)
142
- * grabwindow_width 640
143
- * grabwindow_height 480
144
- * max_framerate 120fps
145
- * mipi_datarate per lane 640Mbps
146
150
  */
147
-static const struct regval ov7251_640x480_120fps_regs[] = {
151
+static const struct regval ov7251_global_regs[] = {
152
+	{REG_NULL, 0x00},
153
+};
154
+
155
+
156
+static __maybe_unused const struct regval ov7251_640x480_120fps_regs[] = {
148
157
 	{0x0103, 0x01},
149
158
 	{0x0100, 0x00},
150
159
 	{0x3005, 0x00},
..
..
@@ -289,159 +298,424 @@
289
298
 
290
299
 /*
291
300
  * Xclk 24Mhz
292
- * Pclk 48Mhz
293
- * PCLK = HTS * VTS * FPS
294
- * linelength 928(0x3a0)
295
- * framelength 1720(0x6b8)
296
- * grabwindow_width 640
297
- * grabwindow_height 480
298
301
  * max_framerate 30fps
299
- * mipi_datarate per lane 640Mbps
302
+ * mipi_datarate per lane 630Mbps, 2lane
300
303
  */
301
-static const struct regval ov7251_640x480_30fps_regs[] = {
302
-	{0x0100, 0x00},
303
-	{0x0103, 0x01},
304
-	{0x3001, 0x62},
305
-	{0x3005, 0x00},
306
-	{0x3012, 0xc0},
307
-	{0x3013, 0xd2},
308
-	{0x3014, 0x04},
309
-	{0x3016, 0x10},
310
-	{0x3017, 0x00},
311
-	{0x3018, 0x00},
312
-	{0x301a, 0x00},
313
-	{0x301b, 0x00},
314
-	{0x301c, 0x20},
315
-	{0x3023, 0x05},
316
-	{0x3037, 0xf0},
317
-	{0x3098, 0x04},
318
-	{0x3099, 0x28},
319
-	{0x309a, 0x05},
320
-	{0x309b, 0x04},
321
-	{0x30b0, 0x0a},
322
-	{0x30b1, 0x01},
323
-	{0x30b3, 0x64},
324
-	{0x30b4, 0x03},
325
-	{0x30b5, 0x05},
326
-	{0x3106, 0xda},
327
-	{0x3500, 0x00},
328
-	{0x3501, 0x1f},
329
-	{0x3502, 0x80},
330
-	{0x3503, 0x07},
331
-	{0x3509, 0x10},
332
-	{0x350b, 0x10},
333
-	{0x3600, 0x1c},
334
-	{0x3602, 0x62},
335
-	{0x3620, 0xb7},
336
-	{0x3622, 0x04},
337
-	{0x3626, 0x21},
338
-	{0x3627, 0x30},
339
-	{0x3630, 0x44},
340
-	{0x3631, 0x35},
341
-	{0x3634, 0x60},
342
-	{0x3636, 0x00},
343
-	{0x3662, 0x01},
344
-	{0x3663, 0x70},
345
-	{0x3664, 0xf0},
346
-	{0x3666, 0x0a},
347
-	{0x3669, 0x1a},
348
-	{0x366a, 0x00},
349
-	{0x366b, 0x50},
350
-	{0x3673, 0x01},
351
-	{0x3674, 0xff},
352
-	{0x3675, 0x03},
353
-	{0x3705, 0xc1},
354
-	{0x3709, 0x40},
355
-	{0x373c, 0x08},
356
-	{0x3742, 0x00},
357
-	{0x3757, 0xb3},
358
-	{0x3788, 0x00},
359
-	{0x37a8, 0x01},
360
-	{0x37a9, 0xc0},
361
-	{0x3800, 0x00},
362
-	{0x3801, 0x04},
363
-	{0x3802, 0x00},
364
-	{0x3803, 0x04},
365
-	{0x3804, 0x02},
366
-	{0x3805, 0x8b},
367
-	{0x3806, 0x01},
368
-	{0x3807, 0xeb},
369
-	{0x3808, 0x02},
370
-	{0x3809, 0x80},
371
-	{0x380a, 0x01},
372
-	{0x380b, 0xe0},
373
-	{0x380c, 0x03},
374
-	{0x380d, 0xa0},
375
-	{0x380e, 0x06},
376
-	{0x380f, 0xb8},
377
-	{0x3810, 0x00},
378
-	{0x3811, 0x02},
379
-	{0x3812, 0x00},
380
-	{0x3813, 0x02},
381
-	{0x3814, 0x11},
382
-	{0x3815, 0x11},
383
-	{0x3820, 0x40},
384
-	{0x3821, 0x00},
385
-	{0x382f, 0x0e},
386
-	{0x3832, 0x00},
387
-	{0x3833, 0x05},
388
-	{0x3834, 0x00},
389
-	{0x3835, 0x0c},
390
-	{0x3837, 0x00},
391
-	{0x3b80, 0x00},
392
-	{0x3b81, 0xa5},
393
-	{0x3b82, 0x10},
394
-	{0x3b83, 0x00},
395
-	{0x3b84, 0x08},
396
-	{0x3b85, 0x00},
397
-	{0x3b86, 0x01},
398
-	{0x3b87, 0x00},
399
-	{0x3b88, 0x00},
400
-	{0x3b89, 0x00},
401
-	{0x3b8a, 0x00},
402
-	{0x3b8b, 0x05},
403
-	{0x3b8c, 0x00},
404
-	{0x3b8d, 0x00},
405
-	{0x3b8e, 0x00},
406
-	{0x3b8f, 0x1a},
407
-	{0x3b94, 0x05},
408
-	{0x3b95, 0xf2},
409
-	{0x3b96, 0x40},
410
-	{0x3c00, 0x89},
411
-	{0x3c01, 0x63},
412
-	{0x3c02, 0x01},
413
-	{0x3c03, 0x00},
414
-	{0x3c04, 0x00},
415
-	{0x3c05, 0x03},
416
-	{0x3c06, 0x00},
417
-	{0x3c07, 0x06},
418
-	{0x3c0c, 0x01},
419
-	{0x3c0d, 0xd0},
420
-	{0x3c0e, 0x02},
421
-	{0x3c0f, 0x04},
422
-	{0x4001, 0x42},
423
-	{0x4004, 0x04},
424
-	{0x4005, 0x00},
425
-	{0x404e, 0x01},
426
-	{0x4241, 0x00},
427
-	{0x4242, 0x00},
428
-	{0x4300, 0xff},
429
-	{0x4301, 0x00},
430
-	{0x4501, 0x48},
431
-	{0x4600, 0x00},
432
-	{0x4601, 0x4e},
433
-	{0x4801, 0x0f},
434
-	{0x4806, 0x0f},
435
-	{0x4819, 0xaa},
436
-	{0x4823, 0x3e},
437
-	{0x4837, 0x19},
438
-	{0x4a0d, 0x00},
439
-	{0x4a47, 0x7f},
440
-	{0x4a49, 0xf0},
441
-	{0x4a4b, 0x30},
442
-	{0x5000, 0x85},
443
-	{0x5001, 0x80},
444
-	{REG_NULL, 0x00},
304
+static __maybe_unused const struct regval ov7251_setting_vga_30fps[] = {
305
+	{ 0x3005, 0x00 },
306
+	{ 0x3012, 0xc0 },
307
+	{ 0x3013, 0xd2 },
308
+	{ 0x3014, 0x04 },
309
+	{ 0x3016, 0xf0 },
310
+	{ 0x3017, 0xf0 },
311
+	{ 0x3018, 0xf0 },
312
+	{ 0x301a, 0xf0 },
313
+	{ 0x301b, 0xf0 },
314
+	{ 0x301c, 0xf0 },
315
+	{ 0x3023, 0x05 },
316
+	{ 0x3037, 0xf0 },
317
+	{ 0x3098, 0x04 }, /* pll2 pre divider */
318
+	{ 0x3099, 0x28 }, /* pll2 multiplier */
319
+	{ 0x309a, 0x05 }, /* pll2 sys divider */
320
+	{ 0x309b, 0x04 }, /* pll2 adc divider */
321
+	{ 0x309d, 0x00 }, /* pll2 divider */
322
+	{ 0x30b0, 0x0a }, /* pll1 pix divider */
323
+	{ 0x30b1, 0x01 }, /* pll1 divider */
324
+	{ 0x30b3, 0x64 }, /* pll1 multiplier */
325
+	{ 0x30b4, 0x03 }, /* pll1 pre divider */
326
+	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
327
+	{ 0x3106, 0xda },
328
+	{ 0x3503, 0x07 },
329
+	{ 0x3509, 0x10 },
330
+	{ 0x3600, 0x1c },
331
+	{ 0x3602, 0x62 },
332
+	{ 0x3620, 0xb7 },
333
+	{ 0x3622, 0x04 },
334
+	{ 0x3626, 0x21 },
335
+	{ 0x3627, 0x30 },
336
+	{ 0x3630, 0x44 },
337
+	{ 0x3631, 0x35 },
338
+	{ 0x3634, 0x60 },
339
+	{ 0x3636, 0x00 },
340
+	{ 0x3662, 0x01 },
341
+	{ 0x3663, 0x70 },
342
+	{ 0x3664, 0x50 },
343
+	{ 0x3666, 0x0a },
344
+	{ 0x3669, 0x1a },
345
+	{ 0x366a, 0x00 },
346
+	{ 0x366b, 0x50 },
347
+	{ 0x3673, 0x01 },
348
+	{ 0x3674, 0xff },
349
+	{ 0x3675, 0x03 },
350
+	{ 0x3705, 0xc1 },
351
+	{ 0x3709, 0x40 },
352
+	{ 0x373c, 0x08 },
353
+	{ 0x3742, 0x00 },
354
+	{ 0x3757, 0xb3 },
355
+	{ 0x3788, 0x00 },
356
+	{ 0x37a8, 0x01 },
357
+	{ 0x37a9, 0xc0 },
358
+	{ 0x3800, 0x00 },
359
+	{ 0x3801, 0x04 },
360
+	{ 0x3802, 0x00 },
361
+	{ 0x3803, 0x04 },
362
+	{ 0x3804, 0x02 },
363
+	{ 0x3805, 0x8b },
364
+	{ 0x3806, 0x01 },
365
+	{ 0x3807, 0xeb },
366
+	{ 0x3808, 0x02 }, /* width high */
367
+	{ 0x3809, 0x80 }, /* width low */
368
+	{ 0x380a, 0x01 }, /* height high */
369
+	{ 0x380b, 0xe0 }, /* height low */
370
+	{ 0x380c, 0x03 }, /* total horiz timing high */
371
+	{ 0x380d, 0xa0 }, /* total horiz timing low */
372
+	{ 0x380e, 0x06 }, /* total vertical timing high */
373
+	{ 0x380f, 0xbc }, /* total vertical timing low */
374
+	{ 0x3810, 0x00 },
375
+	{ 0x3811, 0x04 },
376
+	{ 0x3812, 0x00 },
377
+	{ 0x3813, 0x05 },
378
+	{ 0x3814, 0x11 },
379
+	{ 0x3815, 0x11 },
380
+	{ 0x3820, 0x40 },
381
+	{ 0x3821, 0x00 },
382
+	{ 0x382f, 0x0e },
383
+	{ 0x3832, 0x00 },
384
+	{ 0x3833, 0x05 },
385
+	{ 0x3834, 0x00 },
386
+	{ 0x3835, 0x0c },
387
+	{ 0x3837, 0x00 },
388
+	{ 0x3b80, 0x00 },
389
+	{ 0x3b81, 0xa5 },
390
+	{ 0x3b82, 0x10 },
391
+	{ 0x3b83, 0x00 },
392
+	{ 0x3b84, 0x08 },
393
+	{ 0x3b85, 0x00 },
394
+	{ 0x3b86, 0x01 },
395
+	{ 0x3b87, 0x00 },
396
+	{ 0x3b88, 0x00 },
397
+	{ 0x3b89, 0x00 },
398
+	{ 0x3b8a, 0x00 },
399
+	{ 0x3b8b, 0x05 },
400
+	{ 0x3b8c, 0x00 },
401
+	{ 0x3b8d, 0x00 },
402
+	{ 0x3b8e, 0x00 },
403
+	{ 0x3b8f, 0x1a },
404
+	{ 0x3b94, 0x05 },
405
+	{ 0x3b95, 0xf2 },
406
+	{ 0x3b96, 0x40 },
407
+	{ 0x3c00, 0x89 },
408
+	{ 0x3c01, 0x63 },
409
+	{ 0x3c02, 0x01 },
410
+	{ 0x3c03, 0x00 },
411
+	{ 0x3c04, 0x00 },
412
+	{ 0x3c05, 0x03 },
413
+	{ 0x3c06, 0x00 },
414
+	{ 0x3c07, 0x06 },
415
+	{ 0x3c0c, 0x01 },
416
+	{ 0x3c0d, 0xd0 },
417
+	{ 0x3c0e, 0x02 },
418
+	{ 0x3c0f, 0x0a },
419
+	{ 0x4001, 0x42 },
420
+	{ 0x4004, 0x04 },
421
+	{ 0x4005, 0x00 },
422
+	{ 0x404e, 0x01 },
423
+	{ 0x4300, 0xff },
424
+	{ 0x4301, 0x00 },
425
+	{ 0x4315, 0x00 },
426
+	{ 0x4501, 0x48 },
427
+	{ 0x4600, 0x00 },
428
+	{ 0x4601, 0x4e },
429
+	{ 0x4801, 0x0f },
430
+	{ 0x4806, 0x0f },
431
+	{ 0x4819, 0xaa },
432
+	{ 0x4823, 0x3e },
433
+	{ 0x4837, 0x19 },
434
+	{ 0x4a0d, 0x00 },
435
+	{ 0x4a47, 0x7f },
436
+	{ 0x4a49, 0xf0 },
437
+	{ 0x4a4b, 0x30 },
438
+	{ 0x5000, 0x85 },
439
+	{ 0x5001, 0x80 },
440
+	{REG_NULL, 0x00 },
441
+};
442
+
443
+static __maybe_unused const struct regval ov7251_setting_vga_60fps[] = {
444
+	{ 0x3005, 0x00 },
445
+	{ 0x3012, 0xc0 },
446
+	{ 0x3013, 0xd2 },
447
+	{ 0x3014, 0x04 },
448
+	{ 0x3016, 0x10 },
449
+	{ 0x3017, 0x00 },
450
+	{ 0x3018, 0x00 },
451
+	{ 0x301a, 0x00 },
452
+	{ 0x301b, 0x00 },
453
+	{ 0x301c, 0x00 },
454
+	{ 0x3023, 0x05 },
455
+	{ 0x3037, 0xf0 },
456
+	{ 0x3098, 0x04 }, /* pll2 pre divider */
457
+	{ 0x3099, 0x28 }, /* pll2 multiplier */
458
+	{ 0x309a, 0x05 }, /* pll2 sys divider */
459
+	{ 0x309b, 0x04 }, /* pll2 adc divider */
460
+	{ 0x309d, 0x00 }, /* pll2 divider */
461
+	{ 0x30b0, 0x0a }, /* pll1 pix divider */
462
+	{ 0x30b1, 0x01 }, /* pll1 divider */
463
+	{ 0x30b3, 0x64 }, /* pll1 multiplier */
464
+	{ 0x30b4, 0x03 }, /* pll1 pre divider */
465
+	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
466
+	{ 0x3106, 0xda },
467
+	{ 0x3503, 0x07 },
468
+	{ 0x3509, 0x10 },
469
+	{ 0x3600, 0x1c },
470
+	{ 0x3602, 0x62 },
471
+	{ 0x3620, 0xb7 },
472
+	{ 0x3622, 0x04 },
473
+	{ 0x3626, 0x21 },
474
+	{ 0x3627, 0x30 },
475
+	{ 0x3630, 0x44 },
476
+	{ 0x3631, 0x35 },
477
+	{ 0x3634, 0x60 },
478
+	{ 0x3636, 0x00 },
479
+	{ 0x3662, 0x01 },
480
+	{ 0x3663, 0x70 },
481
+	{ 0x3664, 0x50 },
482
+	{ 0x3666, 0x0a },
483
+	{ 0x3669, 0x1a },
484
+	{ 0x366a, 0x00 },
485
+	{ 0x366b, 0x50 },
486
+	{ 0x3673, 0x01 },
487
+	{ 0x3674, 0xff },
488
+	{ 0x3675, 0x03 },
489
+	{ 0x3705, 0xc1 },
490
+	{ 0x3709, 0x40 },
491
+	{ 0x373c, 0x08 },
492
+	{ 0x3742, 0x00 },
493
+	{ 0x3757, 0xb3 },
494
+	{ 0x3788, 0x00 },
495
+	{ 0x37a8, 0x01 },
496
+	{ 0x37a9, 0xc0 },
497
+	{ 0x3800, 0x00 },
498
+	{ 0x3801, 0x04 },
499
+	{ 0x3802, 0x00 },
500
+	{ 0x3803, 0x04 },
501
+	{ 0x3804, 0x02 },
502
+	{ 0x3805, 0x8b },
503
+	{ 0x3806, 0x01 },
504
+	{ 0x3807, 0xeb },
505
+	{ 0x3808, 0x02 }, /* width high */
506
+	{ 0x3809, 0x80 }, /* width low */
507
+	{ 0x380a, 0x01 }, /* height high */
508
+	{ 0x380b, 0xe0 }, /* height low */
509
+	{ 0x380c, 0x03 }, /* total horiz timing high */
510
+	{ 0x380d, 0xa0 }, /* total horiz timing low */
511
+	{ 0x380e, 0x03 }, /* total vertical timing high */
512
+	{ 0x380f, 0x5c }, /* total vertical timing low */
513
+	{ 0x3810, 0x00 },
514
+	{ 0x3811, 0x04 },
515
+	{ 0x3812, 0x00 },
516
+	{ 0x3813, 0x05 },
517
+	{ 0x3814, 0x11 },
518
+	{ 0x3815, 0x11 },
519
+	{ 0x3820, 0x40 },
520
+	{ 0x3821, 0x00 },
521
+	{ 0x382f, 0x0e },
522
+	{ 0x3832, 0x00 },
523
+	{ 0x3833, 0x05 },
524
+	{ 0x3834, 0x00 },
525
+	{ 0x3835, 0x0c },
526
+	{ 0x3837, 0x00 },
527
+	{ 0x3b80, 0x00 },
528
+	{ 0x3b81, 0xa5 },
529
+	{ 0x3b82, 0x10 },
530
+	{ 0x3b83, 0x00 },
531
+	{ 0x3b84, 0x08 },
532
+	{ 0x3b85, 0x00 },
533
+	{ 0x3b86, 0x01 },
534
+	{ 0x3b87, 0x00 },
535
+	{ 0x3b88, 0x00 },
536
+	{ 0x3b89, 0x00 },
537
+	{ 0x3b8a, 0x00 },
538
+	{ 0x3b8b, 0x05 },
539
+	{ 0x3b8c, 0x00 },
540
+	{ 0x3b8d, 0x00 },
541
+	{ 0x3b8e, 0x00 },
542
+	{ 0x3b8f, 0x1a },
543
+	{ 0x3b94, 0x05 },
544
+	{ 0x3b95, 0xf2 },
545
+	{ 0x3b96, 0x40 },
546
+	{ 0x3c00, 0x89 },
547
+	{ 0x3c01, 0x63 },
548
+	{ 0x3c02, 0x01 },
549
+	{ 0x3c03, 0x00 },
550
+	{ 0x3c04, 0x00 },
551
+	{ 0x3c05, 0x03 },
552
+	{ 0x3c06, 0x00 },
553
+	{ 0x3c07, 0x06 },
554
+	{ 0x3c0c, 0x01 },
555
+	{ 0x3c0d, 0xd0 },
556
+	{ 0x3c0e, 0x02 },
557
+	{ 0x3c0f, 0x0a },
558
+	{ 0x4001, 0x42 },
559
+	{ 0x4004, 0x04 },
560
+	{ 0x4005, 0x00 },
561
+	{ 0x404e, 0x01 },
562
+	{ 0x4300, 0xff },
563
+	{ 0x4301, 0x00 },
564
+	{ 0x4315, 0x00 },
565
+	{ 0x4501, 0x48 },
566
+	{ 0x4600, 0x00 },
567
+	{ 0x4601, 0x4e },
568
+	{ 0x4801, 0x0f },
569
+	{ 0x4806, 0x0f },
570
+	{ 0x4819, 0xaa },
571
+	{ 0x4823, 0x3e },
572
+	{ 0x4837, 0x19 },
573
+	{ 0x4a0d, 0x00 },
574
+	{ 0x4a47, 0x7f },
575
+	{ 0x4a49, 0xf0 },
576
+	{ 0x4a4b, 0x30 },
577
+	{ 0x5000, 0x85 },
578
+	{ 0x5001, 0x80 },
579
+	{REG_NULL, 0x00 },
580
+};
581
+
582
+static __maybe_unused const struct regval ov7251_setting_vga_90fps[] = {
583
+	{ 0x3005, 0x00 },
584
+	{ 0x3012, 0xc0 },
585
+	{ 0x3013, 0xd2 },
586
+	{ 0x3014, 0x04 },
587
+	{ 0x3016, 0x10 },
588
+	{ 0x3017, 0x00 },
589
+	{ 0x3018, 0x00 },
590
+	{ 0x301a, 0x00 },
591
+	{ 0x301b, 0x00 },
592
+	{ 0x301c, 0x00 },
593
+	{ 0x3023, 0x05 },
594
+	{ 0x3037, 0xf0 },
595
+	{ 0x3098, 0x04 }, /* pll2 pre divider */
596
+	{ 0x3099, 0x28 }, /* pll2 multiplier */
597
+	{ 0x309a, 0x05 }, /* pll2 sys divider */
598
+	{ 0x309b, 0x04 }, /* pll2 adc divider */
599
+	{ 0x309d, 0x00 }, /* pll2 divider */
600
+	{ 0x30b0, 0x0a }, /* pll1 pix divider */
601
+	{ 0x30b1, 0x01 }, /* pll1 divider */
602
+	{ 0x30b3, 0x64 }, /* pll1 multiplier */
603
+	{ 0x30b4, 0x03 }, /* pll1 pre divider */
604
+	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
605
+	{ 0x3106, 0xda },
606
+	{ 0x3503, 0x07 },
607
+	{ 0x3509, 0x10 },
608
+	{ 0x3600, 0x1c },
609
+	{ 0x3602, 0x62 },
610
+	{ 0x3620, 0xb7 },
611
+	{ 0x3622, 0x04 },
612
+	{ 0x3626, 0x21 },
613
+	{ 0x3627, 0x30 },
614
+	{ 0x3630, 0x44 },
615
+	{ 0x3631, 0x35 },
616
+	{ 0x3634, 0x60 },
617
+	{ 0x3636, 0x00 },
618
+	{ 0x3662, 0x01 },
619
+	{ 0x3663, 0x70 },
620
+	{ 0x3664, 0x50 },
621
+	{ 0x3666, 0x0a },
622
+	{ 0x3669, 0x1a },
623
+	{ 0x366a, 0x00 },
624
+	{ 0x366b, 0x50 },
625
+	{ 0x3673, 0x01 },
626
+	{ 0x3674, 0xff },
627
+	{ 0x3675, 0x03 },
628
+	{ 0x3705, 0xc1 },
629
+	{ 0x3709, 0x40 },
630
+	{ 0x373c, 0x08 },
631
+	{ 0x3742, 0x00 },
632
+	{ 0x3757, 0xb3 },
633
+	{ 0x3788, 0x00 },
634
+	{ 0x37a8, 0x01 },
635
+	{ 0x37a9, 0xc0 },
636
+	{ 0x3800, 0x00 },
637
+	{ 0x3801, 0x04 },
638
+	{ 0x3802, 0x00 },
639
+	{ 0x3803, 0x04 },
640
+	{ 0x3804, 0x02 },
641
+	{ 0x3805, 0x8b },
642
+	{ 0x3806, 0x01 },
643
+	{ 0x3807, 0xeb },
644
+	{ 0x3808, 0x02 }, /* width high */
645
+	{ 0x3809, 0x80 }, /* width low */
646
+	{ 0x380a, 0x01 }, /* height high */
647
+	{ 0x380b, 0xe0 }, /* height low */
648
+	{ 0x380c, 0x03 }, /* total horiz timing high */
649
+	{ 0x380d, 0xa0 }, /* total horiz timing low */
650
+	{ 0x380e, 0x02 }, /* total vertical timing high */
651
+	{ 0x380f, 0x3c }, /* total vertical timing low */
652
+	{ 0x3810, 0x00 },
653
+	{ 0x3811, 0x04 },
654
+	{ 0x3812, 0x00 },
655
+	{ 0x3813, 0x05 },
656
+	{ 0x3814, 0x11 },
657
+	{ 0x3815, 0x11 },
658
+	{ 0x3820, 0x40 },
659
+	{ 0x3821, 0x00 },
660
+	{ 0x382f, 0x0e },
661
+	{ 0x3832, 0x00 },
662
+	{ 0x3833, 0x05 },
663
+	{ 0x3834, 0x00 },
664
+	{ 0x3835, 0x0c },
665
+	{ 0x3837, 0x00 },
666
+	{ 0x3b80, 0x00 },
667
+	{ 0x3b81, 0xa5 },
668
+	{ 0x3b82, 0x10 },
669
+	{ 0x3b83, 0x00 },
670
+	{ 0x3b84, 0x08 },
671
+	{ 0x3b85, 0x00 },
672
+	{ 0x3b86, 0x01 },
673
+	{ 0x3b87, 0x00 },
674
+	{ 0x3b88, 0x00 },
675
+	{ 0x3b89, 0x00 },
676
+	{ 0x3b8a, 0x00 },
677
+	{ 0x3b8b, 0x05 },
678
+	{ 0x3b8c, 0x00 },
679
+	{ 0x3b8d, 0x00 },
680
+	{ 0x3b8e, 0x00 },
681
+	{ 0x3b8f, 0x1a },
682
+	{ 0x3b94, 0x05 },
683
+	{ 0x3b95, 0xf2 },
684
+	{ 0x3b96, 0x40 },
685
+	{ 0x3c00, 0x89 },
686
+	{ 0x3c01, 0x63 },
687
+	{ 0x3c02, 0x01 },
688
+	{ 0x3c03, 0x00 },
689
+	{ 0x3c04, 0x00 },
690
+	{ 0x3c05, 0x03 },
691
+	{ 0x3c06, 0x00 },
692
+	{ 0x3c07, 0x06 },
693
+	{ 0x3c0c, 0x01 },
694
+	{ 0x3c0d, 0xd0 },
695
+	{ 0x3c0e, 0x02 },
696
+	{ 0x3c0f, 0x0a },
697
+	{ 0x4001, 0x42 },
698
+	{ 0x4004, 0x04 },
699
+	{ 0x4005, 0x00 },
700
+	{ 0x404e, 0x01 },
701
+	{ 0x4300, 0xff },
702
+	{ 0x4301, 0x00 },
703
+	{ 0x4315, 0x00 },
704
+	{ 0x4501, 0x48 },
705
+	{ 0x4600, 0x00 },
706
+	{ 0x4601, 0x4e },
707
+	{ 0x4801, 0x0f },
708
+	{ 0x4806, 0x0f },
709
+	{ 0x4819, 0xaa },
710
+	{ 0x4823, 0x3e },
711
+	{ 0x4837, 0x19 },
712
+	{ 0x4a0d, 0x00 },
713
+	{ 0x4a47, 0x7f },
714
+	{ 0x4a49, 0xf0 },
715
+	{ 0x4a4b, 0x30 },
716
+	{ 0x5000, 0x85 },
717
+	{ 0x5001, 0x80 },
718
+	{REG_NULL, 0x00 },
445
719
 };
446
720
 
447
721
 static const struct ov7251_mode supported_modes[] = {
..
..
@@ -455,44 +729,34 @@
455
729
 		.exp_def = 0x00f8,
456
730
 		.hts_def = 0x03a1,
457
731
 		.vts_def = 0x021a,
732
+		.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
458
733
 		.reg_list = ov7251_640x480_120fps_regs,
459
-		.hdr_mode = 0,
460
-	},
461
-	{
462
-		.width = 640,
463
-		.height = 480,
464
-		.max_fps = {
465
-			.numerator = 10000,
466
-			.denominator = 300000,
467
-		},
468
-		.exp_def = 0x061c,
469
-		.hts_def = 0x03a0,
470
-		.vts_def = 0x06b8,
471
-		.reg_list = ov7251_640x480_30fps_regs,
472
-		.hdr_mode = 0,
734
+		.hdr_mode = NO_HDR,
735
+		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
473
736
 	}
474
737
 };
475
738
 
476
-#define OV7251_LINK_FREQ_320MHZ		320000000
477
739
 static const s64 link_freq_menu_items[] = {
478
-	OV7251_LINK_FREQ_320MHZ
740
+	OV7251_LINK_FREQ_240
479
741
 };
480
742
 
481
743
 static const char * const ov7251_test_pattern_menu[] = {
482
744
 	"Disabled",
483
-	"Vertical Color Bar",
745
+	"Vertical Color Bar Type 1",
746
+	"Vertical Color Bar Type 2",
747
+	"Vertical Color Bar Type 3",
748
+	"Vertical Color Bar Type 4"
484
749
 };
485
750
 
486
751
 /* Write registers up to 4 at a time */
487
752
 static int ov7251_write_reg(struct i2c_client *client, u16 reg,
488
-			    int len, u32 val)
753
+			    u32 len, u32 val)
489
754
 {
490
755
 	u32 buf_i, val_i;
491
756
 	u8 buf[6];
492
757
 	u8 *val_p;
493
758
 	__be32 val_be;
494
759
 
495
-	usleep_range(1500, 1600);
496
760
 	if (len > 4)
497
761
 		return -EINVAL;
498
762
 
..
..
@@ -509,26 +773,25 @@
509
773
 
510
774
 	if (i2c_master_send(client, buf, len + 2) != len + 2)
511
775
 		return -EIO;
512
-
513
776
 	return 0;
514
777
 }
515
778
 
516
779
 static int ov7251_write_array(struct i2c_client *client,
517
-			      const struct regval *regs)
780
+			       const struct regval *regs)
518
781
 {
519
782
 	u32 i;
520
783
 	int ret = 0;
521
784
 
522
-	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
785
+	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
523
786
 		ret = ov7251_write_reg(client, regs[i].addr,
524
-				       OV7251_REG_VALUE_08BIT, regs[i].val);
525
-
787
+					OV7251_REG_VALUE_08BIT, regs[i].val);
788
+	}
526
789
 	return ret;
527
790
 }
528
791
 
529
792
 /* Read registers up to 4 at a time */
530
793
 static int ov7251_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
531
-			   u32 *val)
794
+			    u32 *val)
532
795
 {
533
796
 	struct i2c_msg msgs[2];
534
797
 	u8 *data_be_p;
..
..
@@ -561,8 +824,10 @@
561
824
 	return 0;
562
825
 }
563
826
 
827
+
828
+
564
829
 static int ov7251_get_reso_dist(const struct ov7251_mode *mode,
565
-				struct v4l2_mbus_framefmt *framefmt)
830
+				 struct v4l2_mbus_framefmt *framefmt)
566
831
 {
567
832
 	return abs(mode->width - framefmt->width) +
568
833
 	       abs(mode->height - framefmt->height);
..
..
@@ -575,7 +840,7 @@
575
840
 	int dist;
576
841
 	int cur_best_fit = 0;
577
842
 	int cur_best_fit_dist = -1;
578
-	size_t i;
843
+	unsigned int i;
579
844
 
580
845
 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
581
846
 		dist = ov7251_get_reso_dist(&supported_modes[i], framefmt);
..
..
@@ -589,8 +854,8 @@
589
854
 }
590
855
 
591
856
 static int ov7251_set_fmt(struct v4l2_subdev *sd,
592
-			  struct v4l2_subdev_pad_config *cfg,
593
-			  struct v4l2_subdev_format *fmt)
857
+			   struct v4l2_subdev_pad_config *cfg,
858
+			   struct v4l2_subdev_format *fmt)
594
859
 {
595
860
 	struct ov7251 *ov7251 = to_ov7251(sd);
596
861
 	const struct ov7251_mode *mode;
..
..
@@ -599,7 +864,7 @@
599
864
 	mutex_lock(&ov7251->mutex);
600
865
 
601
866
 	mode = ov7251_find_best_fit(fmt);
602
-	fmt->format.code = PIX_FORMAT;
867
+	fmt->format.code = mode->bus_fmt;
603
868
 	fmt->format.width = mode->width;
604
869
 	fmt->format.height = mode->height;
605
870
 	fmt->format.field = V4L2_FIELD_NONE;
..
..
@@ -619,6 +884,7 @@
619
884
 		__v4l2_ctrl_modify_range(ov7251->vblank, vblank_def,
620
885
 					 OV7251_VTS_MAX - mode->height,
621
886
 					 1, vblank_def);
887
+		ov7251->cur_fps = mode->max_fps;
622
888
 	}
623
889
 
624
890
 	mutex_unlock(&ov7251->mutex);
..
..
@@ -627,8 +893,8 @@
627
893
 }
628
894
 
629
895
 static int ov7251_get_fmt(struct v4l2_subdev *sd,
630
-			  struct v4l2_subdev_pad_config *cfg,
631
-			  struct v4l2_subdev_format *fmt)
896
+			   struct v4l2_subdev_pad_config *cfg,
897
+			   struct v4l2_subdev_format *fmt)
632
898
 {
633
899
 	struct ov7251 *ov7251 = to_ov7251(sd);
634
900
 	const struct ov7251_mode *mode = ov7251->cur_mode;
..
..
@@ -644,8 +910,13 @@
644
910
 	} else {
645
911
 		fmt->format.width = mode->width;
646
912
 		fmt->format.height = mode->height;
647
-		fmt->format.code = PIX_FORMAT;
913
+		fmt->format.code = mode->bus_fmt;
648
914
 		fmt->format.field = V4L2_FIELD_NONE;
915
+		/* format info: width/height/data type/virctual channel */
916
+		if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
917
+			fmt->reserved[0] = mode->vc[fmt->pad];
918
+		else
919
+			fmt->reserved[0] = mode->vc[PAD0];
649
920
 	}
650
921
 	mutex_unlock(&ov7251->mutex);
651
922
 
..
..
@@ -653,24 +924,26 @@
653
924
 }
654
925
 
655
926
 static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
656
-				 struct v4l2_subdev_pad_config *cfg,
657
-				 struct v4l2_subdev_mbus_code_enum *code)
927
+				  struct v4l2_subdev_pad_config *cfg,
928
+				  struct v4l2_subdev_mbus_code_enum *code)
658
929
 {
930
+	struct ov7251 *ov7251 = to_ov7251(sd);
931
+
659
932
 	if (code->index != 0)
660
933
 		return -EINVAL;
661
-	code->code = PIX_FORMAT;
934
+	code->code = ov7251->cur_mode->bus_fmt;
662
935
 
663
936
 	return 0;
664
937
 }
665
938
 
666
939
 static int ov7251_enum_frame_sizes(struct v4l2_subdev *sd,
667
-				   struct v4l2_subdev_pad_config *cfg,
668
-				   struct v4l2_subdev_frame_size_enum *fse)
940
+				    struct v4l2_subdev_pad_config *cfg,
941
+				    struct v4l2_subdev_frame_size_enum *fse)
669
942
 {
670
943
 	if (fse->index >= ARRAY_SIZE(supported_modes))
671
944
 		return -EINVAL;
672
945
 
673
-	if (fse->code != PIX_FORMAT)
946
+	if (fse->code != supported_modes[0].bus_fmt)
674
947
 		return -EINVAL;
675
948
 
676
949
 	fse->min_width  = supported_modes[fse->index].width;
..
..
@@ -695,20 +968,42 @@
695
968
 }
696
969
 
697
970
 static int ov7251_g_frame_interval(struct v4l2_subdev *sd,
698
-				   struct v4l2_subdev_frame_interval *fi)
971
+				    struct v4l2_subdev_frame_interval *fi)
699
972
 {
700
973
 	struct ov7251 *ov7251 = to_ov7251(sd);
701
974
 	const struct ov7251_mode *mode = ov7251->cur_mode;
702
975
 
703
-	mutex_lock(&ov7251->mutex);
704
-	fi->interval = mode->max_fps;
705
-	mutex_unlock(&ov7251->mutex);
976
+	if (ov7251->streaming)
977
+		fi->interval = ov7251->cur_fps;
978
+	else
979
+		fi->interval = mode->max_fps;
980
+
981
+	return 0;
982
+}
983
+
984
+static int ov7251_g_mbus_config(struct v4l2_subdev *sd,
985
+				unsigned int pad_id,
986
+				struct v4l2_mbus_config *config)
987
+{
988
+	struct ov7251 *ov7251 = to_ov7251(sd);
989
+	const struct ov7251_mode *mode = ov7251->cur_mode;
990
+	u32 val = 1 << (OV7251_LANES - 1) |
991
+		V4L2_MBUS_CSI2_CHANNEL_0 |
992
+		V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
993
+
994
+	if (mode->hdr_mode != NO_HDR)
995
+		val |= V4L2_MBUS_CSI2_CHANNEL_1;
996
+	if (mode->hdr_mode == HDR_X3)
997
+		val |= V4L2_MBUS_CSI2_CHANNEL_2;
998
+
999
+	config->type = V4L2_MBUS_CSI2_DPHY;
1000
+	config->flags = val;
706
1001
 
707
1002
 	return 0;
708
1003
 }
709
1004
 
710
1005
 static void ov7251_get_module_inf(struct ov7251 *ov7251,
711
-				  struct rkmodule_inf *inf)
1006
+				   struct rkmodule_inf *inf)
712
1007
 {
713
1008
 	memset(inf, 0, sizeof(*inf));
714
1009
 	strscpy(inf->base.sensor, OV7251_NAME, sizeof(inf->base.sensor));
..
..
@@ -721,6 +1016,7 @@
721
1016
 {
722
1017
 	struct ov7251 *ov7251 = to_ov7251(sd);
723
1018
 	struct rkmodule_hdr_cfg *hdr;
1019
+	u32 i, h, w;
724
1020
 	long ret = 0;
725
1021
 	u32 stream = 0;
726
1022
 
..
..
@@ -735,20 +1031,44 @@
735
1031
 		break;
736
1032
 	case RKMODULE_SET_HDR_CFG:
737
1033
 		hdr = (struct rkmodule_hdr_cfg *)arg;
738
-		if (hdr->hdr_mode != 0)
739
-			ret = -1;
1034
+		w = ov7251->cur_mode->width;
1035
+		h = ov7251->cur_mode->height;
1036
+		for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1037
+			if (w == supported_modes[i].width &&
1038
+			    h == supported_modes[i].height &&
1039
+			    supported_modes[i].hdr_mode == hdr->hdr_mode) {
1040
+				ov7251->cur_mode = &supported_modes[i];
1041
+				break;
1042
+			}
1043
+		}
1044
+		if (i == ARRAY_SIZE(supported_modes)) {
1045
+			dev_err(&ov7251->client->dev,
1046
+				"not find hdr mode:%d %dx%d config\n",
1047
+				hdr->hdr_mode, w, h);
1048
+			ret = -EINVAL;
1049
+		} else {
1050
+			w = ov7251->cur_mode->hts_def - ov7251->cur_mode->width;
1051
+			h = ov7251->cur_mode->vts_def - ov7251->cur_mode->height;
1052
+			__v4l2_ctrl_modify_range(ov7251->hblank, w, w, 1, w);
1053
+			__v4l2_ctrl_modify_range(ov7251->vblank, h,
1054
+						 OV7251_VTS_MAX - ov7251->cur_mode->height, 1, h);
1055
+		}
1056
+		break;
1057
+	case PREISP_CMD_SET_HDRAE_EXP:
740
1058
 		break;
741
1059
 	case RKMODULE_SET_QUICK_STREAM:
1060
+
742
1061
 		stream = *((u32 *)arg);
1062
+
743
1063
 		if (stream)
744
1064
 			ret = ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
745
-				OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
1065
+				 OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
746
1066
 		else
747
1067
 			ret = ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
748
-				OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
1068
+				 OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
749
1069
 		break;
750
1070
 	default:
751
-		ret = -ENOTTY;
1071
+		ret = -ENOIOCTLCMD;
752
1072
 		break;
753
1073
 	}
754
1074
 
..
..
@@ -757,11 +1077,12 @@
757
1077
 
758
1078
 #ifdef CONFIG_COMPAT
759
1079
 static long ov7251_compat_ioctl32(struct v4l2_subdev *sd,
760
-				  unsigned int cmd, unsigned long arg)
1080
+				   unsigned int cmd, unsigned long arg)
761
1081
 {
762
1082
 	void __user *up = compat_ptr(arg);
763
1083
 	struct rkmodule_inf *inf;
764
1084
 	struct rkmodule_hdr_cfg *hdr;
1085
+	struct preisp_hdrae_exp_s *hdrae;
765
1086
 	long ret;
766
1087
 	u32 stream = 0;
767
1088
 
..
..
@@ -775,8 +1096,7 @@
775
1096
 
776
1097
 		ret = ov7251_ioctl(sd, cmd, inf);
777
1098
 		if (!ret) {
778
-			ret = copy_to_user(up, inf, sizeof(*inf));
779
-			if (ret)
1099
+			if (copy_to_user(up, inf, sizeof(*inf)))
780
1100
 				ret = -EFAULT;
781
1101
 		}
782
1102
 		kfree(inf);
..
..
@@ -790,8 +1110,7 @@
790
1110
 
791
1111
 		ret = ov7251_ioctl(sd, cmd, hdr);
792
1112
 		if (!ret) {
793
-			ret = copy_to_user(up, hdr, sizeof(*hdr));
794
-			if (ret)
1113
+			if (copy_to_user(up, hdr, sizeof(*hdr)))
795
1114
 				ret = -EFAULT;
796
1115
 		}
797
1116
 		kfree(hdr);
..
..
@@ -803,19 +1122,33 @@
803
1122
 			return ret;
804
1123
 		}
805
1124
 
806
-		if (copy_from_user(hdr, up, sizeof(*hdr))) {
807
-			kfree(hdr);
808
-			return -EFAULT;
809
-		}
810
-
811
-		ret = ov7251_ioctl(sd, cmd, hdr);
1125
+		ret = copy_from_user(hdr, up, sizeof(*hdr));
1126
+		if (!ret)
1127
+			ret = ov7251_ioctl(sd, cmd, hdr);
1128
+		else
1129
+			ret = -EFAULT;
812
1130
 		kfree(hdr);
813
1131
 		break;
814
-	case RKMODULE_SET_QUICK_STREAM:
815
-		if (copy_from_user(&stream, up, sizeof(u32)))
816
-			return -EFAULT;
1132
+	case PREISP_CMD_SET_HDRAE_EXP:
1133
+		hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1134
+		if (!hdrae) {
1135
+			ret = -ENOMEM;
1136
+			return ret;
1137
+		}
817
1138
 
818
-		ret = ov7251_ioctl(sd, cmd, &stream);
1139
+		ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1140
+		if (!ret)
1141
+			ret = ov7251_ioctl(sd, cmd, hdrae);
1142
+		else
1143
+			ret = -EFAULT;
1144
+		kfree(hdrae);
1145
+		break;
1146
+	case RKMODULE_SET_QUICK_STREAM:
1147
+		ret = copy_from_user(&stream, up, sizeof(u32));
1148
+		if (!ret)
1149
+			ret = ov7251_ioctl(sd, cmd, &stream);
1150
+		else
1151
+			ret = -EFAULT;
819
1152
 		break;
820
1153
 	default:
821
1154
 		ret = -ENOIOCTLCMD;
..
..
@@ -835,20 +1168,18 @@
835
1168
 		return ret;
836
1169
 
837
1170
 	/* In case these controls are set before streaming */
838
-	mutex_unlock(&ov7251->mutex);
839
-	ret = v4l2_ctrl_handler_setup(&ov7251->ctrl_handler);
840
-	mutex_lock(&ov7251->mutex);
1171
+	ret = __v4l2_ctrl_handler_setup(&ov7251->ctrl_handler);
841
1172
 	if (ret)
842
1173
 		return ret;
843
1174
 
844
1175
 	return ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
845
-				OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
1176
+				 OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
846
1177
 }
847
1178
 
848
1179
 static int __ov7251_stop_stream(struct ov7251 *ov7251)
849
1180
 {
850
1181
 	return ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
851
-				OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
1182
+				 OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
852
1183
 }
853
1184
 
854
1185
 static int ov7251_s_stream(struct v4l2_subdev *sd, int on)
..
..
@@ -868,6 +1199,7 @@
868
1199
 			pm_runtime_put_noidle(&client->dev);
869
1200
 			goto unlock_and_return;
870
1201
 		}
1202
+
871
1203
 		ret = __ov7251_start_stream(ov7251);
872
1204
 		if (ret) {
873
1205
 			v4l2_err(sd, "start stream failed while write regs\n");
..
..
@@ -907,6 +1239,13 @@
907
1239
 			goto unlock_and_return;
908
1240
 		}
909
1241
 
1242
+		ret = ov7251_write_array(ov7251->client, ov7251_global_regs);
1243
+		if (ret) {
1244
+			v4l2_err(sd, "could not set init registers\n");
1245
+			pm_runtime_put_noidle(&client->dev);
1246
+			goto unlock_and_return;
1247
+		}
1248
+
910
1249
 		ov7251->power_on = true;
911
1250
 	} else {
912
1251
 		pm_runtime_put(&client->dev);
..
..
@@ -937,12 +1276,11 @@
937
1276
 		if (ret < 0)
938
1277
 			dev_err(dev, "could not set pins\n");
939
1278
 	}
940
-
941
1279
 	ret = clk_set_rate(ov7251->xvclk, OV7251_XVCLK_FREQ);
942
1280
 	if (ret < 0)
943
-		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1281
+		dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
944
1282
 	if (clk_get_rate(ov7251->xvclk) != OV7251_XVCLK_FREQ)
945
-		dev_err(dev, "xvclk mismatched, modes are based on 24MHz\n");
1283
+		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
946
1284
 	ret = clk_prepare_enable(ov7251->xvclk);
947
1285
 	if (ret < 0) {
948
1286
 		dev_err(dev, "Failed to enable xvclk\n");
..
..
@@ -950,7 +1288,7 @@
950
1288
 	}
951
1289
 
952
1290
 	if (!IS_ERR(ov7251->reset_gpio))
953
-		gpiod_set_value_cansleep(ov7251->reset_gpio, 1);
1291
+		gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
954
1292
 
955
1293
 	ret = regulator_bulk_enable(OV7251_NUM_SUPPLIES, ov7251->supplies);
956
1294
 	if (ret < 0) {
..
..
@@ -958,13 +1296,18 @@
958
1296
 		goto disable_clk;
959
1297
 	}
960
1298
 
961
-	usleep_range(1000, 1100);
962
-
1299
+	usleep_range(5 * 1000, 10 * 1000);
963
1300
 	if (!IS_ERR(ov7251->reset_gpio))
964
-		gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
1301
+		gpiod_set_value_cansleep(ov7251->reset_gpio, 1);
965
1302
 
1303
+	usleep_range(500, 1000);
966
1304
 	if (!IS_ERR(ov7251->pwdn_gpio))
967
1305
 		gpiod_set_value_cansleep(ov7251->pwdn_gpio, 1);
1306
+
1307
+	if (!IS_ERR(ov7251->reset_gpio))
1308
+		usleep_range(6000, 8000);
1309
+	else
1310
+		usleep_range(12000, 16000);
968
1311
 
969
1312
 	/* 8192 cycles prior to first SCCB transaction */
970
1313
 	delay_us = ov7251_cal_delay(8192);
..
..
@@ -975,9 +1318,6 @@
975
1318
 disable_clk:
976
1319
 	clk_disable_unprepare(ov7251->xvclk);
977
1320
 
978
-	if (!IS_ERR_OR_NULL(ov7251->pins_sleep))
979
-		pinctrl_select_state(ov7251->pinctrl, ov7251->pins_sleep);
980
-
981
1321
 	return ret;
982
1322
 }
983
1323
 
..
..
@@ -986,17 +1326,17 @@
986
1326
 	int ret;
987
1327
 	struct device *dev = &ov7251->client->dev;
988
1328
 
1329
+	if (!IS_ERR(ov7251->pwdn_gpio))
1330
+		gpiod_set_value_cansleep(ov7251->pwdn_gpio, 0);
1331
+	clk_disable_unprepare(ov7251->xvclk);
1332
+	if (!IS_ERR(ov7251->reset_gpio))
1333
+		gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
989
1334
 	if (!IS_ERR_OR_NULL(ov7251->pins_sleep)) {
990
1335
 		ret = pinctrl_select_state(ov7251->pinctrl,
991
1336
 					   ov7251->pins_sleep);
992
1337
 		if (ret < 0)
993
1338
 			dev_dbg(dev, "could not set pins\n");
994
1339
 	}
995
-	if (!IS_ERR(ov7251->pwdn_gpio))
996
-		gpiod_set_value_cansleep(ov7251->pwdn_gpio, 0);
997
-	clk_disable_unprepare(ov7251->xvclk);
998
-	if (!IS_ERR(ov7251->reset_gpio))
999
-		gpiod_set_value_cansleep(ov7251->reset_gpio, 1);
1000
1340
 	regulator_bulk_disable(OV7251_NUM_SUPPLIES, ov7251->supplies);
1001
1341
 }
1002
1342
 
..
..
@@ -1032,7 +1372,7 @@
1032
1372
 	/* Initialize try_fmt */
1033
1373
 	try_fmt->width = def_mode->width;
1034
1374
 	try_fmt->height = def_mode->height;
1035
-	try_fmt->code = PIX_FORMAT;
1375
+	try_fmt->code = def_mode->bus_fmt;
1036
1376
 	try_fmt->field = V4L2_FIELD_NONE;
1037
1377
 
1038
1378
 	mutex_unlock(&ov7251->mutex);
..
..
@@ -1049,56 +1389,12 @@
1049
1389
 	if (fie->index >= ARRAY_SIZE(supported_modes))
1050
1390
 		return -EINVAL;
1051
1391
 
1052
-	if (fie->code != PIX_FORMAT)
1053
-		return -EINVAL;
1054
-
1392
+	fie->code = supported_modes[fie->index].bus_fmt;
1055
1393
 	fie->width = supported_modes[fie->index].width;
1056
1394
 	fie->height = supported_modes[fie->index].height;
1057
1395
 	fie->interval = supported_modes[fie->index].max_fps;
1396
+	fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1058
1397
 	return 0;
1059
-}
1060
-
1061
-static int ov7251_g_mbus_config(struct v4l2_subdev *sd,
1062
-				struct v4l2_mbus_config *config)
1063
-{
1064
-	u32 val = 0;
1065
-
1066
-	val = 1 << (OV7251_LANES - 1) |
1067
-	      V4L2_MBUS_CSI2_CHANNEL_0 |
1068
-	      V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1069
-	config->type = V4L2_MBUS_CSI2;
1070
-	config->flags = val;
1071
-
1072
-	return 0;
1073
-}
1074
-
1075
-#define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1076
-#define DST_WIDTH 640
1077
-#define DST_HEIGHT 480
1078
-
1079
-/*
1080
- * The resolution of the driver configuration needs to be exactly
1081
- * the same as the current output resolution of the sensor,
1082
- * the input width of the isp needs to be 16 aligned,
1083
- * the input height of the isp needs to be 8 aligned.
1084
- * Can be cropped to standard resolution by this function,
1085
- * otherwise it will crop out strange resolution according
1086
- * to the alignment rules.
1087
- */
1088
-static int ov7251_get_selection(struct v4l2_subdev *sd,
1089
-				struct v4l2_subdev_pad_config *cfg,
1090
-				struct v4l2_subdev_selection *sel)
1091
-{
1092
-	struct ov7251 *ov7251 = to_ov7251(sd);
1093
-
1094
-	if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1095
-		sel->r.left = CROP_START(ov7251->cur_mode->width, DST_WIDTH);
1096
-		sel->r.width = DST_WIDTH;
1097
-		sel->r.top = CROP_START(ov7251->cur_mode->height, DST_HEIGHT);
1098
-		sel->r.height = DST_HEIGHT;
1099
-		return 0;
1100
-	}
1101
-	return -EINVAL;
1102
1398
 }
1103
1399
 
1104
1400
 static const struct dev_pm_ops ov7251_pm_ops = {
..
..
@@ -1123,7 +1419,6 @@
1123
1419
 static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1124
1420
 	.s_stream = ov7251_s_stream,
1125
1421
 	.g_frame_interval = ov7251_g_frame_interval,
1126
-	.g_mbus_config = ov7251_g_mbus_config,
1127
1422
 };
1128
1423
 
1129
1424
 static const struct v4l2_subdev_pad_ops ov7251_pad_ops = {
..
..
@@ -1132,7 +1427,7 @@
1132
1427
 	.enum_frame_interval = ov7251_enum_frame_interval,
1133
1428
 	.get_fmt = ov7251_get_fmt,
1134
1429
 	.set_fmt = ov7251_set_fmt,
1135
-	.get_selection = ov7251_get_selection,
1430
+	.get_mbus_config = ov7251_g_mbus_config,
1136
1431
 };
1137
1432
 
1138
1433
 static const struct v4l2_subdev_ops ov7251_subdev_ops = {
..
..
@@ -1144,10 +1439,11 @@
1144
1439
 static int ov7251_set_ctrl(struct v4l2_ctrl *ctrl)
1145
1440
 {
1146
1441
 	struct ov7251 *ov7251 = container_of(ctrl->handler,
1147
-					     struct ov7251, ctrl_handler);
1442
+					       struct ov7251, ctrl_handler);
1148
1443
 	struct i2c_client *client = ov7251->client;
1149
1444
 	s64 max;
1150
1445
 	int ret = 0;
1446
+	u32 val = 0;
1151
1447
 
1152
1448
 	/* Propagate change of current control to all related controls */
1153
1449
 	switch (ctrl->id) {
..
..
@@ -1183,6 +1479,21 @@
1183
1479
 	case V4L2_CID_TEST_PATTERN:
1184
1480
 		ret = ov7251_enable_test_pattern(ov7251, ctrl->val);
1185
1481
 		break;
1482
+	case V4L2_CID_HFLIP:
1483
+		ret = ov7251_read_reg(ov7251->client, OV7251_MIRROR_REG,
1484
+				       OV7251_REG_VALUE_08BIT, &val);
1485
+		ret |= ov7251_write_reg(ov7251->client, OV7251_MIRROR_REG,
1486
+					 OV7251_REG_VALUE_08BIT,
1487
+					 OV7251_FETCH_MIRROR(val, ctrl->val));
1488
+		break;
1489
+	case V4L2_CID_VFLIP:
1490
+		ret = ov7251_read_reg(ov7251->client, OV7251_FLIP_REG,
1491
+				       OV7251_REG_VALUE_08BIT, &val);
1492
+		ret |= ov7251_write_reg(ov7251->client, OV7251_FLIP_REG,
1493
+					 OV7251_REG_VALUE_08BIT,
1494
+					 OV7251_FETCH_FLIP(val, ctrl->val));
1495
+		break;
1496
+
1186
1497
 	default:
1187
1498
 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1188
1499
 			 __func__, ctrl->id, ctrl->val);
..
..
@@ -1209,7 +1520,7 @@
1209
1520
 
1210
1521
 	handler = &ov7251->ctrl_handler;
1211
1522
 	mode = ov7251->cur_mode;
1212
-	ret = v4l2_ctrl_handler_init(handler, 8);
1523
+	ret = v4l2_ctrl_handler_init(handler, 9);
1213
1524
 	if (ret)
1214
1525
 		return ret;
1215
1526
 	handler->lock = &ov7251->mutex;
..
..
@@ -1220,36 +1531,38 @@
1220
1531
 		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1221
1532
 
1222
1533
 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1223
-			  0, OV7251_PIXEL_RATE, 1, OV7251_PIXEL_RATE);
1534
+			  0, PIXEL_RATE_WITH_240M_10BIT, 1, PIXEL_RATE_WITH_240M_10BIT);
1224
1535
 
1225
1536
 	h_blank = mode->hts_def - mode->width;
1226
1537
 	ov7251->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1227
-				h_blank, h_blank, 1, h_blank);
1538
+					    h_blank, h_blank, 1, h_blank);
1228
1539
 	if (ov7251->hblank)
1229
1540
 		ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1230
-
1231
1541
 	vblank_def = mode->vts_def - mode->height;
1232
1542
 	ov7251->vblank = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1233
-				V4L2_CID_VBLANK, vblank_def,
1234
-				OV7251_VTS_MAX - mode->height,
1235
-				1, vblank_def);
1236
-
1543
+					    V4L2_CID_VBLANK, vblank_def,
1544
+					    OV7251_VTS_MAX - mode->height,
1545
+					    1, vblank_def);
1546
+	ov7251->cur_fps = mode->max_fps;
1237
1547
 	exposure_max = mode->vts_def - 20;
1238
1548
 	ov7251->exposure = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1239
-				V4L2_CID_EXPOSURE, OV7251_EXPOSURE_MIN,
1240
-				exposure_max, OV7251_EXPOSURE_STEP,
1241
-				mode->exp_def);
1242
-
1549
+					      V4L2_CID_EXPOSURE, OV7251_EXPOSURE_MIN,
1550
+					      exposure_max, OV7251_EXPOSURE_STEP,
1551
+					      mode->exp_def);
1243
1552
 	ov7251->anal_gain = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1244
1553
 				V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1245
1554
 				ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1246
1555
 				ANALOG_GAIN_DEFAULT);
1247
1556
 
1248
1557
 	ov7251->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1249
-				&ov7251_ctrl_ops, V4L2_CID_TEST_PATTERN,
1250
-				ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1251
-				0, 0, ov7251_test_pattern_menu);
1252
-
1558
+							    &ov7251_ctrl_ops,
1559
+					V4L2_CID_TEST_PATTERN,
1560
+					ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1561
+					0, 0, ov7251_test_pattern_menu);
1562
+	v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1563
+				V4L2_CID_HFLIP, 0, 1, 1, 0);
1564
+	v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1565
+				V4L2_CID_VFLIP, 0, 1, 1, 0);
1253
1566
 	if (handler->error) {
1254
1567
 		ret = handler->error;
1255
1568
 		dev_err(&ov7251->client->dev,
..
..
@@ -1268,14 +1581,14 @@
1268
1581
 }
1269
1582
 
1270
1583
 static int ov7251_check_sensor_id(struct ov7251 *ov7251,
1271
-				  struct i2c_client *client)
1584
+				   struct i2c_client *client)
1272
1585
 {
1273
1586
 	struct device *dev = &ov7251->client->dev;
1274
1587
 	u32 id = 0;
1275
1588
 	int ret;
1276
1589
 
1277
1590
 	ret = ov7251_read_reg(client, OV7251_REG_CHIP_ID,
1278
-			      OV7251_REG_VALUE_16BIT, &id);
1591
+			       OV7251_REG_VALUE_08BIT, &id);
1279
1592
 	if (id != CHIP_ID) {
1280
1593
 		dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1281
1594
 		return -ENODEV;
..
..
@@ -1288,7 +1601,7 @@
1288
1601
 
1289
1602
 static int ov7251_configure_regulators(struct ov7251 *ov7251)
1290
1603
 {
1291
-	size_t i;
1604
+	unsigned int i;
1292
1605
 
1293
1606
 	for (i = 0; i < OV7251_NUM_SUPPLIES; i++)
1294
1607
 		ov7251->supplies[i].supply = ov7251_supply_names[i];
..
..
@@ -1299,7 +1612,7 @@
1299
1612
 }
1300
1613
 
1301
1614
 static int ov7251_probe(struct i2c_client *client,
1302
-			const struct i2c_device_id *id)
1615
+			 const struct i2c_device_id *id)
1303
1616
 {
1304
1617
 	struct device *dev = &client->dev;
1305
1618
 	struct device_node *node = dev->of_node;
..
..
@@ -1309,9 +1622,9 @@
1309
1622
 	int ret;
1310
1623
 
1311
1624
 	dev_info(dev, "driver version: %02x.%02x.%02x",
1312
-		DRIVER_VERSION >> 16,
1313
-		(DRIVER_VERSION & 0xff00) >> 8,
1314
-		DRIVER_VERSION & 0x00ff);
1625
+		 DRIVER_VERSION >> 16,
1626
+		 (DRIVER_VERSION & 0xff00) >> 8,
1627
+		 DRIVER_VERSION & 0x00ff);
1315
1628
 
1316
1629
 	ov7251 = devm_kzalloc(dev, sizeof(*ov7251), GFP_KERNEL);
1317
1630
 	if (!ov7251)
..
..
@@ -1347,27 +1660,29 @@
1347
1660
 	if (IS_ERR(ov7251->pwdn_gpio))
1348
1661
 		dev_warn(dev, "Failed to get pwdn-gpios\n");
1349
1662
 
1350
-	ret = ov7251_configure_regulators(ov7251);
1351
-	if (ret) {
1352
-		dev_err(dev, "Failed to get power regulators\n");
1353
-		return ret;
1354
-	}
1355
1663
 	ov7251->pinctrl = devm_pinctrl_get(dev);
1356
1664
 	if (!IS_ERR(ov7251->pinctrl)) {
1357
1665
 		ov7251->pins_default =
1358
1666
 			pinctrl_lookup_state(ov7251->pinctrl,
1359
1667
 					     OF_CAMERA_PINCTRL_STATE_DEFAULT);
1360
1668
 		if (IS_ERR(ov7251->pins_default))
1361
-			dev_info(dev, "could not get default pinstate\n");
1669
+			dev_err(dev, "could not get default pinstate\n");
1362
1670
 
1363
1671
 		ov7251->pins_sleep =
1364
1672
 			pinctrl_lookup_state(ov7251->pinctrl,
1365
1673
 					     OF_CAMERA_PINCTRL_STATE_SLEEP);
1366
1674
 		if (IS_ERR(ov7251->pins_sleep))
1367
-			dev_info(dev, "could not get sleep pinstate\n");
1675
+			dev_err(dev, "could not get sleep pinstate\n");
1368
1676
 	} else {
1369
-		dev_info(dev, "no pinctrl\n");
1677
+		dev_err(dev, "no pinctrl\n");
1370
1678
 	}
1679
+
1680
+	ret = ov7251_configure_regulators(ov7251);
1681
+	if (ret) {
1682
+		dev_err(dev, "Failed to get power regulators\n");
1683
+		return ret;
1684
+	}
1685
+
1371
1686
 	mutex_init(&ov7251->mutex);
1372
1687
 
1373
1688
 	sd = &ov7251->subdev;