update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/i2c/maxim4c/maxim4c_mipi_txphy.c
..
..
@@ -11,6 +11,82 @@
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11
 
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 #include "maxim4c_api.h"
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13
 
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+static int maxim4c_txphy_init_timing(maxim4c_t *maxim4c)
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+{
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+	struct i2c_client *client = maxim4c->client;
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+	int ret = 0;
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+	u16 reg_addr = 0;
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+	u8 reg_mask;
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+	u8 timing;
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+	u8 phy_idx = 0;
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+
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+	if (!maxim4c->mipi_txphy.timing_override_en)
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+		return 0;
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+
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+	timing = ((maxim4c->mipi_txphy.timing.t_hs_przero & 0x3) << 6 |
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+		  (maxim4c->mipi_txphy.timing.t_hs_prep & 0x3) << 4 |
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+		  (maxim4c->mipi_txphy.timing.t_clk_trail & 0x3) << 2 |
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+		  (maxim4c->mipi_txphy.timing.t_clk_przero & 0x3) << 0);
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+
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+	ret |= maxim4c_i2c_write_byte(client, 0x08A1,
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+				      MAXIM4C_I2C_REG_ADDR_16BITS, timing);
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+
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+	reg_mask = 0x0F;
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+	timing = ((maxim4c->mipi_txphy.timing.t_lpx & 0x3) << 2 |
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+		  (maxim4c->mipi_txphy.timing.t_hs_trail & 0x3) << 0);
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+
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+	ret |= maxim4c_i2c_update_byte(
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+		client, 0x08A2, MAXIM4C_I2C_REG_ADDR_16BITS, reg_mask, timing);
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+
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+	reg_mask = (0x3 << 6);
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+	timing = (maxim4c->mipi_txphy.timing.t_lpxesc & 0x3) << 6;
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+	ret |= maxim4c_i2c_update_byte(
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+		client, 0x08A5, MAXIM4C_I2C_REG_ADDR_16BITS, reg_mask, timing);
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+
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+	reg_mask = (0x7 << 5);
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+	timing = (maxim4c->mipi_txphy.timing.t_lpxesc & 0x7) << 5;
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+	ret |= maxim4c_i2c_update_byte(
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+		client, 0x08A8, MAXIM4C_I2C_REG_ADDR_16BITS, reg_mask, timing);
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+
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+	for (phy_idx = 0; phy_idx < MAXIM4C_TXPHY_ID_MAX; phy_idx++) {
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+		reg_mask = 0xFF;
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+		reg_addr = 0x0905 + 0x40 * phy_idx;
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+		timing = maxim4c->mipi_txphy.timing.csi2_t_pre;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       reg_mask, timing);
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+
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+		reg_addr = 0x0906 + 0x40 * phy_idx;
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+		timing = maxim4c->mipi_txphy.timing.csi2_t_post;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       reg_mask, timing);
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+
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+		reg_addr = 0x0907 + 0x40 * phy_idx;
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+		timing = maxim4c->mipi_txphy.timing.csi2_tx_gap;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       reg_mask, timing);
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+
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+		reg_addr = 0x0908 + 0x40 * phy_idx;
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+		timing = maxim4c->mipi_txphy.timing.csi2_twakeup & 0xFF;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       reg_mask, timing);
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+		timing = (maxim4c->mipi_txphy.timing.csi2_twakeup >> 8) & 0xFF;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr + 1,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       reg_mask, timing);
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+		reg_mask = 0x7;
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+		timing = (maxim4c->mipi_txphy.timing.csi2_twakeup >> 16) & 0x7;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr + 2,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       reg_mask, timing);
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+	}
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+
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+	return ret;
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+}
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+
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 static int maxim4c_txphy_auto_init_deskew(maxim4c_t *maxim4c)
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 {
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 	struct i2c_client *client = maxim4c->client;
..
..
@@ -182,6 +258,11 @@
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 				reg_addr, MAXIM4C_I2C_REG_ADDR_16BITS,
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 				0xf4);
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+		reg_addr = 0x1C03 + 0x100 * phy_idx;
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+		ret |= maxim4c_i2c_update_byte(client, reg_addr,
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+					       MAXIM4C_I2C_REG_ADDR_16BITS,
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+					       0x07, phy_cfg->ssc_ratio);
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+
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 		// Set dpll data rate
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 		reg_addr = 0x0415 + 0x03 * phy_idx;
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 		ret |= maxim4c_i2c_update_byte(client,
..
..
@@ -349,6 +430,12 @@
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 				phy_cfg->clock_mode = value;
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 			}
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+			ret = of_property_read_u32(node, "ssc-ratio", &value);
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+			if (ret == 0) {
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+				dev_info(dev, "ssc-ratio property: %d", value);
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+				phy_cfg->ssc_ratio = value;
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+			}
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+
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 			sub_idx++;
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 		}
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 	}
..
..
@@ -510,6 +597,9 @@
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 	// mipi txphy auto init deskew
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 	ret |= maxim4c_txphy_auto_init_deskew(maxim4c);
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+	// mipi txphy timing init
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+	ret |= maxim4c_txphy_init_timing(maxim4c);
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+
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 	if (ret) {
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 		dev_err(dev, "%s: txphy hw init error\n", __func__);
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 		return ret;
..
..
@@ -529,6 +619,11 @@
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 	mipi_txphy->force_clock_out_en = 1;
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 	mipi_txphy->force_clk0_en = 0;
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 	mipi_txphy->force_clk3_en = 0;
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+	mipi_txphy->timing.t_lpx = 1;
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+	mipi_txphy->timing.csi2_t_pre = 0x71;
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+	mipi_txphy->timing.csi2_t_post = 0x19;
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+	mipi_txphy->timing.csi2_tx_gap = 0x1C;
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+	mipi_txphy->timing.csi2_twakeup = 0x100;
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 	for (i = 0; i < MAXIM4C_TXPHY_ID_MAX; i++) {
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 		phy_cfg = &mipi_txphy->phy_cfg[i];
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@@ -541,6 +636,7 @@
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 		phy_cfg->vc_ext_en = 0;
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 		phy_cfg->clock_master = 0;
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 		phy_cfg->clock_mode = MAXIM4C_TXPHY_DPLL_PREDEF;
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+		phy_cfg->ssc_ratio = 0;
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 	}
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 }
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 EXPORT_SYMBOL(maxim4c_mipi_txphy_data_init);