forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/media/i2c/max96712.c
....@@ -17,6 +17,7 @@
1717  *         support for GMSL1 Link.
1818  * V1.5.00 only check max96712 chipid when probe.
1919  *         enable stream out if not all link are locked.
20
+ * V1.6.00 serdes read /write api depend on i2c id index.
2021  *
2122  */
2223 
....@@ -45,7 +46,7 @@
4546 #include <media/v4l2-fwnode.h>
4647 #include <media/v4l2-subdev.h>
4748 
48
-#define DRIVER_VERSION			KERNEL_VERSION(1, 0x05, 0x00)
49
+#define DRIVER_VERSION			KERNEL_VERSION(1, 0x06, 0x00)
4950 
5051 #ifndef V4L2_CID_DIGITAL_GAIN
5152 #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
....@@ -63,48 +64,48 @@
6364 #define MAX96717_CHIP_ID		0xBF
6465 #define MAX96717_REG_CHIP_ID		0x0D
6566 
66
-#define MAX96712_REMOTE_CTRL		0x0003
67
-#define MAX96712_REMOTE_DISABLE		0xFF
68
-
6967 /* max96712->link mask: link type = bit[7:4], link mask = bit[3:0] */
70
-#define MAX96712_GMSL_TYPE_LINK_A	BIT(4)
71
-#define MAX96712_GMSL_TYPE_LINK_B	BIT(5)
72
-#define MAX96712_GMSL_TYPE_LINK_C	BIT(6)
73
-#define MAX96712_GMSL_TYPE_LINK_D	BIT(7)
74
-#define MAX96712_GMSL_TYPE_MASK		0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */
68
+#define MAXIM_GMSL_TYPE_LINK_A		BIT(4)
69
+#define MAXIM_GMSL_TYPE_LINK_B		BIT(5)
70
+#define MAXIM_GMSL_TYPE_LINK_C		BIT(6)
71
+#define MAXIM_GMSL_TYPE_LINK_D		BIT(7)
72
+#define MAXIM_GMSL_TYPE_MASK		0xF0 /* bit[7:4], GMSL link type: 0 = GMSL1, 1 = GMSL2 */
7573 
76
-#define MAX96712_LOCK_STATE_LINK_A	BIT(0)
77
-#define MAX96712_LOCK_STATE_LINK_B	BIT(1)
78
-#define MAX96712_LOCK_STATE_LINK_C	BIT(2)
79
-#define MAX96712_LOCK_STATE_LINK_D	BIT(3)
80
-#define MAX96712_LOCK_STATE_MASK	0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */
74
+#define MAXIM_GMSL_LOCK_LINK_A		BIT(0)
75
+#define MAXIM_GMSL_LOCK_LINK_B		BIT(1)
76
+#define MAXIM_GMSL_LOCK_LINK_C		BIT(2)
77
+#define MAXIM_GMSL_LOCK_LINK_D		BIT(3)
78
+#define MAXIM_GMSL_LOCK_MASK		0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */
8179 
82
-#define MAX96712_FORCE_ALL_CLOCK_EN	1 /* 1: enable, 0: disable */
83
-
84
-#define REG_NULL			0xFFFF
80
+#define MAXIM_FORCE_ALL_CLOCK_EN	1 /* 1: enable, 0: disable */
8581 
8682 #define OF_CAMERA_PINCTRL_STATE_DEFAULT	"rockchip,camera_default"
8783 #define OF_CAMERA_PINCTRL_STATE_SLEEP	"rockchip,camera_sleep"
8884 
8985 #define MAX96712_NAME			"max96712"
9086 
87
+#define REG_NULL			0xFFFF
88
+
9189 /* register length: 8bit or 16bit */
92
-#define MAX96712_REG_LENGTH_08BIT	1
93
-#define MAX96712_REG_LENGTH_16BIT	2
90
+#define DEV_REG_LENGTH_08BITS		1
91
+#define DEV_REG_LENGTH_16BITS		2
9492 
9593 /* register value: 8bit or 16bit or 24bit */
96
-#define MAX96712_REG_VALUE_08BIT	1
97
-#define MAX96712_REG_VALUE_16BIT	2
98
-#define MAX96712_REG_VALUE_24BIT	3
94
+#define DEV_REG_VALUE_08BITS		1
95
+#define DEV_REG_VALUE_16BITS		2
96
+#define DEV_REG_VALUE_24BITS		3
9997 
100
-#define MAX96712_I2C_ADDR		(0x29)
101
-#define MAX96715_I2C_ADDR		(0x40)
102
-#define MAX96717_I2C_ADDR		(0x40)
103
-#define CAMERA_I2C_ADDR			(0x30)
98
+/* i2c device default address */
99
+#define SER_I2C_ADDR			(0x40)
100
+#define CAM_I2C_ADDR			(0x30)
104101 
105
-#define MAX96712_GET_BIT(x, bit)	((x & (1 << bit)) >> bit)
106
-#define MAX96712_GET_BIT_M_TO_N(x, m, n)	\
107
-		((unsigned int)(x << (31 - (n))) >> ((31 - (n)) + (m)))
102
+/* Maxim Serdes I2C Device ID */
103
+enum {
104
+	I2C_DEV_DES = 0,
105
+	I2C_DEV_SER,
106
+	I2C_DEV_CAM,
107
+	I2C_DEV_MAX
108
+};
108109 
109110 enum max96712_rx_rate {
110111 	MAX96712_RX_RATE_3GBPS = 0,
....@@ -120,7 +121,7 @@
120121 #define MAX96712_NUM_SUPPLIES		ARRAY_SIZE(max96712_supply_names)
121122 
122123 struct regval {
123
-	u16 i2c_addr;
124
+	u16 i2c_id;
124125 	u16 reg_len;
125126 	u16 reg;
126127 	u8 val;
....@@ -144,6 +145,7 @@
144145 
145146 struct max96712 {
146147 	struct i2c_client *client;
148
+	u16 i2c_addr[I2C_DEV_MAX];
147149 	struct clk *xvclk;
148150 	struct gpio_desc *power_gpio;
149151 	struct gpio_desc *reset_gpio;
....@@ -206,91 +208,93 @@
206208 	.reserved = {0},
207209 };
208210 
211
+/* max96717 */
209212 static const struct regval max96712_mipi_4lane_1920x1440_30fps[] = {
210213 	// Link A/B/C/D all use GMSL2, and disabled
211
-	{ 0x29, 2, 0x0006, 0xf0, 0x00, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled
214
+	{ I2C_DEV_DES, 2, 0x0006, 0xf0, 0x00, 0x00 }, // Link A/B/C/D: select GMSL2, Disabled
212215 	// Disable MIPI CSI output
213
-	{ 0x29, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled
216
+	{ I2C_DEV_DES, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled
214217 	// Increase CMU voltage
215
-	{ 0x29, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range
218
+	{ I2C_DEV_DES, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range
216219 	// VGAHiGain
217
-	{ 0x29, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain
218
-	{ 0x29, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain
219
-	{ 0x29, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain
220
-	{ 0x29, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain
220
+	{ I2C_DEV_DES, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain
221
+	{ I2C_DEV_DES, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain
222
+	{ I2C_DEV_DES, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain
223
+	{ I2C_DEV_DES, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain
221224 	// SSC Configuration
222
-	{ 0x29, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC
223
-	{ 0x29, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC
224
-	{ 0x29, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC
225
-	{ 0x29, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC
225
+	{ I2C_DEV_DES, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC
226
+	{ I2C_DEV_DES, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC
227
+	{ I2C_DEV_DES, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC
228
+	{ I2C_DEV_DES, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC
226229 	// GMSL2 Link Video Pipe Selection
227
-	{ 0x29, 2, 0x00F0, 0x62, 0x00, 0x00 }, // Phy A -> Pipe Z -> Pipe 0; Phy B -> Pipe Z -> Pipe 1
228
-	{ 0x29, 2, 0x00F1, 0xea, 0x00, 0x00 }, // Phy C -> Pipe Z -> Pipe 2; Phy D -> Pipe Z -> Pipe 3
229
-	{ 0x29, 2, 0x00F4, 0x0f, 0x00, 0x00 }, // Enable all 4 Pipes
230
+	{ I2C_DEV_DES, 2, 0x00F0, 0x62, 0x00, 0x00 }, // Phy A -> Pipe Z -> Pipe 0; Phy B -> Pipe Z -> Pipe 1
231
+	{ I2C_DEV_DES, 2, 0x00F1, 0xea, 0x00, 0x00 }, // Phy C -> Pipe Z -> Pipe 2; Phy D -> Pipe Z -> Pipe 3
232
+	{ I2C_DEV_DES, 2, 0x00F4, 0x0f, 0x00, 0x00 }, // Enable all 4 Pipes
230233 	// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
231
-	{ 0x29, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
232
-	{ 0x29, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
234
+	{ I2C_DEV_DES, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
235
+	{ I2C_DEV_DES, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
233236 	// For the following MSB 2 bits = VC, LSB 6 bits = DT
234
-	{ 0x29, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
235
-	{ 0x29, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit
236
-	{ 0x29, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
237
-	{ 0x29, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start
238
-	{ 0x29, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
239
-	{ 0x29, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End
237
+	{ I2C_DEV_DES, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
238
+	{ I2C_DEV_DES, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit
239
+	{ I2C_DEV_DES, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
240
+	{ I2C_DEV_DES, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start
241
+	{ I2C_DEV_DES, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
242
+	{ I2C_DEV_DES, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End
240243 	// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
241
-	{ 0x29, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
242
-	{ 0x29, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
244
+	{ I2C_DEV_DES, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
245
+	{ I2C_DEV_DES, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
243246 	// For the following MSB 2 bits = VC, LSB 6 bits = DT
244
-	{ 0x29, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
245
-	{ 0x29, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit
246
-	{ 0x29, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
247
-	{ 0x29, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start
248
-	{ 0x29, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
249
-	{ 0x29, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End
247
+	{ I2C_DEV_DES, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
248
+	{ I2C_DEV_DES, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit
249
+	{ I2C_DEV_DES, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
250
+	{ I2C_DEV_DES, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start
251
+	{ I2C_DEV_DES, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
252
+	{ I2C_DEV_DES, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End
250253 	// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
251
-	{ 0x29, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
252
-	{ 0x29, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
254
+	{ I2C_DEV_DES, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
255
+	{ I2C_DEV_DES, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
253256 	// For the following MSB 2 bits = VC, LSB 6 bits = DT
254
-	{ 0x29, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
255
-	{ 0x29, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit
256
-	{ 0x29, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
257
-	{ 0x29, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start
258
-	{ 0x29, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
259
-	{ 0x29, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End
257
+	{ I2C_DEV_DES, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
258
+	{ I2C_DEV_DES, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit
259
+	{ I2C_DEV_DES, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
260
+	{ I2C_DEV_DES, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start
261
+	{ I2C_DEV_DES, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
262
+	{ I2C_DEV_DES, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End
260263 	// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
261
-	{ 0x29, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
262
-	{ 0x29, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
264
+	{ I2C_DEV_DES, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
265
+	{ I2C_DEV_DES, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
263266 	// For the following MSB 2 bits = VC, LSB 6 bits = DT
264
-	{ 0x29, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
265
-	{ 0x29, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit
266
-	{ 0x29, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
267
-	{ 0x29, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start
268
-	{ 0x29, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
269
-	{ 0x29, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End
267
+	{ I2C_DEV_DES, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
268
+	{ I2C_DEV_DES, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit
269
+	{ I2C_DEV_DES, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
270
+	{ I2C_DEV_DES, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start
271
+	{ I2C_DEV_DES, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
272
+	{ I2C_DEV_DES, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End
270273 	// MIPI PHY Setting
271
-	{ 0x29, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode
274
+	{ I2C_DEV_DES, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode
272275 	// Set Lane Mapping for 4-lane port A
273
-	{ 0x29, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0
276
+	{ I2C_DEV_DES, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0
274277 	// Set 4 lane D-PHY, 2bit VC
275
-	{ 0x29, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC
276
-	{ 0x29, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC
278
+	{ I2C_DEV_DES, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC
279
+	{ I2C_DEV_DES, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC
277280 	// Turn on MIPI PHYs
278
-	{ 0x29, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns
281
+	{ I2C_DEV_DES, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns
279282 	// YUV422 8bit software override for all pipes since connected GMSL1 is under parallel mode
280
-	{ 0x29, 2, 0x040B, 0x80, 0x00, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
281
-	{ 0x29, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit
282
-	{ 0x29, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit
283
-	{ 0x29, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
284
-	{ 0x29, 2, 0x0411, 0x90, 0x00, 0x00 }, // pipe 1 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
285
-	{ 0x29, 2, 0x0412, 0x40, 0x00, 0x00 }, // pipe 2 bpp=0x10, pipe 3 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
283
+	{ I2C_DEV_DES, 2, 0x040B, 0x80, 0x00, 0x00 }, // pipe 0 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
284
+	{ I2C_DEV_DES, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit
285
+	{ I2C_DEV_DES, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit
286
+	{ I2C_DEV_DES, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
287
+	{ I2C_DEV_DES, 2, 0x0411, 0x90, 0x00, 0x00 }, // pipe 1 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
288
+	{ I2C_DEV_DES, 2, 0x0412, 0x40, 0x00, 0x00 }, // pipe 2 bpp=0x10, pipe 3 bpp=0x10: Datatypes = 0x22, 0x1E, 0x2E
286289 	// Enable all links and pipes
287
-	{ 0x29, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0
288
-	{ 0x29, 2, 0x0006, 0xff, 0x00, 0x64 }, // Enable all links and pipes
290
+	{ I2C_DEV_DES, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Port 0
291
+	{ I2C_DEV_DES, 2, 0x0006, 0xff, 0x00, 0x64 }, // Enable all links and pipes
289292 	// Serializer Setting
290
-	{ 0x40, 2, 0x0302, 0x10, 0x00, 0x00 }, // improve CMU voltage performance to improve link robustness
291
-	{ 0x40, 2, 0x1417, 0x00, 0x00, 0x00 }, // Errata
292
-	{ 0x40, 2, 0x1432, 0x7f, 0x00, 0x00 },
293
-	{ 0x29, 2, REG_NULL, 0x00, 0x00, 0x00 },
293
+	{ I2C_DEV_SER, 2, 0x0302, 0x10, 0x00, 0x00 }, // improve CMU voltage performance to improve link robustness
294
+	{ I2C_DEV_SER, 2, 0x1417, 0x00, 0x00, 0x00 }, // Errata
295
+	{ I2C_DEV_SER, 2, 0x1432, 0x7f, 0x00, 0x00 },
296
+	// End register setting
297
+	{ I2C_DEV_DES, 2, REG_NULL, 0x00, 0x00, 0x00 },
294298 };
295299 
296300 static const struct max96712_mode supported_modes_4lane[] = {
....@@ -342,15 +346,17 @@
342346 	MAX96712_LINK_FREQ_MHZ(1250),
343347 };
344348 
345
-static int max96712_write_reg(struct i2c_client *client,
346
-			u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u32 val)
349
+static int max96712_write_reg(struct max96712 *max96712, u8 i2c_id,
350
+			u16 reg, u16 reg_len, u16 val_len, u32 val)
347351 {
352
+	struct i2c_client *client = max96712->client;
353
+	u16 client_addr = max96712->i2c_addr[i2c_id];
348354 	u32 buf_i, val_i;
349355 	u8 buf[6];
350356 	u8 *val_p;
351357 	__be32 val_be;
352358 
353
-	dev_info(&client->dev, "addr(0x%02x) write reg(0x%04x, %d, 0x%02x)\n", \
359
+	dev_info(&client->dev, "addr(0x%02x) write reg(0x%04x, %d, 0x%02x)\n",
354360 		client_addr, reg, reg_len, val);
355361 
356362 	if (val_len > 4)
....@@ -386,9 +392,11 @@
386392 	return 0;
387393 }
388394 
389
-static int max96712_read_reg(struct i2c_client *client,
390
-			u16 client_addr, u16 reg, u16 reg_len, u16 val_len, u8 *val)
395
+static int max96712_read_reg(struct max96712 *max96712, u8 i2c_id,
396
+			u16 reg, u16 reg_len, u16 val_len, u8 *val)
391397 {
398
+	struct i2c_client *client = max96712->client;
399
+	u16 client_addr = max96712->i2c_addr[i2c_id];
392400 	struct i2c_msg msgs[2];
393401 	u8 *data_be_p;
394402 	__be32 data_be = 0;
....@@ -426,34 +434,34 @@
426434 	*val = be32_to_cpu(data_be);
427435 
428436 #if 0
429
-	dev_info(&client->dev, "addr(0x%02x) read reg(0x%04x, %d, 0x%02x)\n", \
437
+	dev_info(&client->dev, "addr(0x%02x) read reg(0x%04x, %d, 0x%02x)\n",
430438 		client_addr, reg, reg_len, *val);
431439 #endif
432440 
433441 	return 0;
434442 }
435443 
436
-static int max96712_update_reg_bits(struct i2c_client *client,
437
-			u16 client_addr, u16 reg, u16 reg_len, u8 mask, u8 val)
444
+static int max96712_update_reg_bits(struct max96712 *max96712, u8 i2c_id,
445
+				u16 reg, u16 reg_len, u8 mask, u8 val)
438446 {
439447 	u8 value;
440
-	u32 val_len = MAX96712_REG_VALUE_08BIT;
448
+	u32 val_len = DEV_REG_VALUE_08BITS;
441449 	int ret;
442450 
443
-	ret = max96712_read_reg(client, client_addr, reg, reg_len, val_len, &value);
451
+	ret = max96712_read_reg(max96712, i2c_id, reg, reg_len, val_len, &value);
444452 	if (ret)
445453 		return ret;
446454 
447455 	value &= ~mask;
448456 	value |= (val & mask);
449
-	ret = max96712_write_reg(client, client_addr, reg, reg_len, val_len, value);
457
+	ret = max96712_write_reg(max96712, i2c_id, reg, reg_len, val_len, value);
450458 	if (ret)
451459 		return ret;
452460 
453461 	return 0;
454462 }
455463 
456
-static int max96712_write_array(struct i2c_client *client,
464
+static int max96712_write_array(struct max96712 *max96712,
457465 				const struct regval *regs)
458466 {
459467 	u32 i;
....@@ -461,13 +469,13 @@
461469 
462470 	for (i = 0; ret == 0 && regs[i].reg != REG_NULL; i++) {
463471 		if (regs[i].mask != 0)
464
-			ret = max96712_update_reg_bits(client, regs[i].i2c_addr,
472
+			ret = max96712_update_reg_bits(max96712, regs[i].i2c_id,
465473 					regs[i].reg, regs[i].reg_len,
466474 					regs[i].mask, regs[i].val);
467475 		else
468
-			ret = max96712_write_reg(client, regs[i].i2c_addr,
476
+			ret = max96712_write_reg(max96712, regs[i].i2c_id,
469477 						regs[i].reg, regs[i].reg_len,
470
-						MAX96712_REG_VALUE_08BIT, regs[i].val);
478
+						DEV_REG_VALUE_08BITS, regs[i].val);
471479 
472480 		if (regs[i].delay != 0)
473481 			msleep(regs[i].delay);
....@@ -478,14 +486,13 @@
478486 
479487 static int max96712_check_local_chipid(struct max96712 *max96712)
480488 {
481
-	struct i2c_client *client = max96712->client;
482489 	struct device *dev = &max96712->client->dev;
483490 	int ret;
484491 	u8 id = 0;
485492 
486
-	ret = max96712_read_reg(client, MAX96712_I2C_ADDR,
487
-				MAX96712_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT,
488
-				MAX96712_REG_VALUE_08BIT, &id);
493
+	ret = max96712_read_reg(max96712, I2C_DEV_DES,
494
+			MAX96712_REG_CHIP_ID, DEV_REG_LENGTH_16BITS,
495
+			DEV_REG_VALUE_08BITS, &id);
489496 	if ((ret != 0) || (id != MAX96712_CHIP_ID)) {
490497 		dev_err(dev, "Unexpected MAX96712 chip id(%02x), ret(%d)\n", id, ret);
491498 		return -ENODEV;
....@@ -507,9 +514,9 @@
507514 	id = 0;
508515 #if 0
509516 	// max96717
510
-	ret = max96712_read_reg(max96712->client, MAX96717_I2C_ADDR,
511
-				MAX96717_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT,
512
-				MAX96712_REG_VALUE_08BIT, &id);
517
+	ret = max96712_read_reg(max96712, I2C_DEV_SER,
518
+			MAX96717_REG_CHIP_ID, DEV_REG_LENGTH_16BITS,
519
+			DEV_REG_VALUE_08BITS, &id);
513520 	if ((ret != 0) || (id != MAX96717_CHIP_ID)) {
514521 		dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret);
515522 		return -ENODEV;
....@@ -519,9 +526,9 @@
519526 
520527 #if 0
521528 	// max96715
522
-	ret = max96712_read_reg(max96712->client, MAX96715_I2C_ADDR,
523
-				MAX96715_REG_CHIP_ID, MAX96712_REG_LENGTH_08BIT,
524
-				MAX96712_REG_VALUE_08BIT, &id);
529
+	ret = max96712_read_reg(max96712, I2C_DEV_SER,
530
+			MAX96715_REG_CHIP_ID, DEV_REG_LENGTH_08BITS,
531
+			DEV_REG_VALUE_08BITS, &id);
525532 	if ((ret != 0) || (id != MAX96715_CHIP_ID)) {
526533 		dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret);
527534 		return -ENODEV;
....@@ -534,96 +541,95 @@
534541 
535542 static u8 max96712_get_link_lock_state(struct max96712 *max96712, u8 link_mask)
536543 {
537
-	struct i2c_client *client = max96712->client;
538544 	struct device *dev = &max96712->client->dev;
539545 	u8 lock = 0, lock_state = 0;
540546 	u8 link_type = 0;
541547 
542
-	link_type = max96712->link_mask & MAX96712_GMSL_TYPE_MASK;
548
+	link_type = max96712->link_mask & MAXIM_GMSL_TYPE_MASK;
543549 
544
-	if (link_mask & MAX96712_LOCK_STATE_LINK_A) {
545
-		if (link_type & MAX96712_GMSL_TYPE_LINK_A) {
550
+	if (link_mask & MAXIM_GMSL_LOCK_LINK_A) {
551
+		if (link_type & MAXIM_GMSL_TYPE_LINK_A) {
546552 			// GMSL2 LinkA
547
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
548
-					0x001a, MAX96712_REG_LENGTH_16BIT,
549
-					MAX96712_REG_VALUE_08BIT, &lock);
553
+			max96712_read_reg(max96712, I2C_DEV_DES,
554
+				0x001a, DEV_REG_LENGTH_16BITS,
555
+				DEV_REG_VALUE_08BITS, &lock);
550556 			if (lock & BIT(3)) {
551
-				lock_state |= MAX96712_LOCK_STATE_LINK_A;
557
+				lock_state |= MAXIM_GMSL_LOCK_LINK_A;
552558 				dev_info(dev, "GMSL2 LinkA locked\n");
553559 			}
554560 		} else {
555561 			// GMSL1 LinkA
556
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
557
-					0x0bcb, MAX96712_REG_LENGTH_16BIT,
558
-					MAX96712_REG_VALUE_08BIT, &lock);
562
+			max96712_read_reg(max96712, I2C_DEV_DES,
563
+				0x0bcb, DEV_REG_LENGTH_16BITS,
564
+				DEV_REG_VALUE_08BITS, &lock);
559565 			if (lock & BIT(0)) {
560
-				lock_state |= MAX96712_LOCK_STATE_LINK_A;
566
+				lock_state |= MAXIM_GMSL_LOCK_LINK_A;
561567 				dev_info(dev, "GMSL1 LinkA locked\n");
562568 			}
563569 		}
564570 	}
565571 
566
-	if (link_mask & MAX96712_LOCK_STATE_LINK_B) {
567
-		if (link_type & MAX96712_GMSL_TYPE_LINK_B) {
572
+	if (link_mask & MAXIM_GMSL_LOCK_LINK_B) {
573
+		if (link_type & MAXIM_GMSL_TYPE_LINK_B) {
568574 			// GMSL2 LinkB
569
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
570
-					0x000a, MAX96712_REG_LENGTH_16BIT,
571
-					MAX96712_REG_VALUE_08BIT, &lock);
575
+			max96712_read_reg(max96712, I2C_DEV_DES,
576
+				0x000a, DEV_REG_LENGTH_16BITS,
577
+				DEV_REG_VALUE_08BITS, &lock);
572578 			if (lock & BIT(3)) {
573
-				lock_state |= MAX96712_LOCK_STATE_LINK_B;
579
+				lock_state |= MAXIM_GMSL_LOCK_LINK_B;
574580 				dev_info(dev, "GMSL2 LinkB locked\n");
575581 			}
576582 		} else {
577583 			// GMSL1 LinkB
578
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
579
-					0x0ccb, MAX96712_REG_LENGTH_16BIT,
580
-					MAX96712_REG_VALUE_08BIT, &lock);
584
+			max96712_read_reg(max96712, I2C_DEV_DES,
585
+				0x0ccb, DEV_REG_LENGTH_16BITS,
586
+				DEV_REG_VALUE_08BITS, &lock);
581587 			if (lock & BIT(0)) {
582
-				lock_state |= MAX96712_LOCK_STATE_LINK_B;
588
+				lock_state |= MAXIM_GMSL_LOCK_LINK_B;
583589 				dev_info(dev, "GMSL1 LinkB locked\n");
584590 			}
585591 		}
586592 	}
587593 
588
-	if (link_mask & MAX96712_LOCK_STATE_LINK_C) {
589
-		if (link_type & MAX96712_GMSL_TYPE_LINK_C) {
594
+	if (link_mask & MAXIM_GMSL_LOCK_LINK_C) {
595
+		if (link_type & MAXIM_GMSL_TYPE_LINK_C) {
590596 			// GMSL2 LinkC
591
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
592
-					0x000b, MAX96712_REG_LENGTH_16BIT,
593
-					MAX96712_REG_VALUE_08BIT, &lock);
597
+			max96712_read_reg(max96712, I2C_DEV_DES,
598
+				0x000b, DEV_REG_LENGTH_16BITS,
599
+				DEV_REG_VALUE_08BITS, &lock);
594600 			if (lock & BIT(3)) {
595
-				lock_state |= MAX96712_LOCK_STATE_LINK_C;
601
+				lock_state |= MAXIM_GMSL_LOCK_LINK_C;
596602 				dev_info(dev, "GMSL2 LinkC locked\n");
597603 			}
598604 		} else {
599605 			// GMSL1 LinkC
600
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
601
-					0x0dcb, MAX96712_REG_LENGTH_16BIT,
602
-					MAX96712_REG_VALUE_08BIT, &lock);
606
+			max96712_read_reg(max96712, I2C_DEV_DES,
607
+				0x0dcb, DEV_REG_LENGTH_16BITS,
608
+				DEV_REG_VALUE_08BITS, &lock);
603609 			if (lock & BIT(0)) {
604
-				lock_state |= MAX96712_LOCK_STATE_LINK_C;
610
+				lock_state |= MAXIM_GMSL_LOCK_LINK_C;
605611 				dev_info(dev, "GMSL1 LinkC locked\n");
606612 			}
607613 		}
608614 	}
609615 
610
-	if (link_mask & MAX96712_LOCK_STATE_LINK_D) {
611
-		if (link_type & MAX96712_GMSL_TYPE_LINK_D) {
616
+	if (link_mask & MAXIM_GMSL_LOCK_LINK_D) {
617
+		if (link_type & MAXIM_GMSL_TYPE_LINK_D) {
612618 			// GMSL2 LinkD
613
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
614
-					0x000c, MAX96712_REG_LENGTH_16BIT,
615
-					MAX96712_REG_VALUE_08BIT, &lock);
619
+			max96712_read_reg(max96712, I2C_DEV_DES,
620
+				0x000c, DEV_REG_LENGTH_16BITS,
621
+				DEV_REG_VALUE_08BITS, &lock);
616622 			if (lock & BIT(3)) {
617
-				lock_state |= MAX96712_LOCK_STATE_LINK_D;
623
+				lock_state |= MAXIM_GMSL_LOCK_LINK_D;
618624 				dev_info(dev, "GMSL2 LinkD locked\n");
619625 			}
620626 		} else {
621627 			// GMSL1 LinkD
622
-			max96712_read_reg(client, MAX96712_I2C_ADDR,
623
-					0x0ecb, MAX96712_REG_LENGTH_16BIT,
624
-					MAX96712_REG_VALUE_08BIT, &lock);
628
+			max96712_read_reg(max96712, I2C_DEV_DES,
629
+				0x0ecb, DEV_REG_LENGTH_16BITS,
630
+				DEV_REG_VALUE_08BITS, &lock);
625631 			if (lock & BIT(0)) {
626
-				lock_state |= MAX96712_LOCK_STATE_LINK_D;
632
+				lock_state |= MAXIM_GMSL_LOCK_LINK_D;
627633 				dev_info(dev, "GMSL1 LinkD locked\n");
628634 			}
629635 		}
....@@ -634,7 +640,6 @@
634640 
635641 static int max96712_check_link_lock_state(struct max96712 *max96712)
636642 {
637
-	struct i2c_client *client = max96712->client;
638643 	struct device *dev = &max96712->client->dev;
639644 	u8 lock_state = 0, link_mask = 0, link_type = 0;
640645 	int ret, i, time_ms;
....@@ -647,99 +652,99 @@
647652 	 *	CTRL0: Enable REG_ENABLE
648653 	 *	CTRL2: Enable REG_MNL
649654 	 */
650
-	max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
651
-				0x0017, MAX96712_REG_LENGTH_16BIT, BIT(2), BIT(2));
652
-	max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
653
-				0x0019, MAX96712_REG_LENGTH_16BIT, BIT(4), BIT(4));
655
+	max96712_update_reg_bits(max96712, I2C_DEV_DES,
656
+			0x0017, DEV_REG_LENGTH_16BITS, BIT(2), BIT(2));
657
+	max96712_update_reg_bits(max96712, I2C_DEV_DES,
658
+			0x0019, DEV_REG_LENGTH_16BITS, BIT(4), BIT(4));
654659 
655660 	// CSI output disabled
656
-	max96712_write_reg(client, MAX96712_I2C_ADDR,
657
-				0x040B, MAX96712_REG_LENGTH_16BIT,
658
-				MAX96712_REG_VALUE_08BIT, 0x00);
661
+	max96712_write_reg(max96712, I2C_DEV_DES,
662
+			0x040B, DEV_REG_LENGTH_16BITS,
663
+			DEV_REG_VALUE_08BITS, 0x00);
659664 
660665 	// All links select mode by link_type and disable at beginning.
661
-	link_type = max96712->link_mask & MAX96712_GMSL_TYPE_MASK;
662
-	max96712_write_reg(client, MAX96712_I2C_ADDR,
663
-				0x0006, MAX96712_REG_LENGTH_16BIT,
664
-				MAX96712_REG_VALUE_08BIT, link_type);
666
+	link_type = max96712->link_mask & MAXIM_GMSL_TYPE_MASK;
667
+	max96712_write_reg(max96712, I2C_DEV_DES,
668
+			0x0006, DEV_REG_LENGTH_16BITS,
669
+			DEV_REG_VALUE_08BITS, link_type);
665670 
666671 	// Link Rate
667672 	if (max96712->rx_rate == MAX96712_RX_RATE_3GBPS) {
668673 		// Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 3Gbps
669
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
670
-					0x0010, MAX96712_REG_LENGTH_16BIT,
671
-					MAX96712_REG_VALUE_08BIT, 0x11);
672
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
673
-					0x0011, MAX96712_REG_LENGTH_16BIT,
674
-					MAX96712_REG_VALUE_08BIT, 0x11);
674
+		max96712_write_reg(max96712, I2C_DEV_DES,
675
+				0x0010, DEV_REG_LENGTH_16BITS,
676
+				DEV_REG_VALUE_08BITS, 0x11);
677
+		max96712_write_reg(max96712, I2C_DEV_DES,
678
+				0x0011, DEV_REG_LENGTH_16BITS,
679
+				DEV_REG_VALUE_08BITS, 0x11);
675680 	} else {
676681 		// Link A ~ Link D Transmitter Rate: 187.5Mbps, Receiver Rate: 6Gbps
677
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
678
-					0x0010, MAX96712_REG_LENGTH_16BIT,
679
-					MAX96712_REG_VALUE_08BIT, 0x22);
680
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
681
-					0x0011, MAX96712_REG_LENGTH_16BIT,
682
-					MAX96712_REG_VALUE_08BIT, 0x22);
682
+		max96712_write_reg(max96712, I2C_DEV_DES,
683
+				0x0010, DEV_REG_LENGTH_16BITS,
684
+				DEV_REG_VALUE_08BITS, 0x22);
685
+		max96712_write_reg(max96712, I2C_DEV_DES,
686
+				0x0011, DEV_REG_LENGTH_16BITS,
687
+				DEV_REG_VALUE_08BITS, 0x22);
683688 	}
684689 
685690 	// GMSL1: Enable HIM on deserializer on Link A/B/C/D
686
-	if ((link_type & MAX96712_GMSL_TYPE_LINK_A) == 0) {
687
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
688
-					0x0B06, MAX96712_REG_LENGTH_16BIT,
689
-					MAX96712_REG_VALUE_08BIT, 0xEF);
691
+	if ((link_type & MAXIM_GMSL_TYPE_LINK_A) == 0) {
692
+		max96712_write_reg(max96712, I2C_DEV_DES,
693
+				0x0B06, DEV_REG_LENGTH_16BITS,
694
+				DEV_REG_VALUE_08BITS, 0xEF);
690695 	}
691
-	if ((link_type & MAX96712_GMSL_TYPE_LINK_B) == 0) {
692
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
693
-					0x0C06, MAX96712_REG_LENGTH_16BIT,
694
-					MAX96712_REG_VALUE_08BIT, 0xEF);
696
+	if ((link_type & MAXIM_GMSL_TYPE_LINK_B) == 0) {
697
+		max96712_write_reg(max96712, I2C_DEV_DES,
698
+				0x0C06, DEV_REG_LENGTH_16BITS,
699
+				DEV_REG_VALUE_08BITS, 0xEF);
695700 	}
696
-	if ((link_type & MAX96712_GMSL_TYPE_LINK_C) == 0) {
697
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
698
-					0x0D06, MAX96712_REG_LENGTH_16BIT,
699
-					MAX96712_REG_VALUE_08BIT, 0xEF);
701
+	if ((link_type & MAXIM_GMSL_TYPE_LINK_C) == 0) {
702
+		max96712_write_reg(max96712, I2C_DEV_DES,
703
+				0x0D06, DEV_REG_LENGTH_16BITS,
704
+				DEV_REG_VALUE_08BITS, 0xEF);
700705 	}
701
-	if ((link_type & MAX96712_GMSL_TYPE_LINK_D) == 0) {
702
-		max96712_write_reg(client, MAX96712_I2C_ADDR,
703
-					0x0E06, MAX96712_REG_LENGTH_16BIT,
704
-					MAX96712_REG_VALUE_08BIT, 0xEF);
706
+	if ((link_type & MAXIM_GMSL_TYPE_LINK_D) == 0) {
707
+		max96712_write_reg(max96712, I2C_DEV_DES,
708
+				0x0E06, DEV_REG_LENGTH_16BITS,
709
+				DEV_REG_VALUE_08BITS, 0xEF);
705710 	}
706711 
707712 	// Link A ~ Link D One-Shot Reset depend on link_mask
708
-	link_mask = max96712->link_mask & MAX96712_LOCK_STATE_MASK;
709
-	max96712_write_reg(client, MAX96712_I2C_ADDR,
710
-				0x0018, MAX96712_REG_LENGTH_16BIT,
711
-				MAX96712_REG_VALUE_08BIT, link_mask);
713
+	link_mask = max96712->link_mask & MAXIM_GMSL_LOCK_MASK;
714
+	max96712_write_reg(max96712, I2C_DEV_DES,
715
+			0x0018, DEV_REG_LENGTH_16BITS,
716
+			DEV_REG_VALUE_08BITS, link_mask);
712717 
713718 	// Link A ~ Link D enable depend on link_type and link_mask
714
-	max96712_write_reg(client, MAX96712_I2C_ADDR,
715
-			0x0006, MAX96712_REG_LENGTH_16BIT,
716
-			MAX96712_REG_VALUE_08BIT, link_type | link_mask);
719
+	max96712_write_reg(max96712, I2C_DEV_DES,
720
+			0x0006, DEV_REG_LENGTH_16BITS,
721
+			DEV_REG_VALUE_08BITS, link_type | link_mask);
717722 
718723 	time_ms = 50;
719724 	msleep(time_ms);
720725 
721726 	for (i = 0; i < 20; i++) {
722
-		if ((lock_state & MAX96712_LOCK_STATE_LINK_A) == 0)
723
-			if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_A)) {
724
-				lock_state |= MAX96712_LOCK_STATE_LINK_A;
727
+		if ((lock_state & MAXIM_GMSL_LOCK_LINK_A) == 0)
728
+			if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_A)) {
729
+				lock_state |= MAXIM_GMSL_LOCK_LINK_A;
725730 				dev_info(dev, "LinkA locked time: %d ms\n", time_ms);
726731 			}
727732 
728
-		if ((lock_state & MAX96712_LOCK_STATE_LINK_B) == 0)
729
-			if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_B)) {
730
-				lock_state |= MAX96712_LOCK_STATE_LINK_B;
733
+		if ((lock_state & MAXIM_GMSL_LOCK_LINK_B) == 0)
734
+			if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_B)) {
735
+				lock_state |= MAXIM_GMSL_LOCK_LINK_B;
731736 				dev_info(dev, "LinkB locked time: %d ms\n", time_ms);
732737 			}
733738 
734
-		if ((lock_state & MAX96712_LOCK_STATE_LINK_C) == 0)
735
-			if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_C)) {
736
-				lock_state |= MAX96712_LOCK_STATE_LINK_C;
739
+		if ((lock_state & MAXIM_GMSL_LOCK_LINK_C) == 0)
740
+			if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_C)) {
741
+				lock_state |= MAXIM_GMSL_LOCK_LINK_C;
737742 				dev_info(dev, "LinkC locked time: %d ms\n", time_ms);
738743 			}
739744 
740
-		if ((lock_state & MAX96712_LOCK_STATE_LINK_D) == 0)
741
-			if (max96712_get_link_lock_state(max96712, MAX96712_LOCK_STATE_LINK_D)) {
742
-				lock_state |= MAX96712_LOCK_STATE_LINK_D;
745
+		if ((lock_state & MAXIM_GMSL_LOCK_LINK_D) == 0)
746
+			if (max96712_get_link_lock_state(max96712, MAXIM_GMSL_LOCK_LINK_D)) {
747
+				lock_state |= MAXIM_GMSL_LOCK_LINK_D;
743748 				dev_info(dev, "LinkD locked time: %d ms\n", time_ms);
744749 			}
745750 
....@@ -770,7 +775,7 @@
770775 	struct device *dev = &max96712->client->dev;
771776 	u8 lock_state = 0, link_mask = 0;
772777 
773
-	link_mask = max96712->link_mask & MAX96712_LOCK_STATE_MASK;
778
+	link_mask = max96712->link_mask & MAXIM_GMSL_LOCK_MASK;
774779 	if (max96712->streaming) {
775780 		lock_state = max96712_get_link_lock_state(max96712, link_mask);
776781 		if (lock_state == link_mask) {
....@@ -783,21 +788,21 @@
783788 	return IRQ_HANDLED;
784789 }
785790 
786
-static int __maybe_unused max96712_dphy_dpll_predef_set(struct i2c_client *client,
787
-				u32 link_freq_mhz)
791
+static int max96712_dphy_dpll_predef_set(struct max96712 *max96712, u32 link_freq_mhz)
788792 {
793
+	struct device *dev = &max96712->client->dev;
789794 	int ret = 0;
790795 	u8 dpll_val = 0, dpll_lock = 0;
791796 	u8 mipi_tx_phy_enable = 0;
792797 
793
-	ret = max96712_read_reg(client, MAX96712_I2C_ADDR,
794
-			0x08A2, MAX96712_REG_LENGTH_16BIT,
795
-			MAX96712_REG_VALUE_08BIT, &mipi_tx_phy_enable);
798
+	ret = max96712_read_reg(max96712, I2C_DEV_DES,
799
+			0x08A2, DEV_REG_LENGTH_16BITS,
800
+			DEV_REG_VALUE_08BITS, &mipi_tx_phy_enable);
796801 	if (ret)
797802 		return ret;
798803 	mipi_tx_phy_enable = (mipi_tx_phy_enable & 0xF0) >> 4;
799804 
800
-	dev_info(&client->dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n",
805
+	dev_info(dev, "DPLL predef set: mipi_tx_phy_enable = 0x%02x, link_freq_mhz = %d\n",
801806 			mipi_tx_phy_enable, link_freq_mhz);
802807 
803808 	// dphy max data rate is 2500MHz
....@@ -811,116 +816,117 @@
811816 	// MIPI PHY0
812817 	if (mipi_tx_phy_enable & BIT(0)) {
813818 		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
814
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
815
-			0x1C00, MAX96712_REG_LENGTH_16BIT,
816
-			MAX96712_REG_VALUE_08BIT,
817
-			0xf4);
819
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
820
+				0x1C00, DEV_REG_LENGTH_16BITS,
821
+				DEV_REG_VALUE_08BITS, 0xf4);
818822 		// Set data rate and enable software override
819
-		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
820
-			0x0415, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val);
823
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
824
+				0x0415, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
821825 		// Release reset to DPLL (config_soft_rst_n = 1)
822
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
823
-			0x1C00, MAX96712_REG_LENGTH_16BIT,
824
-			MAX96712_REG_VALUE_08BIT, 0xf5);
826
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
827
+				0x1C00, DEV_REG_LENGTH_16BITS,
828
+				DEV_REG_VALUE_08BITS, 0xf5);
825829 	}
826830 
827831 	// MIPI PHY1
828832 	if (mipi_tx_phy_enable & BIT(1)) {
829833 		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
830
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
831
-			0x1D00, MAX96712_REG_LENGTH_16BIT,
832
-			MAX96712_REG_VALUE_08BIT, 0xf4);
834
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
835
+				0x1D00, DEV_REG_LENGTH_16BITS,
836
+				DEV_REG_VALUE_08BITS, 0xf4);
833837 		// Set data rate and enable software override
834
-		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
835
-			0x0418, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val);
838
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
839
+				0x0418, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
836840 		// Release reset to DPLL (config_soft_rst_n = 1)
837
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
838
-			0x1D00, MAX96712_REG_LENGTH_16BIT,
839
-			MAX96712_REG_VALUE_08BIT, 0xf5);
841
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
842
+				0x1D00, DEV_REG_LENGTH_16BITS,
843
+				DEV_REG_VALUE_08BITS, 0xf5);
840844 	}
841845 
842846 	// MIPI PHY2
843847 	if (mipi_tx_phy_enable & BIT(2)) {
844848 		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
845
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
846
-			0x1E00, MAX96712_REG_LENGTH_16BIT,
847
-			MAX96712_REG_VALUE_08BIT, 0xf4);
849
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
850
+				0x1E00, DEV_REG_LENGTH_16BITS,
851
+				DEV_REG_VALUE_08BITS, 0xf4);
848852 		// Set data rate and enable software override
849
-		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
850
-			0x041B, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val);
853
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
854
+				0x041B, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
851855 		// Release reset to DPLL (config_soft_rst_n = 1)
852
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
853
-			0x1E00, MAX96712_REG_LENGTH_16BIT,
854
-			MAX96712_REG_VALUE_08BIT, 0xf5);
856
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
857
+				0x1E00, DEV_REG_LENGTH_16BITS,
858
+				DEV_REG_VALUE_08BITS, 0xf5);
855859 	}
856860 
857861 	// MIPI PHY3
858862 	if (mipi_tx_phy_enable & BIT(3)) {
859863 		// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
860
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
861
-			0x1F00, MAX96712_REG_LENGTH_16BIT,
862
-			MAX96712_REG_VALUE_08BIT, 0xf4);
864
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
865
+				0x1F00, DEV_REG_LENGTH_16BITS,
866
+				DEV_REG_VALUE_08BITS, 0xf4);
863867 		// Set data rate and enable software override
864
-		ret |= max96712_update_reg_bits(client, MAX96712_I2C_ADDR,
865
-			0x041E, MAX96712_REG_LENGTH_16BIT, 0x3F, dpll_val);
868
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
869
+				0x041E, DEV_REG_LENGTH_16BITS, 0x3F, dpll_val);
866870 		// Release reset to DPLL (config_soft_rst_n = 1)
867
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
868
-			0x1F00, MAX96712_REG_LENGTH_16BIT,
869
-			MAX96712_REG_VALUE_08BIT, 0xf5);
871
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
872
+				0x1F00, DEV_REG_LENGTH_16BITS,
873
+				DEV_REG_VALUE_08BITS, 0xf5);
870874 	}
871875 
872876 	if (ret) {
873
-		dev_err(&client->dev, "DPLL predef set error!\n");
877
+		dev_err(dev, "DPLL predef set error!\n");
874878 		return ret;
875879 	}
876880 
877881 	ret = read_poll_timeout(max96712_read_reg, ret,
878882 				!(ret < 0) && (dpll_lock & 0xF0),
879883 				1000, 10000, false,
880
-				client, MAX96712_I2C_ADDR,
881
-				0x0400, MAX96712_REG_LENGTH_16BIT,
882
-				MAX96712_REG_VALUE_08BIT, &dpll_lock);
884
+				max96712, I2C_DEV_DES,
885
+				0x0400, DEV_REG_LENGTH_16BITS,
886
+				DEV_REG_VALUE_08BITS, &dpll_lock);
883887 	if (ret < 0) {
884
-		dev_err(&client->dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock);
888
+		dev_err(dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock);
885889 		return ret;
886890 	} else {
887
-		dev_err(&client->dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock);
891
+		dev_err(dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock);
888892 		return 0;
889893 	}
890894 }
891895 
892
-static int max96712_auto_init_deskew(struct i2c_client *client, u32 deskew_mask)
896
+static int max96712_auto_init_deskew(struct max96712 *max96712, u32 deskew_mask)
893897 {
898
+	struct device *dev = &max96712->client->dev;
894899 	int ret = 0;
895900 
896
-	dev_info(&client->dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask);
901
+	dev_info(dev, "Auto initial deskew: deskew_mask = 0x%02x\n", deskew_mask);
897902 
898903 	// D-PHY Deskew Initial Calibration Control
899904 	if (deskew_mask & BIT(0)) // MIPI PHY0
900
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
901
-			0x0903, MAX96712_REG_LENGTH_16BIT,
902
-			MAX96712_REG_VALUE_08BIT, 0x80);
905
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
906
+				0x0903, DEV_REG_LENGTH_16BITS,
907
+				DEV_REG_VALUE_08BITS, 0x80);
903908 
904909 	if (deskew_mask & BIT(1)) // MIPI PHY1
905
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
906
-			0x0943, MAX96712_REG_LENGTH_16BIT,
907
-			MAX96712_REG_VALUE_08BIT, 0x80);
910
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
911
+				0x0943, DEV_REG_LENGTH_16BITS,
912
+				DEV_REG_VALUE_08BITS, 0x80);
908913 
909914 	if (deskew_mask & BIT(2)) // MIPI PHY2
910
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
911
-			0x0983, MAX96712_REG_LENGTH_16BIT,
912
-			MAX96712_REG_VALUE_08BIT, 0x80);
915
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
916
+				0x0983, DEV_REG_LENGTH_16BITS,
917
+				DEV_REG_VALUE_08BITS, 0x80);
913918 
914919 	if (deskew_mask & BIT(3)) // MIPI PHY3
915
-		ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
916
-			0x09C3, MAX96712_REG_LENGTH_16BIT,
917
-			MAX96712_REG_VALUE_08BIT, 0x80);
920
+		ret |= max96712_write_reg(max96712, I2C_DEV_DES,
921
+				0x09C3, DEV_REG_LENGTH_16BITS,
922
+				DEV_REG_VALUE_08BITS, 0x80);
918923 
919924 	return ret;
920925 }
921926 
922
-static int max96712_frame_sync_period(struct i2c_client *client, u32 period)
927
+static int max96712_frame_sync_period(struct max96712 *max96712, u32 period)
923928 {
929
+	struct device *dev = &max96712->client->dev;
924930 	u32 pclk, fsync_peroid;
925931 	u8 fsync_peroid_h, fsync_peroid_m, fsync_peroid_l;
926932 	int ret = 0;
....@@ -928,30 +934,30 @@
928934 	if (period == 0)
929935 		return 0;
930936 
931
-	dev_info(&client->dev, "Frame sync period = %d\n", period);
937
+	dev_info(dev, "Frame sync period = %d\n", period);
932938 
933
-#if 1 // TODO: Sensor
939
+#if 1 // TODO: Sensor slave mode
934940 	// SC320AT slave mode enable
935
-	ret |= max96712_write_reg(client, 0x30,
936
-		0x3222, MAX96712_REG_LENGTH_16BIT,
937
-		MAX96712_REG_VALUE_08BIT, 0x01);
941
+	ret |= max96712_write_reg(max96712, I2C_DEV_CAM,
942
+			0x3222, DEV_REG_LENGTH_16BITS,
943
+			DEV_REG_VALUE_08BITS, 0x01);
938944 	// Increase the allowable error range of the trigger signal
939
-	ret |= max96712_write_reg(client, 0x30,
940
-		0x32e2, MAX96712_REG_LENGTH_16BIT,
941
-		MAX96712_REG_VALUE_08BIT, 0x19);
945
+	ret |= max96712_write_reg(max96712, I2C_DEV_CAM,
946
+			0x32e2, DEV_REG_LENGTH_16BITS,
947
+			DEV_REG_VALUE_08BITS, 0x19);
942948 #endif
943949 
944950 	// Master link Video 0 for frame sync generation
945
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
946
-		0x04A2, MAX96712_REG_LENGTH_16BIT,
947
-		MAX96712_REG_VALUE_08BIT, 0x00);
951
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
952
+			0x04A2, DEV_REG_LENGTH_16BITS,
953
+			DEV_REG_VALUE_08BITS, 0x00);
948954 	// Disable Vsync-Fsync overlap window
949
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
950
-		0x04AA, MAX96712_REG_LENGTH_16BIT,
951
-		MAX96712_REG_VALUE_08BIT, 0x00);
952
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
953
-		0x04AB, MAX96712_REG_LENGTH_16BIT,
954
-		MAX96712_REG_VALUE_08BIT, 0x00);
955
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
956
+			0x04AA, DEV_REG_LENGTH_16BITS,
957
+			DEV_REG_VALUE_08BITS, 0x00);
958
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
959
+			0x04AB, DEV_REG_LENGTH_16BITS,
960
+			DEV_REG_VALUE_08BITS, 0x00);
955961 
956962 	// Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz
957963 	pclk = 25 * 1000 * 1000;
....@@ -959,72 +965,70 @@
959965 	fsync_peroid_l = (fsync_peroid >> 0) & 0xFF;
960966 	fsync_peroid_m = (fsync_peroid >> 8) & 0xFF;
961967 	fsync_peroid_h = (fsync_peroid >> 16) & 0xFF;
962
-	dev_info(&client->dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n",
968
+	dev_info(dev, "Frame sync period: H = 0x%02x, M = 0x%02x, L = 0x%02x\n",
963969 			fsync_peroid_h, fsync_peroid_m, fsync_peroid_l);
964970 	// FSYNC_PERIOD_H
965
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
966
-		0x04A7, MAX96712_REG_LENGTH_16BIT,
967
-		MAX96712_REG_VALUE_08BIT, fsync_peroid_h);
971
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
972
+			0x04A7, DEV_REG_LENGTH_16BITS,
973
+			DEV_REG_VALUE_08BITS, fsync_peroid_h);
968974 	// FSYNC_PERIOD_M
969
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
970
-		0x04A6, MAX96712_REG_LENGTH_16BIT,
971
-		MAX96712_REG_VALUE_08BIT, fsync_peroid_m);
975
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
976
+			0x04A6, DEV_REG_LENGTH_16BITS,
977
+			DEV_REG_VALUE_08BITS, fsync_peroid_m);
972978 	// FSYNC_PERIOD_L
973
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
974
-		0x04A5, MAX96712_REG_LENGTH_16BIT,
975
-		MAX96712_REG_VALUE_08BIT, fsync_peroid_l);
979
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
980
+			0x04A5, DEV_REG_LENGTH_16BITS,
981
+			DEV_REG_VALUE_08BITS, fsync_peroid_l);
976982 
977983 	// FSYNC is GMSL2 type, use osc for fsync, include all links/pipes in fsync gen
978
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
979
-		0x04AF, MAX96712_REG_LENGTH_16BIT,
980
-		MAX96712_REG_VALUE_08BIT, 0xcf);
984
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
985
+			0x04AF, DEV_REG_LENGTH_16BITS,
986
+			DEV_REG_VALUE_08BITS, 0xcf);
981987 
988
+#if 1 // TODO: Desrializer MFP
982989 	// FSYNC_TX_ID: set 4 to match MFP4 on serializer side
983
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
984
-		0x04B1, MAX96712_REG_LENGTH_16BIT,
985
-		MAX96712_REG_VALUE_08BIT, 0x20);
990
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
991
+			0x04B1, DEV_REG_LENGTH_16BITS,
992
+			DEV_REG_VALUE_08BITS, 0x20);
993
+#endif
986994 
987
-#if 1 // TODO: Serializer
995
+#if 1 // TODO: Serializer MFP
988996 	// Enable GPIO_RX_EN on serializer MFP4
989
-	ret |= max96712_write_reg(client, 0x40,
990
-		0x02CA, MAX96712_REG_LENGTH_16BIT,
991
-		MAX96712_REG_VALUE_08BIT, 0x84);
997
+	ret |= max96712_write_reg(max96712, I2C_DEV_SER,
998
+			0x02CA, DEV_REG_LENGTH_16BITS,
999
+			DEV_REG_VALUE_08BITS, 0x84);
9921000 #endif
9931001 
9941002 	// MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode
995
-	ret |= max96712_write_reg(client, MAX96712_I2C_ADDR,
996
-		0x04A0, MAX96712_REG_LENGTH_16BIT,
997
-		MAX96712_REG_VALUE_08BIT, 0x04);
1003
+	ret |= max96712_write_reg(max96712, I2C_DEV_DES,
1004
+			0x04A0, DEV_REG_LENGTH_16BITS,
1005
+			DEV_REG_VALUE_08BITS, 0x04);
9981006 
9991007 	return ret;
10001008 }
10011009 
1002
-static int max96712_mipi_enable(struct i2c_client *client, bool enable)
1010
+static int max96712_mipi_enable(struct max96712 *max96712, bool enable)
10031011 {
10041012 	int ret = 0;
10051013 
10061014 	if (enable) {
1007
-#if MAX96712_FORCE_ALL_CLOCK_EN
1015
+#if MAXIM_FORCE_ALL_CLOCK_EN
10081016 		// Force all MIPI clocks running
1009
-		ret |= max96712_update_reg_bits(client,
1010
-				MAX96712_I2C_ADDR,
1011
-				0x08A0, MAX96712_REG_LENGTH_16BIT, BIT(7), BIT(7));
1017
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1018
+				0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), BIT(7));
10121019 #endif
10131020 		// CSI output enabled
1014
-		ret |= max96712_update_reg_bits(client,
1015
-				MAX96712_I2C_ADDR,
1016
-				0x040B, MAX96712_REG_LENGTH_16BIT, BIT(1), BIT(1));
1021
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1022
+				0x040B, DEV_REG_LENGTH_16BITS, BIT(1), BIT(1));
10171023 	} else {
1018
-#if MAX96712_FORCE_ALL_CLOCK_EN
1024
+#if MAXIM_FORCE_ALL_CLOCK_EN
10191025 		// Normal mode
1020
-		ret |= max96712_update_reg_bits(client,
1021
-				MAX96712_I2C_ADDR,
1022
-				0x08A0, MAX96712_REG_LENGTH_16BIT, BIT(7), 0x00);
1026
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1027
+				0x08A0, DEV_REG_LENGTH_16BITS, BIT(7), 0x00);
10231028 #endif
10241029 		// CSI output disabled
1025
-		ret |= max96712_update_reg_bits(client,
1026
-				MAX96712_I2C_ADDR,
1027
-				0x040B, MAX96712_REG_LENGTH_16BIT, BIT(1), 0x00);
1030
+		ret |= max96712_update_reg_bits(max96712, I2C_DEV_DES,
1031
+				0x040B, DEV_REG_LENGTH_16BITS, BIT(1), 0x00);
10281032 	}
10291033 
10301034 	return ret;
....@@ -1229,9 +1233,9 @@
12291233 		stream = *((u32 *)arg);
12301234 
12311235 		if (stream)
1232
-			ret = max96712_mipi_enable(max96712->client, true);
1236
+			ret = max96712_mipi_enable(max96712, true);
12331237 		else
1234
-			ret = max96712_mipi_enable(max96712->client, false);
1238
+			ret = max96712_mipi_enable(max96712, false);
12351239 		break;
12361240 	case RKMODULE_GET_VICAP_RST_INFO:
12371241 		max96712_get_vicap_rst_inf(
....@@ -1408,26 +1412,26 @@
14081412 	if (max96712->hot_plug_irq > 0)
14091413 		enable_irq(max96712->hot_plug_irq);
14101414 
1411
-	ret = max96712_write_array(max96712->client,
1415
+	ret = max96712_write_array(max96712,
14121416 				   max96712->cur_mode->reg_list);
14131417 	if (ret)
14141418 		return ret;
14151419 
14161420 	link_freq_idx = max96712->cur_mode->link_freq_idx;
14171421 	link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L);
1418
-	ret = max96712_dphy_dpll_predef_set(max96712->client, link_freq_mhz);
1422
+	ret = max96712_dphy_dpll_predef_set(max96712, link_freq_mhz);
14191423 	if (ret)
14201424 		return ret;
14211425 
14221426 	if (max96712->auto_init_deskew_mask != 0) {
1423
-		ret = max96712_auto_init_deskew(max96712->client,
1427
+		ret = max96712_auto_init_deskew(max96712,
14241428 					max96712->auto_init_deskew_mask);
14251429 		if (ret)
14261430 			return ret;
14271431 	}
14281432 
14291433 	if (max96712->frame_sync_period != 0) {
1430
-		ret = max96712_frame_sync_period(max96712->client,
1434
+		ret = max96712_frame_sync_period(max96712,
14311435 					max96712->frame_sync_period);
14321436 		if (ret)
14331437 			return ret;
....@@ -1440,7 +1444,7 @@
14401444 	if (ret)
14411445 		return ret;
14421446 
1443
-	return max96712_mipi_enable(max96712->client, true);
1447
+	return max96712_mipi_enable(max96712, true);
14441448 
14451449 }
14461450 
....@@ -1449,7 +1453,7 @@
14491453 	if (max96712->hot_plug_irq > 0)
14501454 		disable_irq(max96712->hot_plug_irq);
14511455 
1452
-	return max96712_mipi_enable(max96712->client, false);
1456
+	return max96712_mipi_enable(max96712, false);
14531457 }
14541458 
14551459 static int max96712_s_stream(struct v4l2_subdev *sd, int on)
....@@ -1823,7 +1827,18 @@
18231827 	struct device *dev = &max96712->client->dev;
18241828 	struct device_node *node = dev->of_node;
18251829 	u8 mipi_data_lanes = max96712->bus_cfg.bus.mipi_csi2.num_data_lanes;
1830
+	u32 value = 0;
18261831 	int ret = 0;
1832
+
1833
+	/* serializer i2c address */
1834
+	ret = of_property_read_u32(node, "ser-i2c-addr", &value);
1835
+	if (ret) {
1836
+		max96712->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR;
1837
+	} else {
1838
+		dev_info(dev, "ser-i2c-addr property: %d\n", value);
1839
+		max96712->i2c_addr[I2C_DEV_SER] = value;
1840
+	}
1841
+	dev_info(dev, "serializer i2c address: 0x%02x\n", max96712->i2c_addr[I2C_DEV_SER]);
18271842 
18281843 	/* max96712 link Receiver Rate: 3G or 6G */
18291844 	ret = of_property_read_u32(node, "link-rx-rate",
....@@ -1855,14 +1870,14 @@
18551870 
18561871 	/* auto initial deskew mask */
18571872 	ret = of_property_read_u32(node, "auto-init-deskew-mask",
1858
-			   &max96712->auto_init_deskew_mask);
1873
+				&max96712->auto_init_deskew_mask);
18591874 	if (ret)
18601875 		max96712->auto_init_deskew_mask = 0x0F; // 0x0F: default enable all
18611876 	dev_info(dev, "auto init deskew mask: 0x%02x\n", max96712->auto_init_deskew_mask);
18621877 
18631878 	/* FSYNC period config */
18641879 	ret = of_property_read_u32(node, "frame-sync-period",
1865
-			   &max96712->frame_sync_period);
1880
+				&max96712->frame_sync_period);
18661881 	if (ret)
18671882 		max96712->frame_sync_period = 0; // 0: disable (default)
18681883 	dev_info(dev, "frame sync period: %d\n", max96712->frame_sync_period);
....@@ -1910,6 +1925,11 @@
19101925 
19111926 	max96712->client = client;
19121927 	i2c_set_clientdata(client, max96712);
1928
+
1929
+	/* i2c default address init */
1930
+	max96712->i2c_addr[I2C_DEV_DES] = client->addr;
1931
+	max96712->i2c_addr[I2C_DEV_SER] = SER_I2C_ADDR;
1932
+	max96712->i2c_addr[I2C_DEV_CAM] = CAM_I2C_ADDR;
19131933 
19141934 	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
19151935 	if (!endpoint) {
....@@ -2023,19 +2043,23 @@
20232043 
20242044 	if (!IS_ERR(max96712->lock_gpio)) {
20252045 		max96712->hot_plug_irq = gpiod_to_irq(max96712->lock_gpio);
2026
-		if (max96712->hot_plug_irq < 0)
2046
+		if (max96712->hot_plug_irq < 0) {
20272047 			dev_err(dev, "failed to get hot plug irq\n");
2028
-
2029
-		ret = devm_request_threaded_irq(dev,
2030
-				max96712->hot_plug_irq,
2031
-				NULL,
2032
-				max96712_hot_plug_detect_irq_handler,
2033
-				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
2034
-				"max96712_hot_plug",
2035
-				max96712);
2036
-		if (ret)
2037
-			dev_err(dev, "failed to request hot plug irq (%d)\n", ret);
2038
-		disable_irq(max96712->hot_plug_irq);
2048
+		} else {
2049
+			ret = devm_request_threaded_irq(dev,
2050
+					max96712->hot_plug_irq,
2051
+					NULL,
2052
+					max96712_hot_plug_detect_irq_handler,
2053
+					IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
2054
+					"max96712_hot_plug",
2055
+					max96712);
2056
+			if (ret) {
2057
+				dev_err(dev, "failed to request hot plug irq (%d)\n", ret);
2058
+				max96712->hot_plug_irq = -1;
2059
+			} else {
2060
+				disable_irq(max96712->hot_plug_irq);
2061
+			}
2062
+		}
20392063 	}
20402064 
20412065 	pm_runtime_set_active(dev);