~hc/RK356X_SDK_RELEASE.git

..	..	@@ -50,6 +50,8 @@
50	50	#include <media/v4l2-subdev.h>
51	51	#include <linux/pinctrl/consumer.h>
52	52	#include <linux/rk-preisp.h>
	53	+#include <media/v4l2-fwnode.h>
	54	+#include <linux/of_graph.h>
53	55	#include "../platform/rockchip/isp/rkisp_tb_helper.h"
54	56
55	57	#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x08)
..	..	@@ -58,17 +60,20 @@
58	60	#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
59	61	#endif
60	62
	63	+#define MIPI_FREQ_1188M 1188000000
61	64	#define MIPI_FREQ_891M 891000000
62	65	#define MIPI_FREQ_446M 446000000
63	66	#define MIPI_FREQ_743M 743000000
64	67	#define MIPI_FREQ_297M 297000000
65	68
66	69	#define IMX415_4LANES 4
	70	+#define IMX415_2LANES 2
67	71
68	72	#define IMX415_MAX_PIXEL_RATE (MIPI_FREQ_891M / 10 * 2 * IMX415_4LANES)
69	73	#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
70	74
71	75	#define IMX415_XVCLK_FREQ_37M 37125000
	76	+#define IMX415_XVCLK_FREQ_27M 27000000
72	77
73	78	/* TODO: Get the real chip id from reg */
74	79	#define CHIP_ID 0xE0
..	..	@@ -142,6 +147,7 @@
142	147	#define IMX415_FLIP_REG 0x3030
143	148
144	149	#define REG_NULL 0xFFFF
	150	+#define REG_DELAY 0xFFFE
145	151
146	152	#define IMX415_REG_VALUE_08BIT 1
147	153	#define IMX415_REG_VALUE_16BIT 2
..	..	@@ -164,6 +170,7 @@
164	170
165	171	#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
166	172	#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
	173	+#define RKMODULE_CAMERA_FASTBOOT_ENABLE "rockchip,camera_fastboot"
167	174
168	175	#define IMX415_NAME "imx415"
169	176
..	..	@@ -194,6 +201,7 @@
194	201	const struct regval *reg_list;
195	202	u32 hdr_mode;
196	203	u32 vc[PAD_MAX];
	204	+ u32 xvclk;
197	205	};
198	206
199	207	struct imx415 {
..	..	@@ -220,9 +228,10 @@
220	228	struct mutex mutex;
221	229	bool streaming;
222	230	bool power_on;
223		- bool is_thunderboot;
	231	+ u32 is_thunderboot;
224	232	bool is_thunderboot_ng;
225	233	bool is_first_streamoff;
	234	+ const struct imx415_mode *supported_modes;
226	235	const struct imx415_mode *cur_mode;
227	236	u32 module_index;
228	237	u32 cfg_num;
..	..	@@ -232,6 +241,7 @@
232	241	u32 cur_vts;
233	242	bool has_init_exp;
234	243	struct preisp_hdrae_exp_s init_hdrae_exp;
	244	+ struct v4l2_fwnode_endpoint bus_cfg;
235	245	};
236	246
237	247	static struct rkmodule_csi_dphy_param dcphy_param = {
..	..	@@ -746,6 +756,311 @@
746	756	};
747	757
748	758	/*
	759	+ * Xclk 27Mhz
	760	+ * 15fps
	761	+ * CSI-2_2lane
	762	+ * AD:12bit Output:12bit
	763	+ * 891Mbps
	764	+ * Master Mode
	765	+ * Time 9.988ms Gain:6dB
	766	+ * All-pixel
	767	+ */
	768	+static __maybe_unused const struct regval imx415_linear_12bit_3864x2192_891M_regs_2lane[] = {
	769	+ {0x3008, 0x5D},
	770	+ {0x300A, 0x42},
	771	+ {0x3028, 0x98},
	772	+ {0x3029, 0x08},
	773	+ {0x3033, 0x05},
	774	+ {0x3050, 0x79},
	775	+ {0x3051, 0x07},
	776	+ {0x3090, 0x14},
	777	+ {0x30C1, 0x00},
	778	+ {0x3116, 0x23},
	779	+ {0x3118, 0xC6},
	780	+ {0x311A, 0xE7},
	781	+ {0x311E, 0x23},
	782	+ {0x32D4, 0x21},
	783	+ {0x32EC, 0xA1},
	784	+ {0x344C, 0x2B},
	785	+ {0x344D, 0x01},
	786	+ {0x344E, 0xED},
	787	+ {0x344F, 0x01},
	788	+ {0x3450, 0xF6},
	789	+ {0x3451, 0x02},
	790	+ {0x3452, 0x7F},
	791	+ {0x3453, 0x03},
	792	+ {0x358A, 0x04},
	793	+ {0x35A1, 0x02},
	794	+ {0x35EC, 0x27},
	795	+ {0x35EE, 0x8D},
	796	+ {0x35F0, 0x8D},
	797	+ {0x35F2, 0x29},
	798	+ {0x36BC, 0x0C},
	799	+ {0x36CC, 0x53},
	800	+ {0x36CD, 0x00},
	801	+ {0x36CE, 0x3C},
	802	+ {0x36D0, 0x8C},
	803	+ {0x36D1, 0x00},
	804	+ {0x36D2, 0x71},
	805	+ {0x36D4, 0x3C},
	806	+ {0x36D6, 0x53},
	807	+ {0x36D7, 0x00},
	808	+ {0x36D8, 0x71},
	809	+ {0x36DA, 0x8C},
	810	+ {0x36DB, 0x00},
	811	+ {0x3720, 0x00},
	812	+ {0x3724, 0x02},
	813	+ {0x3726, 0x02},
	814	+ {0x3732, 0x02},
	815	+ {0x3734, 0x03},
	816	+ {0x3736, 0x03},
	817	+ {0x3742, 0x03},
	818	+ {0x3862, 0xE0},
	819	+ {0x38CC, 0x30},
	820	+ {0x38CD, 0x2F},
	821	+ {0x395C, 0x0C},
	822	+ {0x39A4, 0x07},
	823	+ {0x39A8, 0x32},
	824	+ {0x39AA, 0x32},
	825	+ {0x39AC, 0x32},
	826	+ {0x39AE, 0x32},
	827	+ {0x39B0, 0x32},
	828	+ {0x39B2, 0x2F},
	829	+ {0x39B4, 0x2D},
	830	+ {0x39B6, 0x28},
	831	+ {0x39B8, 0x30},
	832	+ {0x39BA, 0x30},
	833	+ {0x39BC, 0x30},
	834	+ {0x39BE, 0x30},
	835	+ {0x39C0, 0x30},
	836	+ {0x39C2, 0x2E},
	837	+ {0x39C4, 0x2B},
	838	+ {0x39C6, 0x25},
	839	+ {0x3A42, 0xD1},
	840	+ {0x3A4C, 0x77},
	841	+ {0x3AE0, 0x02},
	842	+ {0x3AEC, 0x0C},
	843	+ {0x3B00, 0x2E},
	844	+ {0x3B06, 0x29},
	845	+ {0x3B98, 0x25},
	846	+ {0x3B99, 0x21},
	847	+ {0x3B9B, 0x13},
	848	+ {0x3B9C, 0x13},
	849	+ {0x3B9D, 0x13},
	850	+ {0x3B9E, 0x13},
	851	+ {0x3BA1, 0x00},
	852	+ {0x3BA2, 0x06},
	853	+ {0x3BA3, 0x0B},
	854	+ {0x3BA4, 0x10},
	855	+ {0x3BA5, 0x14},
	856	+ {0x3BA6, 0x18},
	857	+ {0x3BA7, 0x1A},
	858	+ {0x3BA8, 0x1A},
	859	+ {0x3BA9, 0x1A},
	860	+ {0x3BAC, 0xED},
	861	+ {0x3BAD, 0x01},
	862	+ {0x3BAE, 0xF6},
	863	+ {0x3BAF, 0x02},
	864	+ {0x3BB0, 0xA2},
	865	+ {0x3BB1, 0x03},
	866	+ {0x3BB2, 0xE0},
	867	+ {0x3BB3, 0x03},
	868	+ {0x3BB4, 0xE0},
	869	+ {0x3BB5, 0x03},
	870	+ {0x3BB6, 0xE0},
	871	+ {0x3BB7, 0x03},
	872	+ {0x3BB8, 0xE0},
	873	+ {0x3BBA, 0xE0},
	874	+ {0x3BBC, 0xDA},
	875	+ {0x3BBE, 0x88},
	876	+ {0x3BC0, 0x44},
	877	+ {0x3BC2, 0x7B},
	878	+ {0x3BC4, 0xA2},
	879	+ {0x3BC8, 0xBD},
	880	+ {0x3BCA, 0xBD},
	881	+ {0x4001, 0x01},
	882	+ {0x4004, 0xC0},
	883	+ {0x4005, 0x06},
	884	+ {0x400C, 0x00},
	885	+ {0x4018, 0x7F},
	886	+ {0x401A, 0x37},
	887	+ {0x401C, 0x37},
	888	+ {0x401E, 0xF7},
	889	+ {0x401F, 0x00},
	890	+ {0x4020, 0x3F},
	891	+ {0x4022, 0x6F},
	892	+ {0x4024, 0x3F},
	893	+ {0x4026, 0x5F},
	894	+ {0x4028, 0x2F},
	895	+ {0x4074, 0x01},
	896	+ {0x3002, 0x00},
	897	+ //{0x3000, 0x00},
	898	+ {REG_DELAY, 0x1E},//wait_ms(30)
	899	+ {REG_NULL, 0x00},
	900	+};
	901	+
	902	+/*
	903	+ * Xclk 27Mhz
	904	+ * 90.059fps
	905	+ * CSI-2_2lane
	906	+ * AD:10bit Output:12bit
	907	+ * 2376Mbps
	908	+ * Master Mode
	909	+ * Time 9.999ms Gain:6dB
	910	+ * 2568x1440 2/2-line binning & Window cropping
	911	+ */
	912	+static __maybe_unused const struct regval imx415_linear_12bit_1284x720_2376M_regs_2lane[] = {
	913	+ {0x3008, 0x5D},
	914	+ {0x300A, 0x42},
	915	+ {0x301C, 0x04},
	916	+ {0x3020, 0x01},
	917	+ {0x3021, 0x01},
	918	+ {0x3022, 0x01},
	919	+ {0x3024, 0xAB},
	920	+ {0x3025, 0x07},
	921	+ {0x3028, 0xA4},
	922	+ {0x3029, 0x01},
	923	+ {0x3031, 0x00},
	924	+ {0x3033, 0x00},
	925	+ {0x3040, 0x88},
	926	+ {0x3041, 0x02},
	927	+ {0x3042, 0x08},
	928	+ {0x3043, 0x0A},
	929	+ {0x3044, 0xF0},
	930	+ {0x3045, 0x02},
	931	+ {0x3046, 0x40},
	932	+ {0x3047, 0x0B},
	933	+ {0x3050, 0xC4},
	934	+ {0x3090, 0x14},
	935	+ {0x30C1, 0x00},
	936	+ {0x30D9, 0x02},
	937	+ {0x30DA, 0x01},
	938	+ {0x3116, 0x23},
	939	+ {0x3118, 0x08},
	940	+ {0x3119, 0x01},
	941	+ {0x311A, 0xE7},
	942	+ {0x311E, 0x23},
	943	+ {0x32D4, 0x21},
	944	+ {0x32EC, 0xA1},
	945	+ {0x344C, 0x2B},
	946	+ {0x344D, 0x01},
	947	+ {0x344E, 0xED},
	948	+ {0x344F, 0x01},
	949	+ {0x3450, 0xF6},
	950	+ {0x3451, 0x02},
	951	+ {0x3452, 0x7F},
	952	+ {0x3453, 0x03},
	953	+ {0x358A, 0x04},
	954	+ {0x35A1, 0x02},
	955	+ {0x35EC, 0x27},
	956	+ {0x35EE, 0x8D},
	957	+ {0x35F0, 0x8D},
	958	+ {0x35F2, 0x29},
	959	+ {0x36BC, 0x0C},
	960	+ {0x36CC, 0x53},
	961	+ {0x36CD, 0x00},
	962	+ {0x36CE, 0x3C},
	963	+ {0x36D0, 0x8C},
	964	+ {0x36D1, 0x00},
	965	+ {0x36D2, 0x71},
	966	+ {0x36D4, 0x3C},
	967	+ {0x36D6, 0x53},
	968	+ {0x36D7, 0x00},
	969	+ {0x36D8, 0x71},
	970	+ {0x36DA, 0x8C},
	971	+ {0x36DB, 0x00},
	972	+ {0x3701, 0x00},
	973	+ {0x3720, 0x00},
	974	+ {0x3724, 0x02},
	975	+ {0x3726, 0x02},
	976	+ {0x3732, 0x02},
	977	+ {0x3734, 0x03},
	978	+ {0x3736, 0x03},
	979	+ {0x3742, 0x03},
	980	+ {0x3862, 0xE0},
	981	+ {0x38CC, 0x30},
	982	+ {0x38CD, 0x2F},
	983	+ {0x395C, 0x0C},
	984	+ {0x39A4, 0x07},
	985	+ {0x39A8, 0x32},
	986	+ {0x39AA, 0x32},
	987	+ {0x39AC, 0x32},
	988	+ {0x39AE, 0x32},
	989	+ {0x39B0, 0x32},
	990	+ {0x39B2, 0x2F},
	991	+ {0x39B4, 0x2D},
	992	+ {0x39B6, 0x28},
	993	+ {0x39B8, 0x30},
	994	+ {0x39BA, 0x30},
	995	+ {0x39BC, 0x30},
	996	+ {0x39BE, 0x30},
	997	+ {0x39C0, 0x30},
	998	+ {0x39C2, 0x2E},
	999	+ {0x39C4, 0x2B},
	1000	+ {0x39C6, 0x25},
	1001	+ {0x3A42, 0xD1},
	1002	+ {0x3A4C, 0x77},
	1003	+ {0x3AE0, 0x02},
	1004	+ {0x3AEC, 0x0C},
	1005	+ {0x3B00, 0x2E},
	1006	+ {0x3B06, 0x29},
	1007	+ {0x3B98, 0x25},
	1008	+ {0x3B99, 0x21},
	1009	+ {0x3B9B, 0x13},
	1010	+ {0x3B9C, 0x13},
	1011	+ {0x3B9D, 0x13},
	1012	+ {0x3B9E, 0x13},
	1013	+ {0x3BA1, 0x00},
	1014	+ {0x3BA2, 0x06},
	1015	+ {0x3BA3, 0x0B},
	1016	+ {0x3BA4, 0x10},
	1017	+ {0x3BA5, 0x14},
	1018	+ {0x3BA6, 0x18},
	1019	+ {0x3BA7, 0x1A},
	1020	+ {0x3BA8, 0x1A},
	1021	+ {0x3BA9, 0x1A},
	1022	+ {0x3BAC, 0xED},
	1023	+ {0x3BAD, 0x01},
	1024	+ {0x3BAE, 0xF6},
	1025	+ {0x3BAF, 0x02},
	1026	+ {0x3BB0, 0xA2},
	1027	+ {0x3BB1, 0x03},
	1028	+ {0x3BB2, 0xE0},
	1029	+ {0x3BB3, 0x03},
	1030	+ {0x3BB4, 0xE0},
	1031	+ {0x3BB5, 0x03},
	1032	+ {0x3BB6, 0xE0},
	1033	+ {0x3BB7, 0x03},
	1034	+ {0x3BB8, 0xE0},
	1035	+ {0x3BBA, 0xE0},
	1036	+ {0x3BBC, 0xDA},
	1037	+ {0x3BBE, 0x88},
	1038	+ {0x3BC0, 0x44},
	1039	+ {0x3BC2, 0x7B},
	1040	+ {0x3BC4, 0xA2},
	1041	+ {0x3BC8, 0xBD},
	1042	+ {0x3BCA, 0xBD},
	1043	+ {0x4001, 0x01},
	1044	+ {0x4004, 0xC0},
	1045	+ {0x4005, 0x06},
	1046	+ {0x4018, 0xE7},
	1047	+ {0x401A, 0x8F},
	1048	+ {0x401C, 0x8F},
	1049	+ {0x401E, 0x7F},
	1050	+ {0x401F, 0x02},
	1051	+ {0x4020, 0x97},
	1052	+ {0x4022, 0x0F},
	1053	+ {0x4023, 0x01},
	1054	+ {0x4024, 0x97},
	1055	+ {0x4026, 0xF7},
	1056	+ {0x4028, 0x7F},
	1057	+ {0x3002, 0x00},
	1058	+ //{0x3000, 0x00},
	1059	+ {REG_DELAY, 0x1E},//wait_ms(30)
	1060	+ {REG_NULL, 0x00},
	1061	+};
	1062	+
	1063	+/*
749	1064	* The width and height must be configured to be
750	1065	* the same as the current output resolution of the sensor.
751	1066	* The input width of the isp needs to be 16 aligned.
..	..	@@ -779,6 +1094,7 @@
779	1094	.mipi_freq_idx = 1,
780	1095	.bpp = 10,
781	1096	.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	1097	+ .xvclk = IMX415_XVCLK_FREQ_37M,
782	1098	},
783	1099	{
784	1100	.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
..	..	@@ -804,6 +1120,7 @@
804	1120	.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
805	1121	.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
806	1122	.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
	1123	+ .xvclk = IMX415_XVCLK_FREQ_37M,
807	1124	},
808	1125	{
809	1126	.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
..	..	@@ -829,6 +1146,7 @@
829	1146	.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
830	1147	.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
831	1148	.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
	1149	+ .xvclk = IMX415_XVCLK_FREQ_37M,
832	1150	},
833	1151	{
834	1152	.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
..	..	@@ -854,6 +1172,7 @@
854	1172	.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
855	1173	.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
856	1174	.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
	1175	+ .xvclk = IMX415_XVCLK_FREQ_37M,
857	1176	},
858	1177	{
859	1178	/* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */
..	..	@@ -873,6 +1192,7 @@
873	1192	.mipi_freq_idx = 1,
874	1193	.bpp = 12,
875	1194	.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	1195	+ .xvclk = IMX415_XVCLK_FREQ_37M,
876	1196	},
877	1197	{
878	1198	.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
..	..	@@ -898,6 +1218,7 @@
898	1218	.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
899	1219	.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
900	1220	.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
	1221	+ .xvclk = IMX415_XVCLK_FREQ_37M,
901	1222	},
902	1223	{
903	1224	.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
..	..	@@ -923,6 +1244,7 @@
923	1244	.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
924	1245	.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
925	1246	.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
	1247	+ .xvclk = IMX415_XVCLK_FREQ_37M,
926	1248	},
927	1249	{
928	1250	.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
..	..	@@ -941,6 +1263,7 @@
941	1263	.mipi_freq_idx = 0,
942	1264	.bpp = 12,
943	1265	.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	1266	+ .xvclk = IMX415_XVCLK_FREQ_37M,
944	1267	},
945	1268	{
946	1269	.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
..	..	@@ -966,6 +1289,50 @@
966	1289	.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
967	1290	.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
968	1291	.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
	1292	+ .xvclk = IMX415_XVCLK_FREQ_37M,
	1293	+ },
	1294	+};
	1295	+
	1296	+static const struct imx415_mode supported_modes_2lane[] = {
	1297	+ {
	1298	+ /* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */
	1299	+ .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
	1300	+ .width = 3864,
	1301	+ .height = 2192,
	1302	+ .max_fps = {
	1303	+ .numerator = 10000,
	1304	+ .denominator = 150000,
	1305	+ },
	1306	+ .exp_def = 0x08ca - 0x08,
	1307	+ .hts_def = 0x0898 * IMX415_2LANES * 2,
	1308	+ .vts_def = 0x08ca,
	1309	+ .global_reg_list = NULL,
	1310	+ .reg_list = imx415_linear_12bit_3864x2192_891M_regs_2lane,
	1311	+ .hdr_mode = NO_HDR,
	1312	+ .mipi_freq_idx = 1,
	1313	+ .bpp = 12,
	1314	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	1315	+ .xvclk = IMX415_XVCLK_FREQ_27M,
	1316	+ },
	1317	+ {
	1318	+ /* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */
	1319	+ .bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
	1320	+ .width = 1284,
	1321	+ .height = 720,
	1322	+ .max_fps = {
	1323	+ .numerator = 10000,
	1324	+ .denominator = 900000,
	1325	+ },
	1326	+ .exp_def = 0x07AB-8,
	1327	+ .hts_def = 0x01A4 * IMX415_2LANES * 2,
	1328	+ .vts_def = 0x07AB,
	1329	+ .global_reg_list = NULL,
	1330	+ .reg_list = imx415_linear_12bit_1284x720_2376M_regs_2lane,
	1331	+ .hdr_mode = NO_HDR,
	1332	+ .mipi_freq_idx = 4,
	1333	+ .bpp = 12,
	1334	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	1335	+ .xvclk = IMX415_XVCLK_FREQ_27M,
969	1336	},
970	1337	};
971	1338
..	..	@@ -974,6 +1341,7 @@
974	1341	MIPI_FREQ_446M,
975	1342	MIPI_FREQ_743M,
976	1343	MIPI_FREQ_891M,
	1344	+ MIPI_FREQ_1188M,
977	1345	};
978	1346
979	1347	/* Write registers up to 4 at a time */
..	..	@@ -1010,10 +1378,18 @@
1010	1378	{
1011	1379	u32 i;
1012	1380	int ret = 0;
1013		-
	1381	+ if (!regs) {
	1382	+ dev_err(&client->dev, "write reg array error\n");
	1383	+ return ret;
	1384	+ }
1014	1385	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
1015		- ret = imx415_write_reg(client, regs[i].addr,
1016		- IMX415_REG_VALUE_08BIT, regs[i].val);
	1386	+ if (regs[i].addr == REG_DELAY) {
	1387	+ usleep_range(regs[i].val * 1000, regs[i].val * 1000 + 500);
	1388	+ dev_info(&client->dev, "write reg array, sleep %dms\n", regs[i].val);
	1389	+ } else {
	1390	+ ret = imx415_write_reg(client, regs[i].addr,
	1391	+ IMX415_REG_VALUE_08BIT, regs[i].val);
	1392	+ }
1017	1393	}
1018	1394	return ret;
1019	1395	}
..	..	@@ -1070,9 +1446,9 @@
1070	1446	unsigned int i;
1071	1447
1072	1448	for (i = 0; i < imx415->cfg_num; i++) {
1073		- dist = imx415_get_reso_dist(&supported_modes[i], framefmt);
	1449	+ dist = imx415_get_reso_dist(&imx415->supported_modes[i], framefmt);
1074	1450	if ((cur_best_fit_dist == -1 \|\| dist < cur_best_fit_dist) &&
1075		- supported_modes[i].bus_fmt == framefmt->code) {
	1451	+ imx415->supported_modes[i].bus_fmt == framefmt->code) {
1076	1452	cur_best_fit_dist = dist;
1077	1453	cur_best_fit = i;
1078	1454	}
..	..	@@ -1080,7 +1456,7 @@
1080	1456	dev_info(&imx415->client->dev, "%s: cur_best_fit(%d)",
1081	1457	__func__, cur_best_fit);
1082	1458
1083		- return &supported_modes[cur_best_fit];
	1459	+ return &imx415->supported_modes[cur_best_fit];
1084	1460	}
1085	1461
1086	1462	static int __imx415_power_on(struct imx415 *imx415);
..	..	@@ -1094,8 +1470,8 @@
1094	1470	}
1095	1471	imx415->cur_mode = mode;
1096	1472	imx415->cur_vts = imx415->cur_mode->vts_def;
1097		- dev_dbg(&imx415->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
1098		- mode->width, mode->height, mode->hdr_mode);
	1473	+ dev_info(&imx415->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d, bpp: %d\n",
	1474	+ mode->width, mode->height, mode->hdr_mode, mode->bpp);
1099	1475	}
1100	1476
1101	1477	static int imx415_set_fmt(struct v4l2_subdev *sd,
..	..	@@ -1106,6 +1482,7 @@
1106	1482	const struct imx415_mode *mode;
1107	1483	s64 h_blank, vblank_def, vblank_min;
1108	1484	u64 pixel_rate = 0;
	1485	+ u8 lanes = imx415->bus_cfg.bus.mipi_csi2.num_data_lanes;
1109	1486
1110	1487	mutex_lock(&imx415->mutex);
1111	1488
..	..	@@ -1134,7 +1511,8 @@
1134	1511	1, vblank_def);
1135	1512	__v4l2_ctrl_s_ctrl(imx415->vblank, vblank_def);
1136	1513	__v4l2_ctrl_s_ctrl(imx415->link_freq, mode->mipi_freq_idx);
1137		- pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX415_4LANES;
	1514	+ pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
	1515	+ mode->bpp * 2 * lanes;
1138	1516	__v4l2_ctrl_s_ctrl_int64(imx415->pixel_rate,
1139	1517	pixel_rate);
1140	1518	}
..	..	@@ -1185,7 +1563,7 @@
1185	1563	if (code->index >= imx415->cfg_num)
1186	1564	return -EINVAL;
1187	1565
1188		- code->code = supported_modes[code->index].bus_fmt;
	1566	+ code->code = imx415->supported_modes[code->index].bus_fmt;
1189	1567
1190	1568	return 0;
1191	1569	}
..	..	@@ -1199,13 +1577,13 @@
1199	1577	if (fse->index >= imx415->cfg_num)
1200	1578	return -EINVAL;
1201	1579
1202		- if (fse->code != supported_modes[fse->index].bus_fmt)
	1580	+ if (fse->code != imx415->supported_modes[fse->index].bus_fmt)
1203	1581	return -EINVAL;
1204	1582
1205		- fse->min_width = supported_modes[fse->index].width;
1206		- fse->max_width = supported_modes[fse->index].width;
1207		- fse->max_height = supported_modes[fse->index].height;
1208		- fse->min_height = supported_modes[fse->index].height;
	1583	+ fse->min_width = imx415->supported_modes[fse->index].width;
	1584	+ fse->max_width = imx415->supported_modes[fse->index].width;
	1585	+ fse->max_height = imx415->supported_modes[fse->index].height;
	1586	+ fse->min_height = imx415->supported_modes[fse->index].height;
1209	1587
1210	1588	return 0;
1211	1589	}
..	..	@@ -1227,8 +1605,9 @@
1227	1605	struct imx415 *imx415 = to_imx415(sd);
1228	1606	const struct imx415_mode *mode = imx415->cur_mode;
1229	1607	u32 val = 0;
	1608	+ u8 lanes = imx415->bus_cfg.bus.mipi_csi2.num_data_lanes;
1230	1609
1231		- val = 1 << (IMX415_4LANES - 1) \|
	1610	+ val = 1 << (lanes - 1) \|
1232	1611	V4L2_MBUS_CSI2_CHANNEL_0 \|
1233	1612	V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1234	1613	if (mode->hdr_mode != NO_HDR)
..	..	@@ -1687,6 +2066,7 @@
1687	2066	const struct imx415_mode *mode;
1688	2067	u64 pixel_rate = 0;
1689	2068	struct rkmodule_csi_dphy_param *dphy_param;
	2069	+ u8 lanes = imx415->bus_cfg.bus.mipi_csi2.num_data_lanes;
1690	2070
1691	2071	switch (cmd) {
1692	2072	case PREISP_CMD_SET_HDRAE_EXP:
..	..	@@ -1708,10 +2088,11 @@
1708	2088	w = imx415->cur_mode->width;
1709	2089	h = imx415->cur_mode->height;
1710	2090	for (i = 0; i < imx415->cfg_num; i++) {
1711		- if (w == supported_modes[i].width &&
1712		- h == supported_modes[i].height &&
1713		- supported_modes[i].hdr_mode == hdr->hdr_mode) {
1714		- imx415_change_mode(imx415, &supported_modes[i]);
	2091	+ if (w == imx415->supported_modes[i].width &&
	2092	+ h == imx415->supported_modes[i].height &&
	2093	+ imx415->supported_modes[i].hdr_mode == hdr->hdr_mode) {
	2094	+ dev_info(&imx415->client->dev, "set hdr cfg, set mode to %d\n", i);
	2095	+ imx415_change_mode(imx415, &imx415->supported_modes[i]);
1715	2096	break;
1716	2097	}
1717	2098	}
..	..	@@ -1741,7 +2122,8 @@
1741	2122	IMX415_VTS_MAX - mode->height,
1742	2123	1, h);
1743	2124	__v4l2_ctrl_s_ctrl(imx415->link_freq, mode->mipi_freq_idx);
1744		- pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX415_4LANES;
	2125	+ pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
	2126	+ mode->bpp * 2 * lanes;
1745	2127	__v4l2_ctrl_s_ctrl_int64(imx415->pixel_rate,
1746	2128	pixel_rate);
1747	2129	mutex_unlock(&imx415->mutex);
..	..	@@ -2045,10 +2427,6 @@
2045	2427	{
2046	2428	int ret;
2047	2429	struct device *dev = &imx415->client->dev;
2048		-
2049		- if (imx415->is_thunderboot)
2050		- return 0;
2051		-
2052	2430	if (!IS_ERR_OR_NULL(imx415->pins_default)) {
2053	2431	ret = pinctrl_select_state(imx415->pinctrl,
2054	2432	imx415->pins_default);
..	..	@@ -2056,26 +2434,28 @@
2056	2434	dev_err(dev, "could not set pins\n");
2057	2435	}
2058	2436
2059		- ret = regulator_bulk_enable(IMX415_NUM_SUPPLIES, imx415->supplies);
2060		- if (ret < 0) {
2061		- dev_err(dev, "Failed to enable regulators\n");
2062		- goto err_pinctrl;
2063		- }
2064		- if (!IS_ERR(imx415->power_gpio))
2065		- gpiod_direction_output(imx415->power_gpio, 1);
2066		- /* At least 500ns between power raising and XCLR */
2067		- /* fix power on timing if insmod this ko */
2068		- usleep_range(10 * 1000, 20 * 1000);
2069		- if (!IS_ERR(imx415->reset_gpio))
2070		- gpiod_direction_output(imx415->reset_gpio, 0);
	2437	+ if (!imx415->is_thunderboot) {
	2438	+ ret = regulator_bulk_enable(IMX415_NUM_SUPPLIES, imx415->supplies);
	2439	+ if (ret < 0) {
	2440	+ dev_err(dev, "Failed to enable regulators\n");
	2441	+ goto err_pinctrl;
	2442	+ }
	2443	+ if (!IS_ERR(imx415->power_gpio))
	2444	+ gpiod_direction_output(imx415->power_gpio, 1);
	2445	+ /* At least 500ns between power raising and XCLR */
	2446	+ /* fix power on timing if insmod this ko */
	2447	+ usleep_range(10 * 1000, 20 * 1000);
	2448	+ if (!IS_ERR(imx415->reset_gpio))
	2449	+ gpiod_direction_output(imx415->reset_gpio, 0);
2071	2450
2072		- /* At least 1us between XCLR and clk */
2073		- /* fix power on timing if insmod this ko */
2074		- usleep_range(10 * 1000, 20 * 1000);
2075		- ret = clk_set_rate(imx415->xvclk, IMX415_XVCLK_FREQ_37M);
	2451	+ /* At least 1us between XCLR and clk */
	2452	+ /* fix power on timing if insmod this ko */
	2453	+ usleep_range(10 * 1000, 20 * 1000);
	2454	+ }
	2455	+ ret = clk_set_rate(imx415->xvclk, imx415->cur_mode->xvclk);
2076	2456	if (ret < 0)
2077	2457	dev_warn(dev, "Failed to set xvclk rate\n");
2078		- if (clk_get_rate(imx415->xvclk) != IMX415_XVCLK_FREQ_37M)
	2458	+ if (clk_get_rate(imx415->xvclk) != imx415->cur_mode->xvclk)
2079	2459	dev_warn(dev, "xvclk mismatched\n");
2080	2460	ret = clk_prepare_enable(imx415->xvclk);
2081	2461	if (ret < 0) {
..	..	@@ -2084,7 +2464,8 @@
2084	2464	}
2085	2465
2086	2466	/* At least 20us between XCLR and I2C communication */
2087		- usleep_range(201000, 301000);
	2467	+ if (!imx415->is_thunderboot)
	2468	+ usleep_range(201000, 301000);
2088	2469
2089	2470	return 0;
2090	2471
..	..	@@ -2154,7 +2535,7 @@
2154	2535	struct imx415 *imx415 = to_imx415(sd);
2155	2536	struct v4l2_mbus_framefmt *try_fmt =
2156	2537	v4l2_subdev_get_try_format(sd, fh->pad, 0);
2157		- const struct imx415_mode *def_mode = &supported_modes[0];
	2538	+ const struct imx415_mode *def_mode = &imx415->supported_modes[0];
2158	2539
2159	2540	mutex_lock(&imx415->mutex);
2160	2541	/* Initialize try_fmt */
..	..	@@ -2179,11 +2560,11 @@
2179	2560	if (fie->index >= imx415->cfg_num)
2180	2561	return -EINVAL;
2181	2562
2182		- fie->code = supported_modes[fie->index].bus_fmt;
2183		- fie->width = supported_modes[fie->index].width;
2184		- fie->height = supported_modes[fie->index].height;
2185		- fie->interval = supported_modes[fie->index].max_fps;
2186		- fie->reserved[0] = supported_modes[fie->index].hdr_mode;
	2563	+ fie->code = imx415->supported_modes[fie->index].bus_fmt;
	2564	+ fie->width = imx415->supported_modes[fie->index].width;
	2565	+ fie->height = imx415->supported_modes[fie->index].height;
	2566	+ fie->interval = imx415->supported_modes[fie->index].max_fps;
	2567	+ fie->reserved[0] = imx415->supported_modes[fie->index].hdr_mode;
2187	2568	return 0;
2188	2569	}
2189	2570
..	..	@@ -2401,8 +2782,10 @@
2401	2782	struct v4l2_ctrl_handler *handler;
2402	2783	s64 exposure_max, vblank_def;
2403	2784	u64 pixel_rate;
	2785	+ u64 max_pixel_rate;
2404	2786	u32 h_blank;
2405	2787	int ret;
	2788	+ u8 lanes = imx415->bus_cfg.bus.mipi_csi2.num_data_lanes;
2406	2789
2407	2790	handler = &imx415->ctrl_handler;
2408	2791	mode = imx415->cur_mode;
..	..	@@ -2418,9 +2801,10 @@
2418	2801	v4l2_ctrl_s_ctrl(imx415->link_freq, mode->mipi_freq_idx);
2419	2802
2420	2803	/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2421		- pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX415_4LANES;
	2804	+ pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * lanes;
	2805	+ max_pixel_rate = MIPI_FREQ_1188M / mode->bpp * 2 * lanes;
2422	2806	imx415->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
2423		- V4L2_CID_PIXEL_RATE, 0, IMX415_MAX_PIXEL_RATE,
	2807	+ V4L2_CID_PIXEL_RATE, 0, max_pixel_rate,
2424	2808	1, pixel_rate);
2425	2809
2426	2810	h_blank = mode->hts_def - mode->width;
..	..	@@ -2511,6 +2895,7 @@
2511	2895	struct device_node *node = dev->of_node;
2512	2896	struct imx415 *imx415;
2513	2897	struct v4l2_subdev *sd;
	2898	+ struct device_node *endpoint;
2514	2899	char facing[2];
2515	2900	int ret;
2516	2901	u32 i, hdr_mode = 0;
..	..	@@ -2542,16 +2927,41 @@
2542	2927	hdr_mode = NO_HDR;
2543	2928	dev_warn(dev, " Get hdr mode failed! no hdr default\n");
2544	2929	}
	2930	+
	2931	+ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
	2932	+ if (!endpoint) {
	2933	+ dev_err(dev, "Failed to get endpoint\n");
	2934	+ return -EINVAL;
	2935	+ }
	2936	+
	2937	+ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
	2938	+ &imx415->bus_cfg);
	2939	+ of_node_put(endpoint);
	2940	+ if (ret) {
	2941	+ dev_err(dev, "Failed to get bus config\n");
	2942	+ return -EINVAL;
	2943	+ }
	2944	+
2545	2945	imx415->client = client;
2546		- imx415->cfg_num = ARRAY_SIZE(supported_modes);
	2946	+ if (imx415->bus_cfg.bus.mipi_csi2.num_data_lanes == IMX415_4LANES) {
	2947	+ imx415->supported_modes = supported_modes;
	2948	+ imx415->cfg_num = ARRAY_SIZE(supported_modes);
	2949	+ } else {
	2950	+ imx415->supported_modes = supported_modes_2lane;
	2951	+ imx415->cfg_num = ARRAY_SIZE(supported_modes_2lane);
	2952	+ }
	2953	+ dev_info(dev, "detect imx415 lane %d\n",
	2954	+ imx415->bus_cfg.bus.mipi_csi2.num_data_lanes);
	2955	+
2547	2956	for (i = 0; i < imx415->cfg_num; i++) {
2548		- if (hdr_mode == supported_modes[i].hdr_mode) {
2549		- imx415->cur_mode = &supported_modes[i];
	2957	+ if (hdr_mode == imx415->supported_modes[i].hdr_mode) {
	2958	+ imx415->cur_mode = &imx415->supported_modes[i];
2550	2959	break;
2551	2960	}
2552	2961	}
2553	2962
2554		- imx415->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
	2963	+ of_property_read_u32(node, RKMODULE_CAMERA_FASTBOOT_ENABLE,
	2964	+ &imx415->is_thunderboot);
2555	2965
2556	2966	imx415->xvclk = devm_clk_get(dev, "xvclk");
2557	2967	if (IS_ERR(imx415->xvclk)) {