forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/media/i2c/imx335.c
....@@ -11,7 +11,6 @@
1111  * V0.0X01.0X04 fix hdr ae error
1212  * V0.0X01.0X05 add quick stream on/off
1313  * V0.0X01.0X06 Increase hdr exposure restrictions
14
- * V0.0X01.0X07 add binning resolution
1514  */
1615 
1716 #define DEBUG
....@@ -34,14 +33,13 @@
3433 #include <linux/pinctrl/consumer.h>
3534 #include <linux/rk-preisp.h>
3635 
37
-#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x07)
36
+#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x06)
3837 
3938 #ifndef V4L2_CID_DIGITAL_GAIN
4039 #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
4140 #endif
4241 
4342 #define MIPI_FREQ_594M			594000000
44
-#define MIPI_FREQ_445M			445000000
4543 
4644 #define IMX335_4LANES			4
4745 
....@@ -160,14 +158,6 @@
160158 
161159 #define IMX335_NUM_SUPPLIES ARRAY_SIZE(imx335_supply_names)
162160 
163
-enum imx335_max_pad {
164
-	PAD0, /* link to isp */
165
-	PAD1, /* link to csi wr0 | hdr x2:L x3:M */
166
-	PAD2, /* link to csi wr1 | hdr      x3:L */
167
-	PAD3, /* link to csi wr2 | hdr x2:M x3:S */
168
-	PAD_MAX,
169
-};
170
-
171161 struct regval {
172162 	u16 addr;
173163 	u8 val;
....@@ -182,7 +172,6 @@
182172 	u32 vts_def;
183173 	u32 exp_def;
184174 	u32 bpp;
185
-	u32 mipi_freq_idx;
186175 	const struct regval *reg_list;
187176 	u32 hdr_mode;
188177 	u32 vc[PAD_MAX];
....@@ -227,157 +216,8 @@
227216 /*
228217  * Xclk 37.125Mhz
229218  */
230
-static const struct regval imx335_linear_12bit_1296x972_regs[] = {
231
-	{0x3002, 0x00},
232
-	{0x3018, 0x01},
233
-	{0x300C, 0x5B},
234
-	{0x300D, 0x40},
235
-	{0x3034, 0x26},
236
-	{0x3035, 0x02},
237
-	{0x3048, 0x00},
238
-	{0x3049, 0x00},
239
-	{0x304A, 0x03},
240
-	{0x304B, 0x01},
241
-	{0x304C, 0x14},
242
-	{0x3050, 0x00},
243
-	{0x3056, 0xd8},
244
-	{0x3057, 0x03},
245
-	{0x3058, 0x4E},
246
-	{0x3059, 0x0C},
247
-	{0x305C, 0x12},
248
-	{0x3060, 0xE8},
249
-	{0x3061, 0x00},
250
-	{0x3068, 0xce},
251
-	{0x3069, 0x00},
252
-	{0x306C, 0x68},
253
-	{0x306D, 0x06},
254
-	{0x3072, 0x30},
255
-	{0x3074, 0xa8},
256
-	{0x3075, 0x00},
257
-	{0x3076, 0x60},
258
-	{0x3077, 0x0f},
259
-	{0x3078, 0x04},
260
-	{0x3079, 0xFD},
261
-	{0x307A, 0x04},
262
-	{0x307B, 0xFE},//binning
263
-	{0x307C, 0x04},
264
-	{0x307D, 0xFB},
265
-	{0x307E, 0x04},
266
-	{0x307F, 0x02}, /* Each frame gain adjustment disabled in linear mode */
267
-	{0x3080, 0x04},
268
-	{0x3081, 0xFD},
269
-	{0x3082, 0x04},//binning
270
-	{0x3083, 0xFE},
271
-	{0x3084, 0x04},
272
-	{0x3085, 0xFB},
273
-	{0x3086, 0x04},
274
-	{0x3087, 0x02},
275
-	{0x30A4, 0x77},
276
-	{0x30A8, 0x20},
277
-	{0x30A9, 0x00},
278
-	{0x30AC, 0x08},
279
-	{0x30AD, 0x08},
280
-	{0x30B0, 0x20},
281
-	{0x30B1, 0x00},
282
-	{0x30B4, 0x10},
283
-	{0x30B5, 0x10},
284
-	{0x30E8, 0x14},
285
-	{0x3112, 0x10},
286
-	{0x3116, 0x10},
287
-	{0x314C, 0xC0},
288
-	{0x315A, 0x06},
289
-	{0x316A, 0x7E},
290
-	{0x3199, 0x30},
291
-	{0x319D, 0x01},
292
-	{0x319E, 0x02},
293
-	{0x31A1, 0x00},
294
-	{0x31D7, 0x00},
295
-	{0x3200, 0x01},
296
-	{0x3288, 0x21},
297
-	{0x328A, 0x02},
298
-	{0x3300, 0x01},
299
-	{0x3414, 0x05},
300
-	{0x3416, 0x18},
301
-	{0x341C, 0xFF},
302
-	{0x341D, 0x01},
303
-	{0x3648, 0x01},
304
-	{0x364A, 0x04},
305
-	{0x364C, 0x04},
306
-	{0x3678, 0x01},
307
-	{0x367C, 0x31},
308
-	{0x367E, 0x31},
309
-	{0x3706, 0x10},
310
-	{0x3708, 0x03},
311
-	{0x3714, 0x02},
312
-	{0x3715, 0x02},
313
-	{0x3716, 0x01},
314
-	{0x3717, 0x03},
315
-	{0x371C, 0x3D},
316
-	{0x371D, 0x3F},
317
-	{0x372C, 0x00},
318
-	{0x372D, 0x00},
319
-	{0x372E, 0x46},
320
-	{0x372F, 0x00},
321
-	{0x3730, 0x89},
322
-	{0x3731, 0x00},
323
-	{0x3732, 0x08},
324
-	{0x3733, 0x01},
325
-	{0x3734, 0xFE},
326
-	{0x3735, 0x05},
327
-	{0x3740, 0x02},
328
-	{0x375D, 0x00},
329
-	{0x375E, 0x00},
330
-	{0x375F, 0x11},
331
-	{0x3760, 0x01},
332
-	{0x3768, 0x1B},
333
-	{0x3769, 0x1B},
334
-	{0x376A, 0x1B},
335
-	{0x376B, 0x1B},
336
-	{0x376C, 0x1A},
337
-	{0x376D, 0x17},
338
-	{0x376E, 0x0F},
339
-	{0x3776, 0x00},
340
-	{0x3777, 0x00},
341
-	{0x3778, 0x46},
342
-	{0x3779, 0x00},
343
-	{0x377A, 0x89},
344
-	{0x377B, 0x00},
345
-	{0x377C, 0x08},
346
-	{0x377D, 0x01},
347
-	{0x377E, 0x23},
348
-	{0x377F, 0x02},
349
-	{0x3780, 0xD9},
350
-	{0x3781, 0x03},
351
-	{0x3782, 0xF5},
352
-	{0x3783, 0x06},
353
-	{0x3784, 0xA5},
354
-	{0x3788, 0x0F},
355
-	{0x378A, 0xD9},
356
-	{0x378B, 0x03},
357
-	{0x378C, 0xEB},
358
-	{0x378D, 0x05},
359
-	{0x378E, 0x87},
360
-	{0x378F, 0x06},
361
-	{0x3790, 0xF5},
362
-	{0x3792, 0x43},
363
-	{0x3794, 0x7A},
364
-	{0x3796, 0xA1},
365
-	{0x3A18, 0x7F},
366
-	{0x3A1A, 0x37},
367
-	{0x3A1C, 0x37},
368
-	{0x3A1E, 0xF7},
369
-	{0x3A1F, 0x00},
370
-	{0x3A20, 0x3F},
371
-	{0x3A22, 0x6F},
372
-	{0x3A24, 0x3F},
373
-	{0x3A26, 0x5F},
374
-	{0x3A28, 0x2F},
375
-	{REG_NULL, 0x00},
376
-};
377
-
378219 static const struct regval imx335_linear_10bit_2592x1944_regs[] = {
379220 	{0x3002, 0x00},
380
-	{0x3018, 0x00},
381221 	{0x300C, 0x5B},
382222 	{0x300D, 0x40},
383223 	{0x3034, 0x26},
....@@ -388,8 +228,6 @@
388228 	{0x304B, 0x01},
389229 	{0x304C, 0x14},
390230 	{0x3050, 0x00},
391
-	{0x3056, 0xac},
392
-	{0x3057, 0x07},
393231 	{0x3058, 0x09},
394232 	{0x3059, 0x00},
395233 	{0x305C, 0x12},
....@@ -399,51 +237,15 @@
399237 	{0x3069, 0x00},
400238 	{0x306C, 0x88},
401239 	{0x306D, 0x06},
402
-	{0x3072, 0x28},
403
-	{0x3074, 0xb0},
404
-	{0x3075, 0x00},
405
-	{0x3076, 0x58},
406
-	{0x3077, 0x0f},
407
-	{0x3078, 0x01},
408
-	{0x3079, 0x02},
409
-	{0x307A, 0xff},
410
-	{0x307B, 0x02},
411
-	{0x307C, 0x00},
412
-	{0x307D, 0x00},
413
-	{0x307E, 0x00},
414
-	{0x307F, 0x00},
415
-	{0x3080, 0x01},
416
-	{0x3081, 0x02},
417
-	{0x3082, 0xff},
418
-	{0x3083, 0x02},
419
-	{0x3084, 0x00},
420
-	{0x3085, 0x00},
421
-	{0x3086, 0x00},
422
-	{0x3087, 0x00},
423
-	{0x30A4, 0x33},
424
-	{0x30A8, 0x10},
425
-	{0x30A9, 0x04},
426
-	{0x30AC, 0x00},
427
-	{0x30AD, 0x00},
428
-	{0x30B0, 0x10},
429
-	{0x30B1, 0x08},
430
-	{0x30B4, 0x00},
431
-	{0x30B5, 0x00},
432240 	{0x30E8, 0x00},
433
-	{0x3112, 0x08},
434
-	{0x3116, 0x08},//full
435
-	{0x314C, 0x80},
436241 	{0x315A, 0x02},
437242 	{0x316A, 0x7E},
438
-	{0x3199, 0x00}, /* Each frame gain adjustment disabled in linear mode */
439243 	{0x319D, 0x00},
440
-	{0x319E, 0x01},
441
-	{0x31A1, 0x00},//full
244
+	{0x31A1, 0x00},
442245 	{0x31D7, 0x00},
443
-	{0x3200, 0x01},
246
+	{0x3200, 0x01}, /* Each frame gain adjustment disabed in linear mode */
444247 	{0x3288, 0x21},
445248 	{0x328A, 0x02},
446
-	{0x3300, 0x00},
447249 	{0x3414, 0x05},
448250 	{0x3416, 0x18},
449251 	{0x341C, 0xFF},
....@@ -510,22 +312,11 @@
510312 	{0x3792, 0x43},
511313 	{0x3794, 0x7A},
512314 	{0x3796, 0xA1},
513
-	{0x3A18, 0x8F},
514
-	{0x3A1A, 0x4f},
515
-	{0x3A1C, 0x47},
516
-	{0x3A1E, 0x37},
517
-	{0x3A1F, 0x01},
518
-	{0x3A20, 0x4F},
519
-	{0x3A22, 0x87},
520
-	{0x3A24, 0x4F},
521
-	{0x3A26, 0x7F},
522
-	{0x3A28, 0x3F},
523315 	{REG_NULL, 0x00},
524316 };
525317 
526318 static const struct regval imx335_hdr2_10bit_2592x1944_regs[] = {
527319 	{0x3002, 0x00},
528
-	{0x3018, 0x00},
529320 	{0x300C, 0x5B},
530321 	{0x300D, 0x40},
531322 	{0x3034, 0x13},
....@@ -536,8 +327,6 @@
536327 	{0x304B, 0x03},
537328 	{0x304C, 0x13},
538329 	{0x3050, 0x00},
539
-	{0x3056, 0xac},
540
-	{0x3057, 0x07},
541330 	{0x3058, 0x48},
542331 	{0x3059, 0x12},
543332 	{0x305C, 0x12},
....@@ -547,51 +336,15 @@
547336 	{0x3069, 0x01},
548337 	{0x306C, 0x68},
549338 	{0x306D, 0x06},
550
-	{0x3072, 0x28},
551
-	{0x3074, 0xb0},
552
-	{0x3075, 0x00},
553
-	{0x3076, 0x58},
554
-	{0x3077, 0x0f},
555
-	{0x3078, 0x01},
556
-	{0x3079, 0x02},//full
557
-	{0x307A, 0xff},
558
-	{0x307B, 0x02},
559
-	{0x307C, 0x00},
560
-	{0x307D, 0x00}, /* Each frame gain adjustment EN */
561
-	{0x307E, 0x00},
562
-	{0x307F, 0x00},
563
-	{0x3080, 0x01},//full
564
-	{0x3081, 0x02},
565
-	{0x3082, 0xff},
566
-	{0x3083, 0x02},
567
-	{0x3084, 0x00},
568
-	{0x3085, 0x00},
569
-	{0x3086, 0x00},
570
-	{0x3087, 0x00},
571
-	{0x30A4, 0x33},
572
-	{0x30A8, 0x10},
573
-	{0x30A9, 0x04},
574
-	{0x30AC, 0x00},
575
-	{0x30AD, 0x00},
576
-	{0x30B0, 0x10},
577
-	{0x30B1, 0x08},
578
-	{0x30B4, 0x00},
579
-	{0x30B5, 0x00},
580339 	{0x30E8, 0x00},
581
-	{0x3112, 0x08},
582
-	{0x3116, 0x08},
583
-	{0x314C, 0x80},
584340 	{0x315A, 0x02},
585341 	{0x316A, 0x7E},
586
-	{0x3199, 0x00},
587342 	{0x319D, 0x00},
588
-	{0x319E, 0x01},
589343 	{0x31A1, 0x00},
590344 	{0x31D7, 0x01},
591
-	{0x3200, 0x00},
345
+	{0x3200, 0x00}, /* Each frame gain adjustment EN */
592346 	{0x3288, 0x21},
593347 	{0x328A, 0x02},
594
-	{0x3300, 0x00},
595348 	{0x3414, 0x05},
596349 	{0x3416, 0x18},
597350 	{0x341C, 0xFF},
....@@ -658,22 +411,11 @@
658411 	{0x3792, 0x43},
659412 	{0x3794, 0x7A},
660413 	{0x3796, 0xA1},
661
-	{0x3A18, 0x8F},
662
-	{0x3A1A, 0x4f},
663
-	{0x3A1C, 0x47},
664
-	{0x3A1E, 0x37},
665
-	{0x3A1F, 0x01},
666
-	{0x3A20, 0x4F},
667
-	{0x3A22, 0x87},
668
-	{0x3A24, 0x4F},
669
-	{0x3A26, 0x7F},
670
-	{0x3A28, 0x3F},
671414 	{REG_NULL, 0x00},
672415 };
673416 
674417 static const struct regval imx335_hdr3_10bit_2592x1944_regs[] = {
675418 	{0x3002, 0x00},
676
-	{0x3018, 0x00},
677419 	{0x300C, 0x5B},
678420 	{0x300D, 0x40},
679421 	{0x3034, 0x13},
....@@ -684,8 +426,6 @@
684426 	{0x304B, 0x03},
685427 	{0x304C, 0x13},
686428 	{0x3050, 0x00},
687
-	{0x3056, 0xac},
688
-	{0x3057, 0x07},
689429 	{0x3058, 0xC4},
690430 	{0x3059, 0x3B},
691431 	{0x305C, 0x1A},
....@@ -695,51 +435,15 @@
695435 	{0x3069, 0x01},
696436 	{0x306C, 0x6C},
697437 	{0x306D, 0x01},
698
-	{0x3072, 0x28},
699
-	{0x3074, 0xb0},
700
-	{0x3075, 0x00},
701
-	{0x3076, 0x58},
702
-	{0x3077, 0x0f},
703
-	{0x3078, 0x01},
704
-	{0x3079, 0x02},
705
-	{0x307A, 0xff},
706
-	{0x307B, 0x02},
707
-	{0x307C, 0x00},
708
-	{0x307D, 0x00},
709
-	{0x307E, 0x00},
710
-	{0x307F, 0x00},
711
-	{0x3080, 0x01},
712
-	{0x3081, 0x02},
713
-	{0x3082, 0xff},
714
-	{0x3083, 0x02},
715
-	{0x3084, 0x00},
716
-	{0x3085, 0x00},
717
-	{0x3086, 0x00},
718
-	{0x3087, 0x00},
719
-	{0x30A4, 0x33},
720
-	{0x30A8, 0x10},
721
-	{0x30A9, 0x04},
722
-	{0x30AC, 0x00},
723
-	{0x30AD, 0x00},
724
-	{0x30B0, 0x10},
725
-	{0x30B1, 0x08},
726
-	{0x30B4, 0x00},
727
-	{0x30B5, 0x00},
728438 	{0x30E8, 0x14},
729
-	{0x3112, 0x08},
730
-	{0x3116, 0x08},
731
-	{0x314C, 0x80},
732439 	{0x315A, 0x02},
733440 	{0x316A, 0x7E},
734
-	{0x3199, 0x00},
735441 	{0x319D, 0x00},
736
-	{0x319E, 0x01},
737442 	{0x31A1, 0x00},
738443 	{0x31D7, 0x03},
739
-	{0x3200, 0x00},
444
+	{0x3200, 0x00}, /* Each frame gain adjustment EN */
740445 	{0x3288, 0x21},
741446 	{0x328A, 0x02},
742
-	{0x3300, 0x00},
743447 	{0x3414, 0x05},
744448 	{0x3416, 0x18},
745449 	{0x341C, 0xFF},
....@@ -775,14 +479,14 @@
775479 	{0x3760, 0x01},
776480 	{0x3768, 0x1B},
777481 	{0x3769, 0x1B},
778
-	{0x376A, 0x1B},//full
482
+	{0x376A, 0x1B},
779483 	{0x376B, 0x1B},
780484 	{0x376C, 0x1A},
781485 	{0x376D, 0x17},
782
-	{0x376E, 0x0F}, /* Each frame gain adjustment EN */
486
+	{0x376E, 0x0F},
783487 	{0x3776, 0x00},
784488 	{0x3777, 0x00},
785
-	{0x3778, 0x46},//full
489
+	{0x3778, 0x46},
786490 	{0x3779, 0x00},
787491 	{0x377A, 0x89},
788492 	{0x377B, 0x00},
....@@ -806,16 +510,6 @@
806510 	{0x3792, 0x43},
807511 	{0x3794, 0x7A},
808512 	{0x3796, 0xA1},
809
-	{0x3A18, 0x8F},
810
-	{0x3A1A, 0x4f},
811
-	{0x3A1C, 0x47},
812
-	{0x3A1E, 0x37},
813
-	{0x3A1F, 0x01},
814
-	{0x3A20, 0x4F},
815
-	{0x3A22, 0x87},
816
-	{0x3A24, 0x4F},
817
-	{0x3A26, 0x7F},
818
-	{0x3A28, 0x3F},
819513 	{REG_NULL, 0x00},
820514 };
821515 
....@@ -848,24 +542,6 @@
848542 		.reg_list = imx335_linear_10bit_2592x1944_regs,
849543 		.hdr_mode = NO_HDR,
850544 		.bpp = 10,
851
-		.mipi_freq_idx = 1,
852
-	},
853
-	{
854
-		/* 1H period = 7.4us */
855
-		.bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
856
-		.width = 1308,
857
-		.height = 984,
858
-		.max_fps = {
859
-			.numerator = 10000,
860
-			.denominator = 300000,
861
-		},
862
-		.exp_def = 0x600,
863
-		.hts_def = 0x0226 * IMX335_4LANES * 2,
864
-		.vts_def = 0x1194,
865
-		.reg_list = imx335_linear_12bit_1296x972_regs,
866
-		.hdr_mode = NO_HDR,
867
-		.bpp = 12,
868
-		.mipi_freq_idx = 0,
869545 	},
870546 	{
871547 		/* 1H period = 3.70us */
....@@ -886,7 +562,6 @@
886562 		.reg_list = imx335_hdr2_10bit_2592x1944_regs,
887563 		.hdr_mode = HDR_X2,
888564 		.bpp = 10,
889
-		.mipi_freq_idx = 1,
890565 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
891566 		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
892567 		.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
....@@ -911,7 +586,6 @@
911586 		.reg_list = imx335_hdr3_10bit_2592x1944_regs,
912587 		.hdr_mode = HDR_X3,
913588 		.bpp = 10,
914
-		.mipi_freq_idx = 1,
915589 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
916590 		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
917591 		.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
....@@ -920,7 +594,6 @@
920594 };
921595 
922596 static const s64 link_freq_items[] = {
923
-	MIPI_FREQ_445M,
924597 	MIPI_FREQ_594M,
925598 };
926599 
....@@ -1044,7 +717,6 @@
1044717 	struct imx335 *imx335 = to_imx335(sd);
1045718 	const struct imx335_mode *mode;
1046719 	s64 h_blank, vblank_def;
1047
-	s64 dst_pixel_rate = 0;
1048720 
1049721 	mutex_lock(&imx335->mutex);
1050722 
....@@ -1065,12 +737,6 @@
1065737 		__v4l2_ctrl_modify_range(imx335->vblank, vblank_def,
1066738 					 IMX335_VTS_MAX - mode->height,
1067739 					 1, vblank_def);
1068
-		dst_pixel_rate = ((u32)link_freq_items[mode->mipi_freq_idx]) /
1069
-				  mode->bpp * 2 * IMX335_4LANES;
1070
-		__v4l2_ctrl_s_ctrl_int64(imx335->pixel_rate,
1071
-					 dst_pixel_rate);
1072
-		__v4l2_ctrl_s_ctrl(imx335->link_freq,
1073
-				   mode->mipi_freq_idx);
1074740 	}
1075741 
1076742 	mutex_unlock(&imx335->mutex);
....@@ -1142,14 +808,12 @@
1142808 	struct imx335 *imx335 = to_imx335(sd);
1143809 	const struct imx335_mode *mode = imx335->cur_mode;
1144810 
1145
-	mutex_lock(&imx335->mutex);
1146811 	fi->interval = mode->max_fps;
1147
-	mutex_unlock(&imx335->mutex);
1148812 
1149813 	return 0;
1150814 }
1151815 
1152
-static int imx335_g_mbus_config(struct v4l2_subdev *sd,
816
+static int imx335_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1153817 				struct v4l2_mbus_config *config)
1154818 {
1155819 	u32 val = 0;
....@@ -1163,7 +827,7 @@
1163827 		val |= V4L2_MBUS_CSI2_CHANNEL_1;
1164828 	if (mode->hdr_mode == HDR_X3)
1165829 		val |= V4L2_MBUS_CSI2_CHANNEL_2;
1166
-	config->type = V4L2_MBUS_CSI2;
830
+	config->type = V4L2_MBUS_CSI2_DPHY;
1167831 	config->flags = val;
1168832 
1169833 	return 0;
....@@ -1261,7 +925,7 @@
1261925 	}
1262926 
1263927 	rhs1 = SHR1_MIN + s_exp_time;
1264
-	rhs1 = (rhs1 + 7u) / 8 * 8 + 2; /* shall be 8n + 2 */
928
+	rhs1 = (rhs1 & ~0x7) + 2; /* shall be 8n + 2 */
1265929 	if (rhs1 > rhs1_max)
1266930 		rhs1 = rhs1_max;
1267931 	if (rhs1 < rhs1_min)
....@@ -1591,7 +1255,6 @@
15911255 	u32 i, h, w;
15921256 	long ret = 0;
15931257 	u32 stream = 0;
1594
-	s64 dst_pixel_rate = 0;
15951258 
15961259 	switch (cmd) {
15971260 	case PREISP_CMD_SET_HDRAE_EXP:
....@@ -1632,12 +1295,6 @@
16321295 			__v4l2_ctrl_modify_range(imx335->vblank, h,
16331296 				IMX335_VTS_MAX - imx335->cur_mode->height,
16341297 				1, h);
1635
-			dst_pixel_rate = ((u32)link_freq_items[imx335->cur_mode->mipi_freq_idx]) /
1636
-				  imx335->cur_mode->bpp * 2 * IMX335_4LANES;
1637
-			__v4l2_ctrl_s_ctrl_int64(imx335->pixel_rate,
1638
-						 dst_pixel_rate);
1639
-			__v4l2_ctrl_s_ctrl(imx335->link_freq,
1640
-					   imx335->cur_mode->mipi_freq_idx);
16411298 		}
16421299 		break;
16431300 	case RKMODULE_SET_QUICK_STREAM:
....@@ -1650,12 +1307,6 @@
16501307 		else
16511308 			imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
16521309 				IMX335_REG_VALUE_08BIT, 1);
1653
-		break;
1654
-	case RKMODULE_GET_READOUT_LINE_CNT_PER_LINE:
1655
-		if (imx335->cur_mode->width == 2616 && imx335->cur_mode->height == 1964)
1656
-			*((u32 *)arg) = 2;
1657
-		else
1658
-			*((u32 *)arg) = 4;
16591310 		break;
16601311 	default:
16611312 		ret = -ENOIOCTLCMD;
....@@ -1676,7 +1327,6 @@
16761327 	struct preisp_hdrae_exp_s *hdrae;
16771328 	long ret;
16781329 	u32 stream = 0;
1679
-	u32 readout = 0;
16801330 
16811331 	switch (cmd) {
16821332 	case RKMODULE_GET_MODULE_INFO:
....@@ -1687,10 +1337,8 @@
16871337 		}
16881338 
16891339 		ret = imx335_ioctl(sd, cmd, inf);
1690
-		if (!ret) {
1691
-			if (copy_to_user(up, inf, sizeof(*inf)))
1692
-				ret = -EFAULT;
1693
-		}
1340
+		if (!ret)
1341
+			ret = copy_to_user(up, inf, sizeof(*inf));
16941342 		kfree(inf);
16951343 		break;
16961344 	case RKMODULE_AWB_CFG:
....@@ -1703,8 +1351,6 @@
17031351 		ret = copy_from_user(cfg, up, sizeof(*cfg));
17041352 		if (!ret)
17051353 			ret = imx335_ioctl(sd, cmd, cfg);
1706
-		else
1707
-			ret = -EFAULT;
17081354 		kfree(cfg);
17091355 		break;
17101356 	case RKMODULE_GET_HDR_CFG:
....@@ -1715,10 +1361,8 @@
17151361 		}
17161362 
17171363 		ret = imx335_ioctl(sd, cmd, hdr);
1718
-		if (!ret) {
1719
-			if (copy_to_user(up, hdr, sizeof(*hdr)))
1720
-				ret = -EFAULT;
1721
-		}
1364
+		if (!ret)
1365
+			ret = copy_to_user(up, hdr, sizeof(*hdr));
17221366 		kfree(hdr);
17231367 		break;
17241368 	case RKMODULE_SET_HDR_CFG:
....@@ -1731,8 +1375,6 @@
17311375 		ret = copy_from_user(hdr, up, sizeof(*hdr));
17321376 		if (!ret)
17331377 			ret = imx335_ioctl(sd, cmd, hdr);
1734
-		else
1735
-			ret = -EFAULT;
17361378 		kfree(hdr);
17371379 		break;
17381380 	case PREISP_CMD_SET_HDRAE_EXP:
....@@ -1745,23 +1387,12 @@
17451387 		ret = copy_from_user(hdrae, up, sizeof(*hdrae));
17461388 		if (!ret)
17471389 			ret = imx335_ioctl(sd, cmd, hdrae);
1748
-		else
1749
-			ret = -EFAULT;
17501390 		kfree(hdrae);
17511391 		break;
17521392 	case RKMODULE_SET_QUICK_STREAM:
17531393 		ret = copy_from_user(&stream, up, sizeof(u32));
17541394 		if (!ret)
17551395 			ret = imx335_ioctl(sd, cmd, &stream);
1756
-		else
1757
-			ret = -EFAULT;
1758
-		break;
1759
-	case RKMODULE_GET_READOUT_LINE_CNT_PER_LINE:
1760
-		ret = imx335_ioctl(sd, cmd, &readout);
1761
-		if (!ret) {
1762
-			if (copy_to_user(up, &readout, sizeof(u32)))
1763
-				ret = -EFAULT;
1764
-		}
17651396 		break;
17661397 	default:
17671398 		ret = -ENOIOCTLCMD;
....@@ -2005,8 +1636,6 @@
20051636 
20061637 #define DST_WIDTH 2592
20071638 #define DST_HEIGHT 1944
2008
-#define BINNING_WIDTH 1296
2009
-#define BINNING_HEIGHT 972
20101639 
20111640 /*
20121641  * The resolution of the driver configuration needs to be exactly
....@@ -2021,23 +1650,15 @@
20211650 				struct v4l2_subdev_pad_config *cfg,
20221651 				struct v4l2_subdev_selection *sel)
20231652 {
2024
-	struct imx335 *imx335 = to_imx335(sd);
20251653 	/*
20261654 	 * From "Pixel Array Image Drawing in All scan mode",
20271655 	 * there are 12 pixel offset on horizontal and vertical.
20281656 	 */
20291657 	if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
2030
-		if (imx335->cur_mode->width == 2616 && imx335->cur_mode->height == 1964) {
2031
-			sel->r.left = 12;
2032
-			sel->r.width = DST_WIDTH;
2033
-			sel->r.top = 12;
2034
-			sel->r.height = DST_HEIGHT;
2035
-		} else {
2036
-			sel->r.left = 4;
2037
-			sel->r.width = BINNING_WIDTH;
2038
-			sel->r.top = 8;
2039
-			sel->r.height = BINNING_HEIGHT;
2040
-		}
1658
+		sel->r.left = 12;
1659
+		sel->r.width = DST_WIDTH;
1660
+		sel->r.top = 12;
1661
+		sel->r.height = DST_HEIGHT;
20411662 		return 0;
20421663 	}
20431664 	return -EINVAL;
....@@ -2063,7 +1684,6 @@
20631684 static const struct v4l2_subdev_video_ops imx335_video_ops = {
20641685 	.s_stream = imx335_s_stream,
20651686 	.g_frame_interval = imx335_g_frame_interval,
2066
-	.g_mbus_config = imx335_g_mbus_config,
20671687 };
20681688 
20691689 static const struct v4l2_subdev_pad_ops imx335_pad_ops = {
....@@ -2073,6 +1693,7 @@
20731693 	.get_fmt = imx335_get_fmt,
20741694 	.set_fmt = imx335_set_fmt,
20751695 	.get_selection = imx335_get_selection,
1696
+	.get_mbus_config = imx335_g_mbus_config,
20761697 };
20771698 
20781699 static const struct v4l2_subdev_ops imx335_subdev_ops = {
....@@ -2111,7 +1732,7 @@
21111732 	switch (ctrl->id) {
21121733 	case V4L2_CID_EXPOSURE:
21131734 		if (imx335->cur_mode->hdr_mode != NO_HDR)
2114
-			return ret;
1735
+			goto ctrl_end;
21151736 		shr0 = imx335->cur_vts - ctrl->val;
21161737 		ret = imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_L,
21171738 				       IMX335_REG_VALUE_08BIT,
....@@ -2127,7 +1748,7 @@
21271748 		break;
21281749 	case V4L2_CID_ANALOGUE_GAIN:
21291750 		if (imx335->cur_mode->hdr_mode != NO_HDR)
2130
-			return ret;
1751
+			goto ctrl_end;
21311752 		ret = imx335_write_reg(imx335->client, IMX335_LF_GAIN_REG_H,
21321753 				       IMX335_REG_VALUE_08BIT,
21331754 				       IMX335_FETCH_GAIN_H(ctrl->val));
....@@ -2166,269 +1787,39 @@
21661787 		break;
21671788 	case V4L2_CID_HFLIP:
21681789 		ret = imx335_write_reg(imx335->client, IMX335_HREVERSE_REG,
2169
-				       IMX335_REG_VALUE_08BIT, ctrl->val);
1790
+				       IMX335_REG_VALUE_08BIT, !!ctrl->val);
21701791 		break;
21711792 	case V4L2_CID_VFLIP:
21721793 		if (ctrl->val) {
21731794 			ret = imx335_write_reg(imx335->client, IMX335_VREVERSE_REG,
2174
-					       IMX335_REG_VALUE_08BIT, ctrl->val);
2175
-			if (imx335->cur_mode->width == 2616 && imx335->cur_mode->height == 1964) {
2176
-				ret |= imx335_write_reg(imx335->client, 0x3078,
2177
-						IMX335_REG_VALUE_08BIT, 0x01);
2178
-				ret |= imx335_write_reg(imx335->client, 0x3079,
2179
-						IMX335_REG_VALUE_08BIT, 0x02);
2180
-				ret |= imx335_write_reg(imx335->client, 0x307a,
2181
-						IMX335_REG_VALUE_08BIT, 0xff);
2182
-				ret |= imx335_write_reg(imx335->client, 0x307b,
2183
-						IMX335_REG_VALUE_08BIT, 0x02);
2184
-				ret |= imx335_write_reg(imx335->client, 0x307c,
2185
-						IMX335_REG_VALUE_08BIT, 0x00);
2186
-				ret |= imx335_write_reg(imx335->client, 0x307d,
2187
-						IMX335_REG_VALUE_08BIT, 0x00);
2188
-				ret |= imx335_write_reg(imx335->client, 0x307e,
2189
-						IMX335_REG_VALUE_08BIT, 0x00);
2190
-				ret |= imx335_write_reg(imx335->client, 0x307f,
2191
-						IMX335_REG_VALUE_08BIT, 0x00);
2192
-				ret |= imx335_write_reg(imx335->client, 0x3080,
2193
-						IMX335_REG_VALUE_08BIT, 0x01);
2194
-				ret |= imx335_write_reg(imx335->client, 0x3081,
2195
-						IMX335_REG_VALUE_08BIT, 0xfe);
2196
-				ret |= imx335_write_reg(imx335->client, 0x3082,
2197
-						IMX335_REG_VALUE_08BIT, 0xff);
2198
-				ret |= imx335_write_reg(imx335->client, 0x3083,
2199
-						IMX335_REG_VALUE_08BIT, 0xfe);
2200
-				ret |= imx335_write_reg(imx335->client, 0x3084,
2201
-						IMX335_REG_VALUE_08BIT, 0x00);
2202
-				ret |= imx335_write_reg(imx335->client, 0x3085,
2203
-						IMX335_REG_VALUE_08BIT, 0x00);
2204
-				ret |= imx335_write_reg(imx335->client, 0x3086,
2205
-						IMX335_REG_VALUE_08BIT, 0x00);
2206
-				ret |= imx335_write_reg(imx335->client, 0x3087,
2207
-						IMX335_REG_VALUE_08BIT, 0x00);
2208
-				ret |= imx335_write_reg(imx335->client, 0x30a4,
2209
-						IMX335_REG_VALUE_08BIT, 0x33);
2210
-				ret |= imx335_write_reg(imx335->client, 0x30a8,
2211
-						IMX335_REG_VALUE_08BIT, 0x10);
2212
-				ret |= imx335_write_reg(imx335->client, 0x30a9,
2213
-						IMX335_REG_VALUE_08BIT, 0x04);
2214
-				ret |= imx335_write_reg(imx335->client, 0x30ac,
2215
-						IMX335_REG_VALUE_08BIT, 0x00);
2216
-				ret |= imx335_write_reg(imx335->client, 0x30ad,
2217
-						IMX335_REG_VALUE_08BIT, 0x00);
2218
-				ret |= imx335_write_reg(imx335->client, 0x30b0,
2219
-						IMX335_REG_VALUE_08BIT, 0x10);
2220
-				ret |= imx335_write_reg(imx335->client, 0x30b1,
2221
-						IMX335_REG_VALUE_08BIT, 0x08);
2222
-				ret |= imx335_write_reg(imx335->client, 0x30b4,
2223
-						IMX335_REG_VALUE_08BIT, 0x00);
2224
-				ret |= imx335_write_reg(imx335->client, 0x30b5,
2225
-						IMX335_REG_VALUE_08BIT, 0x00);
2226
-				ret |= imx335_write_reg(imx335->client, 0x30b6,
2227
-						IMX335_REG_VALUE_08BIT, 0xfa);
2228
-				ret |= imx335_write_reg(imx335->client, 0x30b7,
2229
-						IMX335_REG_VALUE_08BIT, 0x01);
2230
-				ret |= imx335_write_reg(imx335->client, 0x3112,
2231
-						IMX335_REG_VALUE_08BIT, 0x08);
2232
-				ret |= imx335_write_reg(imx335->client, 0x3113,
2233
-						IMX335_REG_VALUE_08BIT, 0x00);
2234
-				ret |= imx335_write_reg(imx335->client, 0x3116,
2235
-						IMX335_REG_VALUE_08BIT, 0x02);
2236
-				ret |= imx335_write_reg(imx335->client, 0x3117,
2237
-						IMX335_REG_VALUE_08BIT, 0x00);
2238
-			} else {
2239
-				ret |= imx335_write_reg(imx335->client, 0x3078,
2240
-						IMX335_REG_VALUE_08BIT, 0x04);
2241
-				ret |= imx335_write_reg(imx335->client, 0x3079,
2242
-						IMX335_REG_VALUE_08BIT, 0xfd);
2243
-				ret |= imx335_write_reg(imx335->client, 0x307a,
2244
-						IMX335_REG_VALUE_08BIT, 0x04);
2245
-				ret |= imx335_write_reg(imx335->client, 0x307b,
2246
-						IMX335_REG_VALUE_08BIT, 0xfe);
2247
-				ret |= imx335_write_reg(imx335->client, 0x307c,
2248
-						IMX335_REG_VALUE_08BIT, 0x04);
2249
-				ret |= imx335_write_reg(imx335->client, 0x307d,
2250
-						IMX335_REG_VALUE_08BIT, 0xfb);
2251
-				ret |= imx335_write_reg(imx335->client, 0x307e,
2252
-						IMX335_REG_VALUE_08BIT, 0x04);
2253
-				ret |= imx335_write_reg(imx335->client, 0x307f,
2254
-						IMX335_REG_VALUE_08BIT, 0x02);
2255
-				ret |= imx335_write_reg(imx335->client, 0x3080,
2256
-						IMX335_REG_VALUE_08BIT, 0xfc);
2257
-				ret |= imx335_write_reg(imx335->client, 0x3081,
2258
-						IMX335_REG_VALUE_08BIT, 0x05);
2259
-				ret |= imx335_write_reg(imx335->client, 0x3082,
2260
-						IMX335_REG_VALUE_08BIT, 0xfc);
2261
-				ret |= imx335_write_reg(imx335->client, 0x3083,
2262
-						IMX335_REG_VALUE_08BIT, 0x02);
2263
-				ret |= imx335_write_reg(imx335->client, 0x3084,
2264
-						IMX335_REG_VALUE_08BIT, 0xfc);
2265
-				ret |= imx335_write_reg(imx335->client, 0x3085,
2266
-						IMX335_REG_VALUE_08BIT, 0x03);
2267
-				ret |= imx335_write_reg(imx335->client, 0x3086,
2268
-						IMX335_REG_VALUE_08BIT, 0xfc);
2269
-				ret |= imx335_write_reg(imx335->client, 0x3087,
2270
-						IMX335_REG_VALUE_08BIT, 0xfe);
2271
-				ret |= imx335_write_reg(imx335->client, 0x30a4,
2272
-						IMX335_REG_VALUE_08BIT, 0x77);
2273
-				ret |= imx335_write_reg(imx335->client, 0x30a8,
2274
-						IMX335_REG_VALUE_08BIT, 0x20);
2275
-				ret |= imx335_write_reg(imx335->client, 0x30a9,
2276
-						IMX335_REG_VALUE_08BIT, 0x00);
2277
-				ret |= imx335_write_reg(imx335->client, 0x30ac,
2278
-						IMX335_REG_VALUE_08BIT, 0x08);
2279
-				ret |= imx335_write_reg(imx335->client, 0x30ad,
2280
-						IMX335_REG_VALUE_08BIT, 0x78);
2281
-				ret |= imx335_write_reg(imx335->client, 0x30b0,
2282
-						IMX335_REG_VALUE_08BIT, 0x20);
2283
-				ret |= imx335_write_reg(imx335->client, 0x30b1,
2284
-						IMX335_REG_VALUE_08BIT, 0x00);
2285
-				ret |= imx335_write_reg(imx335->client, 0x30b4,
2286
-						IMX335_REG_VALUE_08BIT, 0x10);
2287
-				ret |= imx335_write_reg(imx335->client, 0x30b5,
2288
-						IMX335_REG_VALUE_08BIT, 0x70);
2289
-				ret |= imx335_write_reg(imx335->client, 0x30b6,
2290
-						IMX335_REG_VALUE_08BIT, 0xf2);
2291
-				ret |= imx335_write_reg(imx335->client, 0x30b7,
2292
-						IMX335_REG_VALUE_08BIT, 0x01);
2293
-				ret |= imx335_write_reg(imx335->client, 0x3112,
2294
-						IMX335_REG_VALUE_08BIT, 0x10);
2295
-				ret |= imx335_write_reg(imx335->client, 0x3113,
2296
-						IMX335_REG_VALUE_08BIT, 0x00);
2297
-				ret |= imx335_write_reg(imx335->client, 0x3116,
2298
-						IMX335_REG_VALUE_08BIT, 0x02);
2299
-				ret |= imx335_write_reg(imx335->client, 0x3117,
2300
-						IMX335_REG_VALUE_08BIT, 0x00);
2301
-			}
1795
+					       IMX335_REG_VALUE_08BIT, !!ctrl->val);
1796
+			ret |= imx335_write_reg(imx335->client, 0x3081,
1797
+					       IMX335_REG_VALUE_08BIT, 0xfe);
1798
+			ret |= imx335_write_reg(imx335->client, 0x3083,
1799
+					       IMX335_REG_VALUE_08BIT, 0xfe);
1800
+			ret |= imx335_write_reg(imx335->client, 0x30b6,
1801
+					       IMX335_REG_VALUE_08BIT, 0xfa);
1802
+			ret |= imx335_write_reg(imx335->client, 0x30b7,
1803
+					       IMX335_REG_VALUE_08BIT, 0x01);
1804
+			ret |= imx335_write_reg(imx335->client, 0x3116,
1805
+					       IMX335_REG_VALUE_08BIT, 0x02);
1806
+			ret |= imx335_write_reg(imx335->client, 0x3117,
1807
+					       IMX335_REG_VALUE_08BIT, 0x00);
23021808 		} else {
23031809 			ret = imx335_write_reg(imx335->client, IMX335_VREVERSE_REG,
2304
-					       IMX335_REG_VALUE_08BIT, ctrl->val);
2305
-			if (imx335->cur_mode->width == 2616 && imx335->cur_mode->height == 1964) {
2306
-				ret |= imx335_write_reg(imx335->client, 0x3078,
2307
-						IMX335_REG_VALUE_08BIT, 0x01);
2308
-				ret |= imx335_write_reg(imx335->client, 0x3079,
2309
-						IMX335_REG_VALUE_08BIT, 0x02);
2310
-				ret |= imx335_write_reg(imx335->client, 0x307a,
2311
-						IMX335_REG_VALUE_08BIT, 0xff);
2312
-				ret |= imx335_write_reg(imx335->client, 0x307b,
2313
-						IMX335_REG_VALUE_08BIT, 0x02);
2314
-				ret |= imx335_write_reg(imx335->client, 0x307c,
2315
-						IMX335_REG_VALUE_08BIT, 0x00);
2316
-				ret |= imx335_write_reg(imx335->client, 0x307d,
2317
-						IMX335_REG_VALUE_08BIT, 0x00);
2318
-				ret |= imx335_write_reg(imx335->client, 0x307e,
2319
-						IMX335_REG_VALUE_08BIT, 0x00);
2320
-				ret |= imx335_write_reg(imx335->client, 0x307f,
2321
-						IMX335_REG_VALUE_08BIT, 0x00);
2322
-				ret |= imx335_write_reg(imx335->client, 0x3080,
2323
-						IMX335_REG_VALUE_08BIT, 0x01);
2324
-				ret |= imx335_write_reg(imx335->client, 0x3081,
2325
-						IMX335_REG_VALUE_08BIT, 0x02);
2326
-				ret |= imx335_write_reg(imx335->client, 0x3082,
2327
-						IMX335_REG_VALUE_08BIT, 0xff);
2328
-				ret |= imx335_write_reg(imx335->client, 0x3083,
2329
-						IMX335_REG_VALUE_08BIT, 0x02);
2330
-				ret |= imx335_write_reg(imx335->client, 0x3084,
2331
-						IMX335_REG_VALUE_08BIT, 0x00);
2332
-				ret |= imx335_write_reg(imx335->client, 0x3085,
2333
-						IMX335_REG_VALUE_08BIT, 0x00);
2334
-				ret |= imx335_write_reg(imx335->client, 0x3086,
2335
-						IMX335_REG_VALUE_08BIT, 0x00);
2336
-				ret |= imx335_write_reg(imx335->client, 0x3087,
2337
-						IMX335_REG_VALUE_08BIT, 0x00);
2338
-				ret |= imx335_write_reg(imx335->client, 0x30a4,
2339
-						IMX335_REG_VALUE_08BIT, 0x33);
2340
-				ret |= imx335_write_reg(imx335->client, 0x30a8,
2341
-						IMX335_REG_VALUE_08BIT, 0x10);
2342
-				ret |= imx335_write_reg(imx335->client, 0x30a9,
2343
-						IMX335_REG_VALUE_08BIT, 0x04);
2344
-				ret |= imx335_write_reg(imx335->client, 0x30ac,
2345
-						IMX335_REG_VALUE_08BIT, 0x00);
2346
-				ret |= imx335_write_reg(imx335->client, 0x30ad,
2347
-						IMX335_REG_VALUE_08BIT, 0x00);
2348
-				ret |= imx335_write_reg(imx335->client, 0x30b0,
2349
-						IMX335_REG_VALUE_08BIT, 0x10);
2350
-				ret |= imx335_write_reg(imx335->client, 0x30b1,
2351
-						IMX335_REG_VALUE_08BIT, 0x08);
2352
-				ret |= imx335_write_reg(imx335->client, 0x30b4,
2353
-						IMX335_REG_VALUE_08BIT, 0x00);
2354
-				ret |= imx335_write_reg(imx335->client, 0x30b5,
2355
-						IMX335_REG_VALUE_08BIT, 0x00);
2356
-				ret |= imx335_write_reg(imx335->client, 0x30b6,
2357
-						IMX335_REG_VALUE_08BIT, 0x00);
2358
-				ret |= imx335_write_reg(imx335->client, 0x30b7,
2359
-						IMX335_REG_VALUE_08BIT, 0x00);
2360
-				ret |= imx335_write_reg(imx335->client, 0x3112,
2361
-						IMX335_REG_VALUE_08BIT, 0x08);
2362
-				ret |= imx335_write_reg(imx335->client, 0x3113,
2363
-						IMX335_REG_VALUE_08BIT, 0x00);
2364
-				ret |= imx335_write_reg(imx335->client, 0x3116,
2365
-						IMX335_REG_VALUE_08BIT, 0x08);
2366
-				ret |= imx335_write_reg(imx335->client, 0x3117,
2367
-						IMX335_REG_VALUE_08BIT, 0x00);
2368
-			} else {
2369
-				ret |= imx335_write_reg(imx335->client, 0x3078,
2370
-						IMX335_REG_VALUE_08BIT, 0x04);
2371
-				ret |= imx335_write_reg(imx335->client, 0x3079,
2372
-						IMX335_REG_VALUE_08BIT, 0xfd);
2373
-				ret |= imx335_write_reg(imx335->client, 0x307a,
2374
-						IMX335_REG_VALUE_08BIT, 0x04);
2375
-				ret |= imx335_write_reg(imx335->client, 0x307b,
2376
-						IMX335_REG_VALUE_08BIT, 0xfe);
2377
-				ret |= imx335_write_reg(imx335->client, 0x307c,
2378
-						IMX335_REG_VALUE_08BIT, 0x04);
2379
-				ret |= imx335_write_reg(imx335->client, 0x307d,
2380
-						IMX335_REG_VALUE_08BIT, 0xfb);
2381
-				ret |= imx335_write_reg(imx335->client, 0x307e,
2382
-						IMX335_REG_VALUE_08BIT, 0x04);
2383
-				ret |= imx335_write_reg(imx335->client, 0x307f,
2384
-						IMX335_REG_VALUE_08BIT, 0x02);
2385
-				ret |= imx335_write_reg(imx335->client, 0x3080,
2386
-						IMX335_REG_VALUE_08BIT, 0x04);
2387
-				ret |= imx335_write_reg(imx335->client, 0x3081,
2388
-						IMX335_REG_VALUE_08BIT, 0xfd);
2389
-				ret |= imx335_write_reg(imx335->client, 0x3082,
2390
-						IMX335_REG_VALUE_08BIT, 0x04);
2391
-				ret |= imx335_write_reg(imx335->client, 0x3083,
2392
-						IMX335_REG_VALUE_08BIT, 0xfe);
2393
-				ret |= imx335_write_reg(imx335->client, 0x3084,
2394
-						IMX335_REG_VALUE_08BIT, 0x04);
2395
-				ret |= imx335_write_reg(imx335->client, 0x3085,
2396
-						IMX335_REG_VALUE_08BIT, 0xfb);
2397
-				ret |= imx335_write_reg(imx335->client, 0x3086,
2398
-						IMX335_REG_VALUE_08BIT, 0x04);
2399
-				ret |= imx335_write_reg(imx335->client, 0x3087,
2400
-						IMX335_REG_VALUE_08BIT, 0x02);
2401
-				ret |= imx335_write_reg(imx335->client, 0x30a4,
2402
-						IMX335_REG_VALUE_08BIT, 0x77);
2403
-				ret |= imx335_write_reg(imx335->client, 0x30a8,
2404
-						IMX335_REG_VALUE_08BIT, 0x20);
2405
-				ret |= imx335_write_reg(imx335->client, 0x30a9,
2406
-						IMX335_REG_VALUE_08BIT, 0x00);
2407
-				ret |= imx335_write_reg(imx335->client, 0x30ac,
2408
-						IMX335_REG_VALUE_08BIT, 0x08);
2409
-				ret |= imx335_write_reg(imx335->client, 0x30ad,
2410
-						IMX335_REG_VALUE_08BIT, 0x08);
2411
-				ret |= imx335_write_reg(imx335->client, 0x30b0,
2412
-						IMX335_REG_VALUE_08BIT, 0x20);
2413
-				ret |= imx335_write_reg(imx335->client, 0x30b1,
2414
-						IMX335_REG_VALUE_08BIT, 0x00);
2415
-				ret |= imx335_write_reg(imx335->client, 0x30b4,
2416
-						IMX335_REG_VALUE_08BIT, 0x10);
2417
-				ret |= imx335_write_reg(imx335->client, 0x30b5,
2418
-						IMX335_REG_VALUE_08BIT, 0x10);
2419
-				ret |= imx335_write_reg(imx335->client, 0x30b6,
2420
-						IMX335_REG_VALUE_08BIT, 0x00);
2421
-				ret |= imx335_write_reg(imx335->client, 0x30b7,
2422
-						IMX335_REG_VALUE_08BIT, 0x00);
2423
-				ret |= imx335_write_reg(imx335->client, 0x3112,
2424
-						IMX335_REG_VALUE_08BIT, 0x10);
2425
-				ret |= imx335_write_reg(imx335->client, 0x3113,
2426
-						IMX335_REG_VALUE_08BIT, 0x00);
2427
-				ret |= imx335_write_reg(imx335->client, 0x3116,
2428
-						IMX335_REG_VALUE_08BIT, 0x10);
2429
-				ret |= imx335_write_reg(imx335->client, 0x3117,
2430
-						IMX335_REG_VALUE_08BIT, 0x00);
2431
-			}
1810
+					       IMX335_REG_VALUE_08BIT, !!ctrl->val);
1811
+			ret |= imx335_write_reg(imx335->client, 0x3081,
1812
+					       IMX335_REG_VALUE_08BIT, 0x02);
1813
+			ret |= imx335_write_reg(imx335->client, 0x3083,
1814
+					       IMX335_REG_VALUE_08BIT, 0x02);
1815
+			ret |= imx335_write_reg(imx335->client, 0x30b6,
1816
+					       IMX335_REG_VALUE_08BIT, 0x00);
1817
+			ret |= imx335_write_reg(imx335->client, 0x30b7,
1818
+					       IMX335_REG_VALUE_08BIT, 0x00);
1819
+			ret |= imx335_write_reg(imx335->client, 0x3116,
1820
+					       IMX335_REG_VALUE_08BIT, 0x08);
1821
+			ret |= imx335_write_reg(imx335->client, 0x3117,
1822
+					       IMX335_REG_VALUE_08BIT, 0x00);
24321823 		}
24331824 		break;
24341825 	default:
....@@ -2437,6 +1828,7 @@
24371828 		break;
24381829 	}
24391830 
1831
+ctrl_end:
24401832 	pm_runtime_put(&client->dev);
24411833 
24421834 	return ret;
....@@ -2468,7 +1860,7 @@
24681860 				link_freq_items);
24691861 
24701862 	/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2471
-	pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * IMX335_4LANES;
1863
+	pixel_rate = (u32)link_freq_items[0] / mode->bpp * 2 * IMX335_4LANES;
24721864 	imx335->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
24731865 		V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, pixel_rate);
24741866